CN101771525B - High-speed digital communication line error code detection device and method - Google Patents
High-speed digital communication line error code detection device and method Download PDFInfo
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Abstract
The invention relates to high-speed digital communication line error code detection device and method. The high-speed digital communication line error code detection device comprises a pseudorandom sequence generation circuit I, a pseudorandom sequence generation circuit II, a register, a control circuit, a comparison circuit and an error code counter. In the high-speed digital communication lien error code detection method, the pseudorandom sequence generation circuit I and the pseudorandom sequence generation circuit II directly generate parallel pseudorandom sequence codes which are directly output to a line; the parallel pseudorandom sequence codes after being output can be looped into an input channel from an external circuit and also can be input into the input channel through a signal generated by the pseudorandom sequence generation circuit in an opposite side transmitting terminal; and the input signal is taken as a feedback signal of the pseudorandom sequence generation circuit, input into a new pseudorandom sequence generated in the pseudorandom sequence generation circuit and then compared with a signal received in a next clock period so as to judge whether error codes generate or not. The invention can carry out error code detection on a great deal of channels very flexibly and conveniently, is simple to implement the circuit and can be suitable for various occasions.
Description
(1) technical field
The present invention relates to numeral exchange and transmission system, comprise (SONET, SDH, Ethernet etc.), particularly use the pseudo-random binary sequence code to carry out applied in network performance test.
(2) background technology
Error detection is the measurement means a kind of commonly used in the digital communication, no matter is at wire communication or in wireless telecommunications, for the error code of determining to produce in numeral exchange or the Digital Transmission process, must carry out Error detection to numeral exchange and transmission circuit.
In digital communications network, for the performance of test network, usually can in the transmission of data, insert the error rate detection that pseudo-random binary sequence PRBS (Pseudo Random Binary Sequence) code carries out network.PRBS is a relevant number series, for the generator of this number series, knows that previous code value just can determine a rear code value.Such as an integer sequence generator, can produce 1,2,3.4,5 ... number series.When we will produce current code value, as long as tell that its front code value once is 5, it just can produce 6.And pass through to detect this sequence at receiving device, just can know whether that error code produces.
The Chinese patent application of application number 02151119.5 " device for detecting code error of digital exchange system and method ", the device for detecting code error of a kind of digital exchange system that this invention provides, comprise a m sequencer, serial-parallel conversion circuit, error code receiving circuit, shift register, the 2nd m sequencer, control circuit, comparison circuit and error code counter.The m sequencer produces the m sequence pseudo random code of serial, through string and convert the parallel data identical with exchanging channel width (being generally 8bit) to, control circuit joins this parallel data on the delivery channel of different error codes to be detected, be looped back to input channel by external circuit after the output, whether device for detecting code error is the judgement of pseudo noise code to the input data of loopback again.But this checkout gear and method can only be carried out loopback test, namely by external cable or optical fiber hoop being got back to the local device input after the output of this device signal detects, carry out whole transmission channel is carried out Error detection and can not be transferred to remote equipment by communication network, so range of application is very limited.What the random sequence generator in the described device for detecting code error of this application produced in addition is the serial random sequence, and this method can only be applicable in the lower communication line of speed.For in (baud rate is greater than 1Gbps) digital communication system at a high speed, if still with as above structure generation serial random sequence, can greatly increase design difficulty and the cost of circuit.
(3) summary of the invention
Technical problem to be solved by this invention is as high-speed digital communication line provides a kind of device for detecting code error and method, solves existing high-speed digital communication line can not carry out Error detection cheaply to whole networking circuit problem.
The invention provides a kind of high-speed digital communication line error code detection device, comprise error code counter, pseudorandom sequences generation I, pseudorandom sequences generation II, register, control circuit and comparison circuit,
Described error code counter, in order to calculate the error code number of times, its structure is:
When a) receiving the reset signal of control circuit generation, this counter O reset.
When b) receiving the pulse signal of comparison circuit generation, this counter adds one.
Described pseudorandom sequences generation I, in order to produce a pseudo random sequence data pattern in an integrated circuit, high-speed digital communication line error code detection device will send this pseudo random sequence, in order to the detection line error rate.Above-mentioned pseudorandom sequences generation I, its structure is:
A) pseudorandom sequences generation of standard all comprises a n level linear feedback shift register, and the pseudorandom sequences generation I among the present invention does not comprise n level linear feedback shift register, but form with the m group XOR that input and output are the m position, wherein m is the parallel data width.
B) initial value of this pseudorandom sequences generation I is the binary number of full m position complete 1.
C) this pseudorandom sequences generation I inputs the result of calculation of oneself as value of feedback, and do not use initial value this moment when this pseudorandom sequences generation I calculates, but produces the output valve of the pseudo random sequence of next clock cycle with value of feedback.
Described pseudorandom sequences generation II, in order in an integrated circuit, to produce a pseudo random sequence data pattern, high-speed digital communication line error code detection device will arrive pseudorandom sequences generation II to the sequence that receives as feed back input, produces new pseudo random sequence.Above-mentioned pseudorandom sequences generation II, its structure is:
A) pseudorandom sequences generation of standard all comprises a n level linear feedback shift register, and the pseudorandom sequences generation II among the present invention does not comprise n level linear feedback shift register, but form with the m group XOR that input and output are the m position, wherein m is the parallel data width.And it is identical to organize the described pseudorandom sequences generation I of logical AND.
The initial value of this pseudorandom sequences generation II is the binary number of full m position complete 1.
This pseudorandom sequences generation II does not input the result of calculation of oneself as value of feedback.But with the input value of current channel as value of feedback, generate the input of calculating in order to pseudo random sequence.
Described register is in order to pseudo random sequence clock cycle of storage that pseudorandom sequences generation II is generated.
Described control circuit in order to control pseudorandom sequences generation I, pseudorandom sequences generation II and error code counter, comprises that pseudorandom sequences generation resets, the functions such as error code counter zero clearing.Its structure is:
A) reset signal of generation pseudorandom sequences generation I, this signal makes pseudorandom sequences generation I get back to initial condition.
B) reset signal of generation pseudorandom sequences generation II, this signal makes pseudorandom sequences generation II get back to initial condition.
C) reset signal of generation error code counter, this signal make the zero clearing of error code counting.
Described comparison circuit is the m bit comparator of a standard, and wherein m is the parallel data width, in order to the sequence that produces among the data that relatively receive and the pseudorandom sequences generation II.If both are unequal, then produce a pulse signal requirement error code counter and add one.
According to another aspect of the present invention, provide a kind of high-speed digital communication line error code detection method, said method comprising the steps of:
A) by control circuit initializing pseudo random sequence generative circuit I, namely write an initial value, be the binary number of m position complete 1, wherein m is the parallel data width.
B) under the effect of clock, pseudorandom sequences generation I produces the output of parallel pseudo-random sequences data, simultaneously, with the pseudo random sequence of output as feed back input in pseudorandom sequences generation I.
At communication receiver:
A) by control circuit zero clearing error code counter.
B) data of transmitting on the circuit are sent into pseudorandom sequences generation II, produce a new m position pseudo random sequence by this pseudorandom sequences generation II, wherein m is the parallel data width.
C) the temporary clock cycle of sequence that by the m bit register above-mentioned pseudorandom sequences generation II is produced.
D) by comparison circuit the m position pseudo random sequence of register output and device channel input data are compared, if both are unequal, then produce a pulse signal requirement error code counter and add one.
The invention has the beneficial effects as follows:
Device for detecting code error of the present invention and method can be carried out Error detection to various network service type very flexibly and easily, are applicable to SONET, SDH, the variety of network types such as Ethernet, different speed grade.Both can carry out error code testing by local loopback, and also can send pseudo random sequence by an end, a termination is received this sequence and carried out error code testing, and is applied widely.In addition, the used pseudo random sequence of error code testing uses parallel mode to produce, and also greatly reduces circuit cost and design difficulty.
(4) description of drawings
Fig. 1 is that serial produces the pseudo-random binary sequence circuit structure diagram.
Fig. 2 is the parallel output pseudo-random binary sequence circuit structure diagram that device for detecting code error of the present invention adopts.
Fig. 3 is the structural representation of device for detecting code error of the present invention.
Fig. 4 adopts Loopback Mode to carry out the connection diagram of Error detection.
Fig. 5 adopts to be transferred to the connection diagram that the far-end mode is carried out Error detection.
(5) embodiment
The present invention is further elaborated below in conjunction with the drawings and specific embodiments.
The 10Gbps ethernet line is carried out the error rate to be detected, define equipment internal data width is 20bit, clock frequency is 156.25Mhz, must generate pseudo-random binary sequence PRBS (Pseudo Random Binary Sequence) code in order to carry out error code testing.Suppose and use prbs7, both generator polynomial was X^7+X^6+1, and using this generator polynomial can formation sequence length be 128 pseudo-random binary sequence.This generator polynomial serial circuit forms as shown in Figure 1:
If but used this serial circuit to generate the pseudo-random binary sequence of 20bit, then the circuit clock frequency would be that 156.25Mhz multiply by 20, is 3125Mhz.Under the work high frequency like this circuit design cost and difficulty are improved greatly, the present invention uses parallel mode as shown below to generate pseudo-random binary sequence, can make pseudo-random binary sequence be operated in the core frequency 156.25Mhz of equipment.Comprise the computing of following execution XOR, be respectively from high to low by parallel data bit, as shown in Figure 2:
The 6th bit and the 5th bit; The 5th bit and the 4th bit; The 4th bit and the 3rd bit; The 3rd bit and the 2nd bit; The 2nd bit and the 1st bit; The 1st bit and the 0th bit; The 0th bit, the 5th bit and the 6th bit; The 6th bit, the 5th bit and the 4th bit; The 5th bit, the 4th bit and the 3rd bit; The 4th bit, the 3rd bit and the 2nd bit; The 3rd bit, the 2nd bit and the 1st bit; The 2nd bit, the 1st bit and the 0th bit; The 1st bit, the 0th bit, the 6th bit and the 5th bit; The 4th bit, the 0th bit, the 6th bit and the 5th bit; The 3rd bit, the 4th bit, the 6th bit and the 5th bit; The 3rd bit, the 4th bit, the 2nd bit and the 5th bit; The 3rd bit, the 4th bit, the 2nd bit and the 1st bit; The 3rd bit, the 2nd bit, the 1st bit and the 0th bit; The 2nd bit, the 1st bit, the 0th bit, the 6th bit and the 5th bit; The 4th bit, the 1st bit, the 0th bit, the 6th bit and the 5th bit.
With as above pseudorandom sequences generation I and the pseudorandom sequences generation II of the electric circuit constitute high-speed digital communication line error code detection device.This pseudorandom sequences generation I and pseudorandom sequences generation II and other parts of high-speed digital communication line error code detection device: register, control circuit, comparison circuit and error code counter are as shown in Figure 3.
Then as follows connecting test equipment and circuit:
Embodiment 1:
Be looped back to input channel by external circuit after the pseudo random sequence output, whether device for detecting code error meets the judgement of pseudo random sequence code again to the input data of loopback, carry out Error detection.As shown in Figure 4.
Embodiment 2:
Pseudo random sequence outputs to remote receiver, more whether the input data is met the judgement of pseudo random sequence code by the device for detecting code error of remote equipment, carries out Error detection.As shown in Figure 5.
Then operate with following steps:
A) by control circuit initializing pseudo random sequence generative circuit I, namely writing an initial value, is 20 complete 1 binary number.
B) under the effect of clock, pseudorandom sequences generation I produces the output of parallel pseudo-random sequences data.Simultaneously, with output pseudo random sequence as feed back input in pseudorandom sequences generation I.
At communication receiver:
A) by control circuit zero clearing error code counter.
B) data of transmitting on the circuit are sent into pseudorandom sequences generation II, produce 20 new pseudo random sequences by this circuit.
C) the temporary clock cycle of sequence that by 20 bit registers above-mentioned pseudorandom sequences generation II is produced.
D) by comparison circuit 20 pseudo random sequences of register output and device channel input data are compared, if both are unequal, then produce a pulse signal requirement error code counter and add one.
In the above-described embodiments, device for detecting code error of the present invention and method both can be carried out error code testing by local loopback, also can send pseudo random sequence by an end, and a termination is received this sequence and carried out error code testing, and is applied widely.The used pseudo random sequence of error code testing uses parallel mode to produce, and also greatly reduces circuit cost and design difficulty.
Above-described embodiment is more preferably embodiment of the present invention, and common variation and replacement that those skilled in the art carries out in the technical solution of the present invention scope all should be included in protection scope of the present invention.
Claims (3)
1. a high-speed digital communication line error code detection device comprises error code counter, pseudorandom sequences generation I, pseudorandom sequences generation II, register, control circuit, comparison circuit;
Described error code counter, in order to calculate the error code number of times, its structure is:
When a) receiving the reset signal of control circuit generation, this counter O reset,
When b) receiving the pulse signal of comparison circuit generation, this counter adds one;
Described pseudorandom sequences generation I, in order to produce a pseudo random sequence data pattern in an integrated circuit, high-speed digital communication line error code detection device will send this pseudo random sequence, in order to the detection line error rate, described pseudorandom sequences generation I, its structure is:
A) this pseudorandom sequences generation I does not comprise n level linear feedback shift register, but is the m group XOR composition of m position with input and output, and wherein m is the parallel data width,
B) initial value of this pseudorandom sequences generation I is the binary number of full m position complete 1,
C) this pseudorandom sequences generation I inputs the result of calculation of oneself as value of feedback, and do not use initial value this moment when this pseudorandom sequences generation I calculates, but produces the output valve of the pseudo random sequence of next clock cycle with value of feedback;
Described pseudorandom sequences generation II, in order in an integrated circuit, to produce a pseudo random sequence data pattern, high-speed digital communication line error code detection device will arrive pseudorandom sequences generation II to the sequence that receives as feed back input, produce new pseudo random sequence, described pseudorandom sequences generation II, its structure is:
A) pseudorandom sequences generation II does not comprise n level linear feedback shift register, but is the m group XOR composition of m position with input and output, and wherein m is the parallel data width, and described pseudorandom sequences generation I is identical for this group logical AND,
The initial value of this pseudorandom sequences generation II is the binary number of full m position complete 1,
This pseudorandom sequences generation II does not input the result of calculation of oneself as value of feedback, but, as value of feedback, generate the feed back input that calculates with the input value of current channel in order to pseudo random sequence;
Described register is in order to pseudo random sequence clock cycle of storage that pseudorandom sequences generation II is generated;
Described control circuit in order to control pseudorandom sequences generation I, pseudorandom sequences generation II and error code counter, comprises that pseudorandom sequences generation resets, the error code counter Protection Counter Functions, and its structure is:
A) reset signal of generation pseudorandom sequences generation I, this signal makes pseudorandom sequences generation I get back to initial condition,
B) reset signal of generation pseudorandom sequences generation II, this signal makes pseudorandom sequences generation II get back to initial condition,
C) reset signal of generation error code counter, this signal make the zero clearing of error code counting;
Described comparison circuit, be the m bit comparator of a standard, wherein m is the parallel data width, in order to compare the sequence that produces among parallel pseudo-random sequences input and the pseudorandom sequences generation II, if both are unequal, then produce a pulse signal requirement error code counter and add one.
2. the detection method of a high-speed digital communication line error code detection device as claimed in claim 1 is characterized in that said method comprising the steps of:
A) by control circuit initializing pseudo random sequence generative circuit I, namely write an initial value, be the binary number of m position complete 1, wherein m is the parallel data width,
B) under the effect of clock, pseudorandom sequences generation I produces the output of parallel pseudo-random sequences data, simultaneously, with the pseudo random sequence of output as feed back input in pseudorandom sequences generation I;
At communication receiver:
A) by control circuit zero clearing error code counter,
B) data of transmitting on the circuit are sent into pseudorandom sequences generation II, produce a new m position pseudo random sequence by this pseudorandom sequences generation II, wherein m is the parallel data width,
C) the temporary clock cycle of sequence that by the m bit register above-mentioned pseudorandom sequences generation II is produced,
D) by comparison circuit the m position pseudo random sequence of register output and parallel pseudo-random sequences input are compared, if both are unequal, then produce a pulse signal requirement error code counter and add one.
3. the purposes of a high-speed digital communication line error code detection device as claimed in claim 1 is characterized in that comprising following two kinds of application modes:
A) be looped back to input channel by external circuit after the pseudo random sequence output, whether device for detecting code error meets the judgement of pseudo random sequence code again to the input data of loopback, carry out Error detection, or:
B) pseudo random sequence outputs to remote receiver, more whether the input data is met the judgement of pseudo random sequence code by the device for detecting code error of remote receiver, carries out Error detection.
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| CN102970077A (en) * | 2012-12-13 | 2013-03-13 | 上海市共进通信技术有限公司 | Error rate testing device and method for circuit board integrated optical component system |
| CN105183428A (en) * | 2015-08-12 | 2015-12-23 | 中国电子科技集团公司第四十一研究所 | Pseudo-random signal generation method |
| CN105634644B (en) * | 2015-12-25 | 2017-12-29 | 潘岭 | A kind of detection method and system of SDH transmission |
| CN107135033B (en) * | 2017-05-27 | 2019-04-16 | 烽火通信科技股份有限公司 | A kind of optical link fault diagnosis system and method based on PRBS |
| US10372535B2 (en) * | 2017-08-29 | 2019-08-06 | Winbond Electronics Corp. | Encoding method and a memory storage apparatus using the same |
| CN109787723B (en) * | 2019-01-04 | 2021-08-24 | 武汉邮电科学研究院有限公司 | Detection method and detection system for bit error rate and high-order modulation communication system |
| CN111654358B (en) * | 2020-05-26 | 2023-03-24 | 中国人民解放军国防科技大学 | Physical layer transmission real error code acquisition device and equipment |
| CN113030709B (en) * | 2021-04-06 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | Superconducting high-frequency test system and method |
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| CN1505326A (en) * | 2002-12-02 | 2004-06-16 | 深圳市中兴通讯股份有限公司 | Error code detection apparatus and method for digital exchange system |
| CN1728626A (en) * | 2004-07-27 | 2006-02-01 | 中兴通讯股份有限公司 | Method and device for detecting error code in wireless digital communication system |
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| DE19838782C2 (en) * | 1998-08-26 | 2002-12-19 | Ericsson Telefon Ab L M | Transmitter, receiver and method in a telecommunication system for generating PN sequences for a variety of user channels |
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| CN1505326A (en) * | 2002-12-02 | 2004-06-16 | 深圳市中兴通讯股份有限公司 | Error code detection apparatus and method for digital exchange system |
| CN1728626A (en) * | 2004-07-27 | 2006-02-01 | 中兴通讯股份有限公司 | Method and device for detecting error code in wireless digital communication system |
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