CN110457008B

CN110457008B - m sequence generation method, device and storage medium

Info

Publication number: CN110457008B
Application number: CN201810434254.2A
Authority: CN
Inventors: 程觉
Original assignee: Beijing Xiaomi Pinecone Electronic Co Ltd
Current assignee: Beijing Xiaomi Pinecone Electronic Co Ltd
Priority date: 2018-05-08
Filing date: 2018-05-08
Publication date: 2021-08-03
Anticipated expiration: 2038-05-08
Also published as: CN110457008A

Abstract

The disclosure relates to a method and a device for generating an m sequence, which can improve the efficiency of generating the m sequence. The method comprises the following steps: determining the positions of N nonzero feedback coefficients included in the feedback coefficients of the multistage shift register; respectively shifting the state variable of the register for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient; carrying out XOR operation on the N variable values subjected to the N times of shifting; generating an m-sequence according to the result of the XOR operation; and updating the state variable of the register according to the generated m sequence.

Description

m sequence generation method, device and storage medium

Technical Field

The present disclosure relates to the field of computer and communication technologies, and in particular, to a method and an apparatus for generating an m-sequence, and a storage medium.

Background

The sequence includes a plurality of kinds, and the sequence which can be predetermined and can be repeatedly realized is called a determined sequence; sequences that can neither be predetermined nor repeatedly implemented are called random sequences; sequences that cannot be predetermined but can be repeatedly generated are called pseudo-random sequences. The m sequence is a short for the longest linear shift register sequence, and is a Pseudo random sequence, Pseudo Noise code (PN) or Pseudo random code. The m sequence is a pseudo random sequence which is widely applied at present, and has wide application in the communication field, such as spread spectrum communication, code division multiple access of satellite communication, encryption, scrambling, synchronization, error rate measurement and the like in digital data.

At present, there are many methods for generating m-sequences, for example, the m-sequence is generated by using the following formula:

n is 0,1,2,3, … …, r is the register series, x (i) is the m sequence with the binary number 0 or 1, c_iIs a feedback coefficient.

The m sequence of only one bit can be generated by one operation through the formula, the efficiency is low, and the method is not suitable for the scalar processor which is widely used at present to operate.

Or for example, a matrix method may be used to generate m-sequences, however, each time n bits are generated, n times of state transition matrix multiplication are required, especially when the shift register is long, the operation amount is large, and at the same time, the state transition matrix also needs to be stored, and each time the transition matrix is called, the memory needs to be read, which increases the processing time.

Disclosure of Invention

The purpose of the present disclosure is to provide an m-sequence generation method, apparatus, and storage medium, which can improve the efficiency of generating an m-sequence.

According to a first aspect of the embodiments of the present disclosure, there is provided an m-sequence generation method, including:

determining the positions of N nonzero feedback coefficients included in the feedback coefficients of the multistage shift register;

respectively shifting the state variable of the register for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient;

carrying out XOR operation on the N variable values subjected to the N times of shifting;

generating an m-sequence according to the result of the XOR operation;

and updating the state variable of the register according to the generated m sequence.

Optionally, let the number of stages of the multi-stage shift register be r, and the corresponding values of the positions of the N non-zero feedback coefficients from low to high are a0, a1, … …, am, where m<R, a0 is 0, and N variable values obtained by shifting the register state variables N times are R_a0，R_a1，……，R_am；

Generating an m-sequence based on the result of the exclusive-or operation, comprising:

value of order variable R_y＝R_a0^R_a1^…^R_amWherein ^ is an exclusive or operation;

value of variable R_yAnd taking the value of r-am bit from low to high as the value of the generated m sequence.

Optionally, the making the register state variable be a variable R, and updating the register state variable according to the generated m sequence includes:

determining the number r-am as the bit number of the m sequence which can be output at one time;

right-shifting the variable R by R-am bits;

supplementing the generated R-am bit to the high order of the variable R to update the register state variable;

after updating the state variable of the register, executing the steps of shifting the state variable of the register for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient, carrying out XOR operation on the N variable values after the N times of shifting, and generating an m sequence according to the result of the XOR operation.

Optionally, performing an exclusive or operation on the N variable values subjected to the N times of shifting includes:

aiming at the numerical value corresponding to the position of each non-zero feedback coefficient, after the state variable of the register is moved to the right by the digit corresponding to the numerical value, the moved high order is supplemented into the numerical value 0 of the corresponding digit;

and carrying out XOR operation on the N variable values after the high-order is supplemented with the value 0.

performing an exclusive-OR operation on the N variable values by a scalar processor of a computer.

According to a second aspect of the embodiments of the present disclosure, there is provided an m-sequence generating apparatus including:

the determining module is used for determining the positions of N nonzero feedback coefficients included in the feedback coefficients of the multistage shift register;

the shift module is used for shifting the state variable of the register for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient;

the exclusive-OR operation module is used for carrying out exclusive-OR operation on the N variable values subjected to the N times of shifting;

the m sequence generating module is used for generating an m sequence according to the result of the exclusive or operation;

and the register variable updating module is used for updating the register state variable according to the generated m sequence.

the m-sequence generation module is configured to:

Optionally, the register state variable is made to be a variable R, and the register variable updating module is configured to:

right-shifting the variable R by R-am bits;

after the register state variable is updated, the shifting module executes the step of shifting the register state variable for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient, the exclusive-or operation module executes the step of performing exclusive-or operation on the N shifted variable values for N times, and the m sequence generation module executes the step of generating an m sequence according to the result of the exclusive-or operation.

Optionally, the xor operation module is configured to:

According to a third aspect of embodiments of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method of any one of the first aspects.

Through the technical scheme, the positions of N nonzero feedback coefficients included in the feedback coefficients of the multistage shift register can be determined firstly, then the state variable of the register is shifted for N times according to the numerical value corresponding to the position of each nonzero feedback coefficient, and then the N variable values subjected to N times of shifting are subjected to XOR operation, so that an m sequence can be generated according to the result of the XOR operation. According to the technical scheme, on one hand, the m sequence can be generated without storing a state transition matrix, so that the memory is saved, the processing time for reading data from the memory is also saved, on the other hand, a shift exclusive-OR method is adopted to replace multiplication among calculation matrixes, so that a large number of operations are reduced, on the other hand, for a scalar processor, the m sequence can be generated by directly carrying out exclusive-OR operation, and compared with a mode that a scalar processor singly takes out specific bits and then carries out operation to generate the m sequence, the method is simpler and quicker.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

FIG. 1 is a schematic diagram of a shift register shown in accordance with an exemplary embodiment;

FIG. 2 is a flow diagram illustrating a method of m-sequence generation in accordance with an exemplary embodiment;

FIG. 3 is a schematic diagram of a shift register shown in accordance with an exemplary embodiment;

fig. 4 is a block diagram illustrating an m-sequence generating apparatus according to an example embodiment.

Detailed Description

The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.

First, referring to fig. 1, an m-sequence generation manner in the prior art is illustrated, where m-sequence generation is composed of two parts, namely, a register state and a feedback coefficient, where x (n) to x (n + r-1) are shift register states, and c0 to c (r-1) are feedback coefficients. The feedback coefficients are not changed when set initially during the whole sequence generation process, the register state is circularly shifted to the right by x (n) and x (n +1), x (n +1) and x (n +2), … …, x (n + r-1) is filled according to the feedback result of each coefficient,

n is 0,1,2,3, … …, r is the number of register stages, where x (i) is the generated m-sequence, 0<＝i<＝2^r-1. If the register length is r, the m-sequence period length is 2^r-1。

For example, the register stage number r is 8, the initial state x (0) is 0, x (1) is 1, x (2) is 1, x (3) is 0, x (4) is 1, x (5) is 1, x (6) is 0, x (7) is 1, the feedback coefficient c0 is 1, c1 is 0, c2 is 1, c3 is 0, c4 is 1, c5 is 0, c6 is 0, c7 is 0, and x (8) can be obtained as follows.

When n is 0, substituting the formula to obtain: (hereinafter, the addition is modulo two addition)

x(8)＝x(0)*c0+x(1)*c1+x(2)*c2+....+x(7)*c7

＝x(0)*c0+x(2)*c2+x(4)*c4

＝0*1+1*1+1*1

＝0+1+1

＝0；

And by analogy, when n takes 1,2 and 3 …, the formula is substituted to calculate x (9) and x (10) … ….

It can be seen that, by the above manner, an m-sequence capable of generating one bit is calculated at a time, the calculation amount is large, and the efficiency is low, and the manner of reducing the calculation amount and improving the m-sequence generation efficiency proposed by the present disclosure will be described below.

Fig. 2 is a flowchart illustrating an m-sequence generation method according to an exemplary embodiment, which may be applied to an electronic device (including but not limited to a computer, a mobile phone, a tablet computer, etc.) as shown in fig. 2, and includes the following steps.

Step S11: the positions of N non-zero feedback coefficients included in the feedback coefficients of the multi-stage shift register are determined.

Step S12: and respectively shifting the state variable of the register for N times according to the numerical value corresponding to the position of each non-zero feedback coefficient.

Step S13: and carrying out XOR operation on the N variable values subjected to the N times of shifting.

Step S14: based on the result of the exclusive-or operation, an m-sequence is generated.

Step S15: and updating the state variable of the register according to the generated m sequence.

Also taking the multi-stage register shown in fig. 1 as an example, let the stage R of the linear feedback shift register store its state in a variable R (i.e., register state variable), and let the lowest bit of the variable be x (n) in fig. 1, and sequentially left be x (n +1), … …, x (n + R-1).

In step S11, the positions of the non-zero feedback coefficients in the feedback coefficients c corresponding to the registers of each stage are a0, a1, … …, am from right to left (for example, if there are N non-zero feedback coefficients, N is m +1), where m < r, and a0 is 0. For example, if the number r of register stages is 4, c0, c2, c1, c3 and 0, there are 2 non-zero feedback coefficients, c0 and c2, respectively, and their positions are 0 and 2 from right to left, so a0 is 0, a1 is 2, and m is 1.

In step S12, i.e., shifting R to the right by a0, a1, … …, am, respectively, the results after shifting are shown in table 1 below:

TABLE 1 variable R Shift results

bit(r-1)

…

bit4

bit3

bit2

bit1

bit0

x(n+r-1)

…

x(n+4)

x(n+3)

x(n+2)

x(n+1)

x(n)

x(n+a1+r-1)

…

x(n+a1+4)

x(n+a1+3)

x(n+a1+2)

x(n+a1+1)

x(n+a1)

x(n+a2+r-1)

…

x(n+a2+4)

x(n+a2+3)

x(n+a2+2)

x(n+a2+1)

x(n+a2)

…

x(n+am+r-1)

…

x(n+am+4)

x(n+am+3)

x(n+am+2)

x(n+am+1)

x(n+am)

The values after the shift of the register are respectively recorded as:

R_a0＝R>>a0；(“>>"means right shift, here means right shift a0 bit)

R_a1＝R>>a1；

R_a2＝R>>a2；

……

R_am＝R>>am；

Then R is_a0Is shown in the first row of Table 1, where the lowest bits are x (n), R_a1Is shown in the second row of table 1, where the lowest bit is x (n + a1), the remaining shifted variable values and so on.

In step S13, the N variable values R obtained by shifting are used_a0，R_a1，……，R_amPerforming XOR operation, then, let R_y＝R_a0^R_a1^…^R_amWherein ^ is an exclusive OR operation.

Optionally, for the value corresponding to the position of each non-zero feedback coefficient, after the register state variable is shifted to the right by the number of bits corresponding to the value, the shifted high order is complemented with the value 0 of the corresponding number of bits, and then the xor operation is performed on the N variable values after the high order is complemented with the value 0. That is, R_a0，R_a1，……，R_amAfter shifting to the right, the xor operation may be performed directly, or the upper bits may be complemented with 0, and the xor operation may be performed with the variable value after being complemented with 0.

Optionally, in step S14, an m-sequence is generated according to the result of the xor operation, which may be to change the value R_yAnd taking the value of r-am bit from low to high as the value of the generated m sequence.

Let offset be R-am-1, R_yMay be represented as shown in table 2.

TABLE 2 XOR result of values of variables after shifting

bit(r-1)

…

bit(offset+1)

bit(offset)

…

bit1

bit0

y(n+r-1)

…

y(n+offset+1)

y(n+offset)

…

y(n+1)

y(n)

With the method of the present disclosure, it is possible to output offset +1 (i.e., r-am) bits at a time, and the outputs are x (n + r) ═ y (n), (n + r +1) ═ y (n +1), … …, and x (n + r + offset) ═ y (n + offset), respectively. It can be seen that the length of the sequence that can be generated at a time by the present disclosure depends on the offset, i.e., the number of stages r of the linear feedback register and the maximum non-zero feedback coefficient am, and as am is smaller, offset is larger, the efficiency of the sequence generation is higher.

Optionally, in step S15, the register state variable may be updated by first determining the value R-am as the number of bits of the m-sequence that can be output at one time, then shifting the variable R to the right by R-am bits, and then supplementing the generated R-am bits to the high bits of the variable R. After updating the state variable of the register, the steps of shifting the state variable of the register N times according to the value corresponding to the position of each non-zero feedback coefficient, performing xor operation on the N shifted variable values, and generating an m-sequence according to the result of the xor operation are performed again.

That is, after the sequence is output, the register state is updated, and the updated register state is shown in table 3.

TABLE 3 register State after bit output

bit(r-1)	…	bit(r-offset-1)	…	bit1	bit0
						y(n+offset)	…	y(n)	…	X(n+offset+2)	X(n+offset+1)

The updated register state is actually the register state R before output is shifted to the right by offset +1, i.e. R-am bits, and then the R-am bits of y (n), y (n +1), … …, y (n + offset) output this time are supplemented to the tail of the register state.

Then, step S12-step S14 are performed again to generate the remaining bits, and the maximum non-periodic m-sequence length that can be generated is 2^r-1。

Optionally, the xor operation may be performed on the N variable values after the N times of shifting, or may be performed on the N variable values by a scalar processor of the computer.

That is, for a scalar processor, it is not convenient to operate on each bit, but an exclusive or operation may be performed on a variable, so the technical solution of the present disclosure may be applied to any scalar processor.

Of course, in practical applications, the selected m sequence is not taken from x (0) directly, but has an offset, which is D, that is, the m sequence is taken from x (D), and a certain sequence length is selected from the beginning, for example, D value is 1600, if according to the disclosed scheme, 1600 bits need to be generated first, and then 1601 bits are used to start with the actually required target bit. For this case, a matrix method may be used in combination with the technical solution of the present disclosure.

For example, when D is 1600 and the number of register stages is r, a matrix method, X, may be used first₁₆₀₀＝X₀×A¹⁶⁰⁰(X₀Is the initial register state vector, a is the state transition matrix, is known), so a can be first calculated using tools such as matlab, etc¹⁶⁰⁰Calculated X₁₆₀₀I.e., register state R when D1600, and X₁₆₀₀The values of (a) are x (1600), x (1601), … …, and x (1600+ r-1) in sequence from low to high, and then the remaining m-sequence can be calculated by using the technical scheme of the present disclosure.

In order to better illustrate the technical solutions of the present disclosure, the following detailed description will be given through the full examples.

The first embodiment is as follows:

assuming that the register stage number r is 8, the initial state x (0) is 0, x (1) is 1, x (2) is 1, x (3) is 0, x (4) is 1, x (5) is 1, x (6) is 0, x (7) is 1, the feedback coefficient c0 is 1, c1 is 0, c2 is 1, c3 is 0, c4 is 1, c5 is 0, c6 is 0, and c7 is 0.

The initial variable value R of the register is 0xb6 ('0 xb 6' is 16-ary representation, for a total of 8 bits, corresponding to 10110110), if R is shifted one bit to the right, it becomes 01011011, the bit shifted up is replaced by 0, corresponding to 0x5b and so on, and R is shifted two bits to the right, it becomes 00101101, the bit shifted up is further shifted in by one 0, corresponding to 0x2d and so on.

As can be seen from the feedback coefficients, the non-zero coefficients are c0, c2 and c4, respectively, so that a0 equals 0, a1 equals 2, and a2 equals 4, then:

R_a0＝R>>a0＝R＝0xb6；

R_a1＝R>>a1＝R>>2＝0x2d；

R_a2＝R>>a2＝R>>4＝0x0b；

in scalar processors, variables can be xored, for example:

to R_a0^R_a1XOR' ing bit bits corresponding to modulo twoThe result of addition and exclusive or is 10011011. Then: r_a0^R_a1＝0x9b；R_y＝R_a0^R_a1^R_a2＝0x9b^0x0b＝0x90；

offset＝r-am-1＝8-a2-1＝8-4-1＝3；

Then offset +1 can be calculated at one time as 4 bits x (8), x (9), x (10) and x (11), corresponding to R_yThe lower 4 bits of (a):

x(8)＝0，x(9)＝0，x(10)＝0，x(11)＝0。

example two:

as shown in fig. 3, it is assumed that the register stage number R is 4, the register initial state R is 3 (binary 0011, i.e. when n is 0, x (0) is 1, x (1) is 1, x (2) is 0, and x (3) is 0), the feedback coefficient c0 is 1, c1 is 1, c2 is 0, c3 is 0, a0 is 0, a1 is 1, m is 1, and offset R-am-1 is 4-1-2, so that offset +1 can be generated at a time by the method of the present disclosure, which is 3 bits.

Shifting R to obtain R_a0And R_a1：R_a0＝R>>a0＝R＝3；R_a1＝R>>a1＝R>>1＝1。

To R_a0And R_a1Performing exclusive-or operation: r_y＝R_a0^R _a13^1 ^2, 2 is represented by binary 0010, and the lower 3 bits are the generated m-sequence, so x (4) ═ 0, x (5) ═ 1, and x (6) ═ 0.

And forming a new register state, wherein x (6) is 0, x (5) is 1, x (4) is 0, and x (3) is 0 in sequence from high to low. That is, the update register state R is 4 (0100 in binary);

based on the updated register state, the shift and XOR operations are performed again to produce new data outputs x (6), x (7), and x (8):

R_y＝R_a0^R_a14^2 ^ 6 (binary 0110), x (7) is 0, x (8) is 1, and x (9) is 1. The following x (n), n>9, the method can be analogized, 4 stages of registers can generate m sequences with the period of 2⁴-1＝15。

Referring to fig. 4, based on the same inventive concept, an embodiment of the present disclosure provides an m-sequence generating apparatus 400, where the apparatus 400 may include:

a determining module 401, configured to determine positions of N nonzero feedback coefficients included in feedback coefficients of a multi-stage shift register;

a shift module 402, configured to shift the state variable of the register N times according to a value corresponding to a position of each non-zero feedback coefficient;

an exclusive-or operation module 403, configured to perform exclusive-or operation on the N variable values subjected to the N times of shifting;

an m-sequence generating module 404, configured to generate an m-sequence according to the result of the xor operation;

and a register variable update module 405, configured to update the register state variable according to the generated m-sequence.

the m-sequence generation module 404 is configured to:

Optionally, the register state variable is made to be a variable R, and the register variable updating module 405 is configured to:

right-shifting the variable R by R-am bits;

after the register state variables are updated, the shift module 402 again executes the step of shifting the register state variables N times according to the values corresponding to the positions of the respective non-zero feedback coefficients, the exclusive-or operation module 403 again executes the step of exclusive-oring the N shifted variable values N times, and the m-sequence generation module 404 again executes the step of generating the m-sequence according to the result of the exclusive-or operation.

Optionally, the exclusive or operation module 403 is configured to:

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed.

The functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a non-transitory computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a ROM (Read-Only Memory), a RAM (Random access Memory), a magnetic disk, or an optical disk.

The above embodiments are only used to describe the technical solutions of the present disclosure in detail, but the above embodiments are only used to help understanding the method and the core idea of the present disclosure, and should not be construed as limiting the present disclosure. Those skilled in the art should also appreciate that various modifications and substitutions can be made without departing from the scope of the present disclosure.

Claims

1. An m-sequence generation method, comprising:

let the number of stages of the multi-stage shift register be r, and the corresponding numerical values of the positions of the N non-zero feedback coefficients from low to high are a0, a1, … … and am, wherein m<R, a0 is 0, and N variable values obtained by shifting the register state variables N times are R_a0，R_a1，……，R_amValue of order variable R_y＝R_a0^R_a1^…^R_amWherein ^ is exclusive-OR operation, and the value R is changed_yTaking the value of r-am bit from low to high as the value of the generated m sequence;

2. The method according to claim 1, wherein the updating the register state variable according to the generated m-sequence by making the register state variable a variable R comprises:

right-shifting the variable R by R-am bits;

after updating the state variable of the register, executing the steps of shifting the state variable of the register for N times according to the numerical value corresponding to the position of each nonzero feedback coefficient, carrying out XOR operation on the N variable values subjected to the N times of shifting, and generating an m sequence according to the result of the XOR operation.

3. The method of any of claims 1-2, wherein xoring the N shifted N variable values, comprising:

4. The method of any of claims 1-2, wherein xoring the N shifted N variable values, comprising:

5. An m-sequence generating apparatus, comprising:

an m-sequence generation module, configured to make the number of stages of the multi-stage shift register r, where the positions of the N non-zero feedback coefficients from low to high correspond to values a0, a1, … …, am, where m is<R, a0 is 0, and N variable values obtained by shifting the register state variables N times are R_a0，R_a1，……，R_amValue of order variable R_y＝R_a0^R_a1^…^R_amWherein ^ is exclusive-OR operation, and the value R is changed_yTaking the value of r-am bit from low to high as the value of the generated m sequence;

6. The apparatus of claim 5, wherein the register state variable is made to be a variable R, and wherein the register variable update module is configured to:

right-shifting the variable R by R-am bits;

7. The apparatus of any one of claims 5-6, wherein the XOR operation module is configured to:

8. The apparatus of any one of claims 5-6, wherein the XOR operation module is configured to:

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.