CN1728350A - Method for preparing NMOS device withou source and drain poles being heavily doped - Google Patents
Method for preparing NMOS device withou source and drain poles being heavily doped Download PDFInfo
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- CN1728350A CN1728350A CN 200410053297 CN200410053297A CN1728350A CN 1728350 A CN1728350 A CN 1728350A CN 200410053297 CN200410053297 CN 200410053297 CN 200410053297 A CN200410053297 A CN 200410053297A CN 1728350 A CN1728350 A CN 1728350A
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Abstract
After deposition of polysilicon gate through conventional technique, the disclosed method carries out following steps: first; carrying out selective ion implantation for NMOS gate, next, carrying out procedure for etching gate; then carrying out ion implantation of slow changed junction; finally, fabricating self-aligned silicide. The invention carries out NMOS ion implantation selectively in order to reduce polysilicon exhaustion of transistor, and to adjust resistivity of polysilicon. High-energy ion implantation in low dose is adopted in the invention instead of source-drain implantation in high dose. Thus, the invention reduces hot carrier's effect effectively, and raises rate of finished products.
Description
Technical field
The preparation method of the relevant a kind of nmos device of the present invention, especially a kind of preparation method of without source-drain heavy doping nmos device.
Background technology
In the conventional device technology, all have heavily doped source to leak ion and inject, concrete function is as follows:
1. satisfy the drive current of device;
2. satisfy the face resistance of no silicide polysilicon;
3. obtain enough little source-and-drain junction electric capacity;
4. the realization source ohmic contact of leaking;
5. reduce the series resistance of source-drain area.
In modern semiconductors technology, silicide is used for replacing conventional gold-half ohmic contact, and silicide makes that the series resistance of source-drain area is enough little, and the drive current of device is many is determined by low doping source drain region (LDD).But consider other function that the leakage of high dose source is injected, people still are accustomed to using it.
But the source of high dose is leaked to inject and has been brought some drawbacks, mainly be because injection is leaked in the source of high dose, impurity can diffuse laterally into low doping source drain region (LDD) by source-drain area (SD), cause high channel laterally electric field, more ionization by collision takes place, cause hot carrier's effect (HCI) problem, cause the reliability decrease of device.
Summary of the invention
For a change the defective in the prior art the objective of the invention is to reduce hot carrier's effect by changing the injection mode of leaking in the nmos device source, and then improves the reliability of device.
In order to realize goal of the invention of the present invention, the preparation method of the heavily doped nmos device of a kind of without source-drain of the present invention, it is characterized in that: after polysilicon gate is long-pending, the NMOS grid are carried out the selectivity ion to be injected, make the etching technics of grid then, then carry out the progressive junction ion and inject, make self-aligned silicide at last.
Owing to adopt technique scheme, the present invention optionally carries out ion to NMOS and injects, and reduces transistorized depletion of polysilicon on the one hand, is used for regulating the polysilicon resistance rate on the other hand.The source of cancellation high dose is leaked and is injected, and adopts the low dosage high energy ion to inject and replaces, and reduces hot carrier's effect effectively, improves the rate of finished products of device.
The accompanying drawing simple declaration
Fig. 1 is the flow chart of one embodiment of the present of invention.
Fig. 2 is an implementation process schematic diagram of the present invention.
Fig. 3 is the distribution map of nmos device schematic diagram and channel surface phosphorus in one embodiment of the present of invention and the traditional handicraft.
Fig. 4 is nmos device schematic diagram in one embodiment of the present of invention and the traditional handicraft and the transverse electric field distribution figure that leaks the lateral sulcus road.
Fig. 5 is the substrate current of one embodiment of the present of invention and the graph of a relation of gate voltage.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
Consult shown in Figure 1ly, it is the flow chart of one embodiment of the present of invention.As shown in the figure, a kind of preparation method of without source-drain heavy doping nmos device, its principal character is after the polysilicon gate of common process is long-pending, at first the NMOS grid being carried out the selectivity phosphonium ion injects, carry out the etching technics of grid then, the progressive junction ion that then carries out low dosage injects, and makes self-aligned silicide at last.See also shown in Figure 2ly, it is an implementation process schematic diagram of the present invention.In common process, the deposit polysilicon gate does not need to inject doping later on usually, directly carry out the etching of grid, the doping of NMOS polysilicon gate relies on the source of back to leak to inject and finishes, so after the etching of finishing device grid side wall, device is carried out heavy dose of source leakage current amount, and carry out the progressive junction ion injection of low dosage, higher-energy.But in the present invention, after the polysilicon gate deposit, the NMOS grid are carried out selectivity phosphorus inject, just make the etching of grid then.Leak movable heavy dose of injection the in the formation in the source, only need keep secondary progressive junction ion and inject, make self-aligned silicide subsequently.
See also shown in Figure 3ly, it is the distribution map of the phosphorus of nmos device schematic diagram and channel surface in the tradition of using the simulation of TCAD method and the technology of the present invention.Adopt the Impurity Distribution after high dose phosphorus is injected in the curve representation traditional handicraft in the part of the rightmost side of this figure above, and be to adopt the low dosage source to leak the distribution of the phosphorus that injects among the present invention than the curve representation of below.By this figure as can be seen, the concentration of the channel surface phosphorus of a side of device will mean the remarkable improvement of HCI (short-channel effect) far below traditional handicraft in new technology.
See also shown in Figure 4ly, it is the traditional handicraft of using the simulation of the TCAD method transverse electric field distribution figure with NMOS schematic diagram in the technology of the present invention and leakage lateral sulcus road.The conventional device channel laterally Electric Field Distribution of the curve representation TCAD simulation in the part of the rightmost side of this figure above, and be the device channel transverse electric field distribution of the present invention of TCAD simulation than the curve representation of below.By this figure as can be seen, adopt the device of technology of the present invention that lower transverse electric field is arranged, confirmed the improvement of HCI.
See also shown in Figure 5ly, it is for using traditional handicraft and the substrate current of the nmos device in the technology of the present invention and graph of a relation of gate voltage of the simulation of TCAD method.The substrate current of the curve representation conventional device in the part of the rightmost side of this figure above, and be the substrate current of device of the present invention than the curve representation of below.By this figure as can be seen, adopt the new technology of technology of the present invention, the NMOS substrate current further confirms the improvement of hot carrier's effect far below traditional handicraft.
In sum, the goal of the invention that can finish the inventor of the present invention is optionally carried out ion to NMOS and is injected, and reduces transistorized depletion of polysilicon on the one hand, is used for regulating the polysilicon resistance rate on the other hand.The source of cancellation high dose is leaked and is injected, and adopts the low dosage high energy ion to inject and replaces, and reduces hot carrier's effect effectively, improves the rate of finished products of device.
Claims (3)
1, a kind of preparation method of without source-drain heavy doping nmos device is characterized in that: after polysilicon gate is long-pending, the NMOS grid is carried out the selectivity ion inject, make the etching technics of grid then, then carry out the progressive junction ion and inject, make self-aligned silicide at last.
2, the preparation method of without source-drain heavy doping nmos device as claimed in claim 1 is characterized in that: described what carry out adopting when the progressive junction ion injects is that the progressive junction ion of low dosage injects.
3, the preparation method of without source-drain heavy doping nmos device as claimed in claim 1 is characterized in that: described what carry out adopting when ion optionally injects at the NMOS grid is that optionally phosphorus injects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410053297 CN1728350A (en) | 2004-07-29 | 2004-07-29 | Method for preparing NMOS device withou source and drain poles being heavily doped |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410053297 CN1728350A (en) | 2004-07-29 | 2004-07-29 | Method for preparing NMOS device withou source and drain poles being heavily doped |
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| Publication Number | Publication Date |
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| CN1728350A true CN1728350A (en) | 2006-02-01 |
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| CN 200410053297 Pending CN1728350A (en) | 2004-07-29 | 2004-07-29 | Method for preparing NMOS device withou source and drain poles being heavily doped |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923296B (en) * | 2009-06-17 | 2011-12-14 | 上海华虹Nec电子有限公司 | Making method of photoetching fiducial mark in process of making NVM (Non-Volatile Memory) device |
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2004
- 2004-07-29 CN CN 200410053297 patent/CN1728350A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923296B (en) * | 2009-06-17 | 2011-12-14 | 上海华虹Nec电子有限公司 | Making method of photoetching fiducial mark in process of making NVM (Non-Volatile Memory) device |
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