CN1725454A - Manufacturing method of semiconductor transistor element with supershallow connection surface drain/source expansion - Google Patents
Manufacturing method of semiconductor transistor element with supershallow connection surface drain/source expansion Download PDFInfo
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- CN1725454A CN1725454A CN 200410070964 CN200410070964A CN1725454A CN 1725454 A CN1725454 A CN 1725454A CN 200410070964 CN200410070964 CN 200410070964 CN 200410070964 A CN200410070964 A CN 200410070964A CN 1725454 A CN1725454 A CN 1725454A
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- semiconductor transistor
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- transistor component
- sidewall
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Abstract
This invention provides a method for processing drain/source extension semiconductor transistor elements with super shallow connecting face including: providing a base, forming a grid structure on it with two walls and one up surface, forming a side wall on the sidewalls of the grid, implanting the ions to form super shallow connecting face doped area on said base at both sides of the grid structure, deposition a spacer layer on the side wall and its up surface of the grid, depositing a side wall layer on said spacer layer, carrying out a stress correction implantation process to change the state of the side wall layer from tensile to the compressive data and etching the side wall layer to a side wall.
Description
Technical field
The invention relates to a kind of manufacture of semiconductor, refer to a kind of diffusion of (defect-induced) instantaneous gain (transient enhanced diffusion, TED) manufacture of semiconductor method of effect that can suppress the defective initiation especially.The present invention is particularly suitable for being applied to possessing the manufacturing process of transistor unit of the drain/source elongated area of supershallow connection surface.
Background technology
Along with the semiconducter IC element is advanced into time micron or the miniaturization size below the rice grade how, MOS transistor element in the integrated circuit must be made into structure that the have supershallow connection surface drain/source of (ultra shallowjunction) extends (source/drain extension) zone, dwindles supervene as short-channel effect problems such as (short channel effect) to overcome component size.Yet it is shallow more that the problem of the drain/source elongated area of formation supershallow connection surface is that it connects face, and the sheet resistor of MOS transistor element is big more, the saturation current in the time of so will causing element operation (saturation current) deficiency.It is serious that this phenomenon seems on the PMOS transistor unit more.
Generally, the making of the drain/source elongated area of supershallow connection surface is to plant the shallow surface that enters silicon base with low energy ion cloth.Dwindling component size simultaneously, source electrode, drain electrode must improve with the concentration of dopant atoms of raceway groove, the face degree of depth of connecing reduces and the concentration of dopant atoms distribution shape has variation more significantly, therefore the behavior of grasping the doped chemical diffusion just seems quite important, but the diffusion of the interior doped chemical of silicon wafer is subjected to the influence of many process parameter and material characteristic, and for example (transient enhanced diffusion, TED) effect must manage to reduce in the instantaneous gain diffusion of defective initiation.
Therefore, this technical field needs a kind of method that can effectively suppress the instantaneous gain diffusion effect of aforementioned disadvantages initiation really at present, can avoid the doping profile of supershallow connection surface drain/source elongated area to produce change because of diffusion.
Summary of the invention
Main purpose of the present invention is providing a kind of manufacture of semiconductor, can effectively suppress the instantaneous gain diffusion effect that aforementioned disadvantages causes.
Another main purpose of the present invention is providing a kind of transistor unit manufacture method that possesses the drain/source elongated area of supershallow connection surface, can avoid the doping profile of supershallow connection surface drain/source elongated area to produce change because of the instantaneous gain diffusion effect.
According to preferred embodiment of the present invention, the invention provides the manufacture method that a kind of tool supershallow connection surface drain/source extends semiconductor transistor component, include: a substrate is provided; Form a grid structure in this substrate, it includes a two side and a upper surface; On the sidewall of this grid structure, form inclined to one side sidewall; Carry out first ion disposing process, this substrate in these grid structure both sides forms first doped region; On inclined to one side sidewall of this grid structure with and upper surface deposit a laying; Deposition one sidewall sublayer on this laying; Carry out a stress modifier cloth and plant processing procedure, the stress state that changes this sidewall sublayer changes to the comparatively state of compression (compressive) by stretched condition (tensile); And carry out a dry ecthing procedure, this sidewall sublayer is etched into sidewall.
The present invention provides a kind of manufacture method of semiconductor transistor component in addition, and the manufacture method of described semiconductor transistor component includes: a silicon base is provided; Form a grid structure on this silicon base, it includes a two side and a upper surface; On the sidewall of this grid structure, form inclined to one side sidewall; Carry out first ion disposing process, this silicon base in these grid structure both sides forms first doped region, as the drain/source extension of this semiconductor transistor component; On inclined to one side sidewall of this grid structure, its upper surface, and form a laying on this first doped region; Deposition one sidewall sublayer on this laying; Carry out a stress modifier cloth and plant processing procedure, the stress state that changes this sidewall sublayer changes to the comparatively state of compression by stretched condition; Carry out a dry ecthing procedure, this sidewall sublayer is etched into sidewall; And carry out second ion disposing process, this silicon base in these sub-both sides of sidewall forms second doped region, as the drain/source of this semiconductor transistor component.
Description of drawings
What Fig. 1 to Fig. 3 illustrated is the generalized section that the PMOS transistor unit of the drain/source elongated area that possesses supershallow connection surface is made in preferred embodiment according to the present invention;
Fig. 4 utilizes germanium and xenon to carry out the preferableization condition that cloth is planted processing procedure respectively with tabular;
It is the admixture that stress modifier cloth is planted processing procedure that Fig. 5 utilizes germanium (Ge) with tabular, at the sheet resistor (Rs) of the P type doped region of following silicon nitride sidewall sublayer stress value that can change of different doping conditions and supershallow connection surface.
Symbol description:
10～substrate
12～polysilicon gate construction
14～gate dielectric
16～partially sidewall
18～P type doped region
22～silicon dioxide laying
24～silicon nitride sidewall sublayer
30～stress modifier cloth is planted processing procedure
34～sidewall
48～drain/source zone
100～PMOS transistor unit
120～active area
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
See also Fig. 1 to Fig. 3, what it illustrated is the generalized section that the PMOS transistor unit 100 of the drain/source elongated area 18 that possesses supershallow connection surface is made in preferred embodiment according to the present invention.As shown in Figure 1, with insulation system, (shallow trenchisolation, STI) structure define active area 120 as shallow-channel insulation in N type substrate 10.N type substrate 10 is as N type silicon base.On active area 120, be formed with polysilicon gate construction 12.Between polysilicon gate construction 12 and the substrate 10 gate dielectric 14 is arranged, for example silicon dioxide etc.
On the sidewall of polysilicon gate construction 12, be formed with inclined to one side sidewall (offset spacer) 16.Sidewall 16 can be made of silicon dioxide partially.After forming inclined to one side sidewall 16, utilize ion disposing process, be implanted into P type admixture in polysilicon gate construction 12 substrate on two sides 10, boron ion for example forms the P type doped region 18 of supershallow connection surface.According to preferred embodiment of the present invention, the face that the connects degree of depth of P type doped region 18 is about in 30 dusts.
Subsequently, with chemical gaseous phase depositing process or with boiler tube, at deposition of silica laying 22 on the polysilicon gate construction 12 and on P type doped region 18.Silicon dioxide laying 22 can be with BTBAS (bis (tertiarybutylamine) silane) silicon dioxide that to be predecessor (precursor) produced with oxygen.
Then, cvd nitride sidewall silicon sublayer 24 on silicon dioxide laying 22.The deposition of silicon nitride sidewall sublayer 24 can adopt chemical vapour deposition (CVD) (chemical vapor deposition, CVD) processing procedure.According to preferred embodiment of the present invention, the thickness of silicon nitride sidewall sublayer 24 is about 600 to 700 dusts.Silicon nitride sidewall sublayer 24 stress at this moment still is stretched condition (tensile).
As shown in Figure 2, then a stress modifier (stressmodification) cloth is carried out in silicon nitride sidewall sublayer 24 plants processing procedure 30, being the heavily doped matter of neutrality electrically, for example germanium (germanium) or xenon (xenon) etc., plant energy between 25 to 150KeV with cloth, dosage is at 2E14 to 5E15atoms/cm
2Between condition under, be that the silicon nitride sidewall sublayer 24 of stretched condition (tensile) changes over the comparatively state of compression (compressive) with original stress.According to preferred embodiment of the present invention, stress modifier cloth plant processing procedure 30 the projection scope (projected range, Rp) its value should be an example with thickness 700 dusts less than the thickness of silicon nitride sidewall sublayer 24, Rp is preferable between 350 to 700 dusts.Fig. 4 utilizes germanium and xenon to carry out the preferableization condition that cloth is planted processing procedure 30 respectively with tabular.
As shown in Figure 3, then carry out a dry ecthing procedure, silicon nitride sidewall sublayer 24 is etched into sidewall 34 on polysilicon gate construction 12 sidewalls.Carry out ion disposing process subsequently again, in P type admixture implanted polysilicon grid structure 12 substrate on two sides 10, form the drain/source zone 48 of PMOS transistor unit 100.
It is the admixture that stress modifier cloth is planted processing procedure 30 that Fig. 5 utilizes germanium (Ge) with tabular, the sheet resistor (Rs) of silicon nitride sidewall sublayer 24 stress values that can change following of different doping condition and the P type doped region 18 of supershallow connection surface.As shown in Figure 5, plant energy when the cloth of germanium (Ge) and reach 100KeV, dosage is at 5E15atoms/cm
2Condition under, silicon nitride sidewall sublayer 24 stress values are by original 1.19E10dyne/cm
2(tensile) reduce to-2.27E9dyne/cm
2And the sheet resistor (Rs) of the P type doped region 18 of supershallow connection surface significantly is reduced to 1787ohm/sq by 4634ohm/sq (compressive).
Compared to prior art, because the present invention plants the stress value that processing procedure 30 changes silicon nitride sidewall sublayer 24 with stress modifier cloth, make it change over the comparatively state of compression (compressive) by original stretched condition (tensile), reduce the void defects (defect) of silicon face whereby, the boron dopant diffusion degree of implanted silicon substrate 10 is reduced, avoid the doping profile of supershallow connection surface drain/source elongated area to produce change, therefore can reach the sheet resistor of the P type doped region 18 that reduces supershallow connection surface and obtain the more shallow face that the connects degree of depth because of the instantaneous gain diffusion effect.
Claims (20)
1. a tool supershallow connection surface drain/source extends the manufacture method of semiconductor transistor component, and the manufacture method that described tool supershallow connection surface drain/source extends semiconductor transistor component includes:
One substrate is provided;
Form a grid structure in this substrate, it includes a two side and a upper surface;
On the sidewall of this grid structure, form inclined to one side sidewall;
Carry out an ion disposing process, this substrate in these grid structure both sides forms the shallow junction doped region;
On inclined to one side sidewall of this grid structure with and upper surface deposit a laying;
Deposition one sidewall sublayer on this laying;
Carry out a stress modifier cloth and plant processing procedure, the stress state that changes this sidewall sublayer changes to the comparatively state of compression by stretched condition; And
Carry out a dry ecthing procedure, this sidewall sublayer is etched into sidewall.
2. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this substrate is a silicon base.
3. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this grid structure is a polysilicon gate.
4. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, wherein is provided with gate dielectric between this grid structure and this substrate.
5. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this sidewall sublayer is constituted by silicon nitride.
6. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein to plant the implantation admixture of processing procedure be germanium or xenon to this stress modifier cloth.
7. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this stress modifier cloth is planted the admixture species of the implantation admixture of processing procedure for electrical neutrality.
8. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this stress modifier cloth is planted the implantation energy of processing procedure between 25 to 150KeV.
9. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein to plant the implantation admixture of processing procedure be germanium to this stress modifier cloth, implants energy 100KeV, and dosage is at 5E15atoms/cm
2
10. tool supershallow connection surface drain/source according to claim 1 extends the manufacture method of semiconductor transistor component, and wherein this shallow junction doped region is a P type doped region.
11. the manufacture method of a semiconductor transistor component, the manufacture method of described semiconductor transistor component includes:
One silicon base is provided;
Form a grid structure on this silicon base, it includes a two side and a upper surface;
On the sidewall of this grid structure, form inclined to one side sidewall;
Carry out first ion disposing process, this silicon base in these grid structure both sides forms first doped region, as the drain/source extension of this semiconductor transistor component;
On inclined to one side sidewall of this grid structure, its upper surface, and form a laying on this first doped region;
Deposition one sidewall sublayer on this laying;
Carry out a stress modifier cloth and plant processing procedure, the stress state that changes this sidewall sublayer changes to the comparatively state of compression by stretched condition;
Carry out a dry ecthing procedure, this sidewall sublayer is etched into sidewall; And
Carry out second ion disposing process, this silicon base in these sub-both sides of sidewall forms second doped region, as the drain/source of this semiconductor transistor component.
12. the manufacture method of semiconductor transistor component according to claim 11, wherein this stress modifier cloth is planted the admixture species of the implantation admixture of processing procedure for electrical neutrality.
13. the manufacture method of semiconductor transistor component according to claim 11, wherein to plant the implantation admixture of processing procedure be germanium or xenon to this stress modifier cloth.
14. the manufacture method of semiconductor transistor component according to claim 11, wherein this stress modifier cloth is planted the implantation energy of processing procedure between 25 to 150KeV.
15. the manufacture method of semiconductor transistor component according to claim 11, wherein to plant the implantation admixture of processing procedure be germanium to this stress modifier cloth, implants energy 100KeV, and dosage is at 5E15atoms/cm
2
16. the manufacture method of semiconductor transistor component according to claim 11, wherein this stress modifier cloth is planted processing procedure and is had the thickness of its value of projection scope less than this sidewall sublayer.
17. the manufacture method of semiconductor transistor component according to claim 16, wherein the thickness of this sidewall sublayer is 600 to 700 dusts.
18. the manufacture method of semiconductor transistor component according to claim 11, wherein this sidewall sublayer is constituted by silicon nitride.
19. the manufacture method of semiconductor transistor component according to claim 11 wherein is provided with gate dielectric between this grid structure and this silicon base.
20. the manufacture method of semiconductor transistor component according to claim 11, wherein this stress modifier cloth is planted the void defects that processing procedure can reduce this silicon base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410070964XA CN100388440C (en) | 2004-07-21 | 2004-07-21 | Manufacturing method of semiconductor transistor element with supershallow connection surface drain/source expansion |
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|---|---|---|---|
| CNB200410070964XA CN100388440C (en) | 2004-07-21 | 2004-07-21 | Manufacturing method of semiconductor transistor element with supershallow connection surface drain/source expansion |
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|---|---|
| CN1725454A true CN1725454A (en) | 2006-01-25 |
| CN100388440C CN100388440C (en) | 2008-05-14 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466255C (en) * | 2006-04-18 | 2009-03-04 | 联华电子股份有限公司 | Semiconductor structure and its manufacture method |
| US7642166B2 (en) | 2006-10-25 | 2010-01-05 | United Microelectronics Corp. | Method of forming metal-oxide-semiconductor transistors |
| CN101179028B (en) * | 2006-11-08 | 2010-10-13 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702986A (en) * | 1995-12-05 | 1997-12-30 | Micron Technology, Inc. | Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges |
| TW399302B (en) * | 1998-08-06 | 2000-07-21 | United Microelectronics Corp | Structure of titanium salicide and the method for forming the same |
| JP2002016246A (en) * | 2000-06-28 | 2002-01-18 | Sharp Corp | Manufacturing method of mos-type semiconductor transistor |
| US6602754B1 (en) * | 2001-02-02 | 2003-08-05 | Advanced Micro Devices, Inc. | Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer |
| JP3799277B2 (en) * | 2002-02-21 | 2006-07-19 | 松下電器産業株式会社 | Semiconductor device evaluation method and semiconductor device manufacturing method |
| US6858487B2 (en) * | 2003-01-02 | 2005-02-22 | United Microelectronics Corp. | Method of manufacturing a semiconductor device |
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2004
- 2004-07-21 CN CNB200410070964XA patent/CN100388440C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466255C (en) * | 2006-04-18 | 2009-03-04 | 联华电子股份有限公司 | Semiconductor structure and its manufacture method |
| US7642166B2 (en) | 2006-10-25 | 2010-01-05 | United Microelectronics Corp. | Method of forming metal-oxide-semiconductor transistors |
| CN101179028B (en) * | 2006-11-08 | 2010-10-13 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
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| Publication number | Publication date |
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| CN100388440C (en) | 2008-05-14 |
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