經濟部中央梂準局員工消費合作社印聚 A7 B7___ 五、發明説明（/ ) 本發明是有關於一種形成矽化鈦(Ti Salicide)之方法， 且特別是有關於一種應用於在邏輯製程(Logic Process)中線 寬在次0.25微米(Subquater Micron Line)上形成自對準矽化 鈦(Ti Salicide)的製造方法。 在現今超大型積體電路(Very Large Scale Integration)的 金屬化(Metallization)製程中，所採用的材料以鋁與鎢爲 主，鋁因爲其電阻率(Resistivity)較低，所以主要作用是作 爲元件間的導線，且多數以濺鍍法(Sputtering)來沉積。鎢 可以用化學氣相沉積法(CVD)來形成，所以階梯覆蓋(Step Coverage)能力較佳，加上本身極易形成較高揮發性的氟化 物，而沒有蝕刻上的困難，因此已廣爲各半導體廠應用在 作爲不同金屬間的插塞(Plugs)之用，以便將各層金屬加以 連接。 然而，由於鋁與矽的接觸界面極易形成尖峰現象 (Spiking) ’即使有加入適量的矽在鋁線中，也無法完全倖 免，加上鎢對其他材質的附著能力也不是十分理想，所以 在使用鎢及鋁這兩種金屬時，通常會在這兩種金屬與其他 材質之間，加入一層阻障層(Barrier Layer)的導電材料，以 避免鋁矽界面的尖峰現象，並提昇鎢對其他材質的附著能 力。一般常用的阻障層材料爲氮化鈦(Titanium Nitride ; TiN) 與金屬鈦搭配使用，Ti/TiN，在適當的溫度下(約500°C)， 與矽因交互擴散而形成一種電阻率很低的化合物-矽化鈦 (TiSi2)，以提昇金屬對砂進行歐姆式接觸(Ohmic Contact)的 能力。而當元件的積集度增加，使得M0S元件的汲極與 __3 本紙張尺度適用f國國家榡準（CNS ) A4規格(210X 297公釐） ' 2732twf.doc/006 ---------A------tr -m (請先閱讀背面之注意事項再填寫本頁) 經濟部中央梯準局貝工消费合作社印製 2732twf.doc/006 A7 B7 五、發明説明（2) 源極的電阻，逐漸上升到與MOS通道(Channel)的電阻相 當時，爲了調降汲極與源極的片電阻（Sheet Resistance)， 並確保金屬與MOS間的淺接面(Shallow Junction)的完整， 一種稱爲”自行對準金屬矽化物”製程的應用便逐漸開發， 此製程又簡稱Salicide。 請參考第1A圖至第1D圖，爲習知製作自行對準金屬 矽化鈦之製程剖面示意圖。如第1A圖所示，在一至少含 有MOS，並已定義主動(Active)與場氧化(Field Oxide)區域 16的基底10上以濺鍍方式沉積一層鈦金屬層18，此金屬 層18的厚度約在200A到1000A。接著，在含有氮氣的環 境中，進行第一快速加熱製程(Rapid Thermal Processing ; RTP)，此製程溫度約在600°C至650°C，使得沉積在基底10 表面的鈦金屬層與富含矽金屬的基底10反應形成結晶結 構爲C49的矽化鈦30a，位在閘極12與源極/汲極區14上 方，如第1B圖所示。由於金屬鈦在氮氣環境中會與氮氣 反應形成氮化鈦，因此將位在場氧化區16與閘極12周圍 間隙壁15上多餘的未反應金屬鈦或氮化鈦剝除，如第1C 圖所示。接下來進行第二快速加熱製程，溫度約在800°C 至900°C，以將原覆蓋在閘極12與源極/汲極區14上方C49 的矽化鈦30a轉換爲C54的矽化鈦30b，以上所述即爲習 知製造自行對準金屬矽化鈦之製程。 由於C49矽化鈦結構的片電阻(Sheet Resistance)高於 C54矽化鈦結構(C49矽化鈦的電阻約爲80/ζ Ω*αη至100 // Q*cm，而C54矽化鈦的電阻約爲13# Ω*αη至20μ Ω 4 本紙張尺度適用中國國家標率（CNS ) Α4規格（210X297公餐Ί " (請先閲讀背面之注意事項再填寫本頁) 2732twf.doc/006 B7 經濟部中央標準局貝工消费合作社印聚 五、發明説明（J) *cm)，在半導體製程中，尤其是當製程的線寬進入次0.25 微米或更小時，C49矽化鈦的存在將導致晶片電阻的增加。 然而，在進行第二快速加熱製程中，並不能完全將結構爲 C49的矽化鈦轉換爲C54的矽化鈦，部分C49矽化鈦與C54 矽化鈦會形成共存，而無法有效降低晶片整體的片電阻， 使得晶片導電性變差，而影響晶片性質。 因此本發明的主要目的就是在改善C49矽化鈦轉換成 C54矽化鈦之製程，以提高C49矽化鈦轉換成C54矽化鈦 的轉換率，降低晶片的片電阻，使晶片的導電性增強，以 改善晶片性質。 根據本發明之上述目的，提出一種應用於在邏輯製程 中線寬在次0.25微米上形成自對準金屬矽化鈦的製造方 法。在已定義主動與場氧化區，並已形成一 MOS的基底 上濺鍍一層鈦金屬，位在基底上。進行第一快速加熱製程 將此金屬鈦與積底矽反應形成C49矽化鈦，位在MOS的 閘極與源極/汲極區上，然後剝除其餘在場氧化層上未形成 C49矽化鈦的鈦/氮化鈦。接著，在場氧化層、C49矽化鈦 與閘極周圍的間隙壁上以電漿化學氣相沉積法(Plasma-Enhanced CVD ; PECVD)形成一高壓縮膜(Highly Compressive Film)，此高壓縮膜的材質可以氮化矽(SiN)與氮氧化矽(SiON) 中擇其一使用。而後再進行第二快速加熱製程，將C49矽 化鈦轉換爲C54矽化鈦，完成本發明所提出的改善自對準 金屬矽化鈦的製程方法。利用本發明所提出的製程方法， 可完全將C49矽化鈦結構在第二快速加熱製程中轉換爲 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公策)~ ---------------ix (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局员工消費合作社印掣 2732twf.doc/006 A7 _____B7_ 五、發明説明（分） C54矽化鈦結構，以降低因C49矽化鈦結構的存在而引起 的髙片電阻現象’使晶片的導電性增強，而所採用的氮化 矽膜也可用於阻隔高密度電漿化學氣相沉積介電層時之電 漿損害’以及作爲不留白接觸窗(Borderless Contact)的蝕刻 中止層，此外，此氮化矽膜亦與自對準接觸窗製程相容， 可避免在形成自對準接觸窗時，開口的過度偏差而對其他 元件造成損害。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1D圖是習知製作自行對準金屬矽化鈦之 剖面示意圖。 第2A圖至第2E圖是依據本發明所提出之改善製作自 行對準金屬矽化鈦之剖面示意圖。 圖式之標記說明： 10、20 :基底 12、22 : M0S之閘極 14、 24 : M0S之源極/汲極區 15、 25 :間隙壁 16、 26 :場氧化區 18、28 :鈦金屬層 30a、40a: C49矽化鈦結構 30b、40b : C54矽化鈦結構 6 本紙張尺度適用國家標準（CNS ) Α4ίϋ 210X 297公ΪΥ~ ---------士木------—1Τ / . (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 2732twf.doc/006 A7 __B7__ 五、發明説明（$ ) 42:高壓縮膜 實施例 請參照第2A圖至第2E圖，其繪示依照本發明一較佳 實施例的一種應用於邏輯製程中在次0.25微米線寬上製造 自行對準金屬矽化鈦之剖面示意圖。如第2A圖所示，在 一至少含有MOS，並已定義主動與場氧化區域26的基底 20上以濺鍍方式沉積一層鈦金靥層28，此金屬層28的厚 度約在200A到1000A。接著，在含有氮氣的環境中，進 行第一快速加熱製程，此製程溫度約在600°C至650°C，使 得沉積在基底20表面的鈦金屬層與富含矽金屬的基底20 反應形成結晶結構爲C49的矽化鈦40a，位在閘極22與源 極/汲極區24上方，如第2B圖所示。而由於金屬鈦會與 環境中的氮氣反應，形成氮化鈦，因此將位在場氧化區26 與閘極22周圍間隙壁25上多餘的未反應鈦或氮化鈦以選 擇性蝕刻將其剝除，如第2C圖所示。 請參考第2D圖，此時，在整個基底結構表面形成一 層高壓縮膜42,此高壓縮膜之材料可採用氮化矽與氮氧化 矽等選擇其一，因爲此兩種材料具有良好的舒展性與緻密 性，能緊密的覆蓋並壓縮位在此高壓縮膜下的C49矽化鈦 40a。接下來進行第二快速加熱製程，如第2E圖所示，此 製程溫度約在700°C至750°C，並可將C49矽化鈦40a結構 大幅轉換爲C54矽化鈦40b結構，而以上所述即爲依據本 發明所提出之製造自行對準金屬矽化鈦之製造方法。 由上述本發明較佳實施例可知，應用本發明具有下列 7 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公# j ~ " ~ ---^---^-----d.------ΐτ (請先閲讀背面之注意事項再填寫本頁) 2732twf.doc/006 A7 B7 五、發明説明（έ) 優點： 第一 ’本發明所提出的改善方法，可大幅增加C49 W 化鈦轉換成C54砂化鈦的轉換率’此乃因爲高壓縮膜可舒 展並緻密的覆蓋在C49矽化鈦層上，因此外力的壓縮力量 可幫助C49轉換成C54，以達到改善晶片性質。 第二’依據本發明所形成的高壓縮膜對後續製程中所 形成的氮化矽膜也可用於阻隔高密度電獎化學氣相沉積介 電層時之電漿損害，以及作爲不留白接觸窗的蝕刻中止 層，此外，此氮化矽膜亦與自對準接觸窗製程相容，可避 免在形成自對準接觸窗時，開口的過度偏差而對其他元件 造成損害。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ---------^------tT (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 度 4 A NsEmployees' Cooperatives of the Central Government Procurement Bureau of the Ministry of Economic Affairs, A7 B7___ 5. Description of the Invention (/) The present invention relates to a method for forming titanium silicide (Ti Salicide), and in particular, it relates to a method used in logic processes (Logic Process ) A method for manufacturing a self-aligned titanium silicide (Ti Salicide) on a subquater micron line with a center line width. In today's Very Large Scale Integration metallization process, the materials used are mainly aluminum and tungsten. Aluminum has a low resistivity, so it is mainly used as a component Between the wires, and most of them are deposited by sputtering. Tungsten can be formed by chemical vapor deposition (CVD), so the step coverage is better. In addition, it is easy to form highly volatile fluoride without the difficulty of etching, so it has been widely used. Each semiconductor factory is used as plugs between different metals in order to connect the layers of metal. However, because the contact interface between aluminum and silicon is extremely prone to spiking. 'Even if a suitable amount of silicon is added to the aluminum wire, it is not completely immune, and the adhesion of tungsten to other materials is not very satisfactory. When using two metals, tungsten and aluminum, a barrier layer conductive material is usually added between these two metals and other materials to avoid spikes at the aluminum-silicon interface and enhance the effect of tungsten on other materials. The adhesion of the material. The commonly used barrier layer material is titanium nitride (Titanium Nitride; TiN) used in combination with metal titanium, Ti / TiN, at a suitable temperature (about 500 ° C), and silicon form a resistivity due to cross-diffusion. Low compound-titanium silicide (TiSi2) to enhance the metal's ability to make ohmic contact with sand. And when the component accumulation increases, the drain of M0S components and __3 This paper size applies to the national standard (CNS) A4 specification (210X 297 mm) '2732twf.doc / 006 ------ --- A ------ tr -m (Please read the precautions on the back before filling out this page) Printed by the Central Laboratories of the Ministry of Economy, Shellfish Consumer Cooperative, 2732twf.doc / 006 A7 B7 V. Description of the invention ( 2) When the resistance of the source gradually rises to be equivalent to the resistance of the MOS channel, in order to reduce the sheet resistance of the drain and source, and ensure a shallow junction between the metal and the MOS (Shallow Junction) ) Complete, an application called a "self-aligned metal silicide" process has been gradually developed, this process is also referred to as Salicide. Please refer to Figures 1A to 1D for schematic cross-sectional views of the conventional process for making self-aligned metal titanium silicide. As shown in FIG. 1A, a titanium metal layer 18 is deposited on a substrate 10 that contains at least MOS and has defined Active and Field Oxide regions 16 by sputtering. The thickness of this metal layer 18 About 200A to 1000A. Then, in a nitrogen-containing environment, a first rapid thermal processing (RTP) process is performed, and the process temperature is about 600 ° C to 650 ° C, so that the titanium metal layer and the silicon-rich layer deposited on the surface of the substrate 10 The metal substrate 10 reacts to form a titanium silicide 30a having a crystal structure of C49, which is located above the gate 12 and the source / drain region 14, as shown in FIG. 1B. Since titanium metal reacts with nitrogen to form titanium nitride in a nitrogen environment, the excess unreacted metal titanium or titanium nitride located on the gap 15 between the field oxidation region 16 and the gate 12 is stripped, as shown in Figure 1C. As shown. Next, a second rapid heating process is performed at a temperature of about 800 ° C to 900 ° C to convert the titanium silicide 30a that originally covered C49 over the gate 12 and the source / drain region 14 to titanium silicide 30b that is C54. The above is the conventional process for manufacturing self-aligned metal titanium silicide. The sheet resistance of the C49 titanium silicide structure is higher than the C54 titanium silicide structure (the resistance of the C49 titanium silicide is about 80 / ζ Ω * αη to 100 // Q * cm, and the resistance of the C54 titanium silicide is about 13 # Ω * αη to 20μ Ω 4 This paper size applies to China National Standards (CNS) Α4 specifications (210X297 public meals) " (Please read the precautions on the back before filling this page) 2732twf.doc / 006 B7 Central Standard of the Ministry of Economic Affairs Printed by Cooper Consumer Co., Ltd. 5. Description of the invention (J) * cm) In the semiconductor process, especially when the line width of the process enters the sub-0.25 micron or less, the presence of C49 titanium silicide will increase the chip resistance. However, in the second rapid heating process, the titanium silicide with the structure of C49 cannot be completely converted to the titanium silicide of C54. Some C49 titanium silicide and C54 titanium silicide will coexist, which cannot effectively reduce the overall chip resistance of the chip. As a result, the conductivity of the wafer is deteriorated, which affects the properties of the wafer. Therefore, the main purpose of the present invention is to improve the process of converting C49 titanium silicide to C54 titanium silicide, so as to increase the conversion rate of C49 titanium silicide to C54 titanium silicide and reduce the crystal The chip resistance of the chip enhances the conductivity of the chip to improve the properties of the chip. According to the above purpose of the present invention, a manufacturing method for forming a self-aligned metal titanium silicide with a line width of less than 0.25 microns in a logic process is proposed. A layer of titanium metal is sputtered on the substrate that has defined active and field oxidation regions and has formed a MOS, and is located on the substrate. The first rapid heating process is performed to react this metal titanium with silicon substrate to form C49 titanium silicide, which is located at MOS gate and source / drain regions, and then strip the remaining titanium oxide / titanium nitride on the field oxide layer without C49 titanium silicide. Then, the field oxide layer, C49 titanium silicide and the gap around the gate Plasma-Enhanced CVD (PECVD) is used to form a highly compressed film on the wall. The material of this highly compressed film can be in silicon nitride (SiN) and silicon oxynitride (SiON). Use one of them. Then, the second rapid heating process is performed to convert C49 titanium silicide to C54 titanium silicide to complete the method for improving the self-aligned metal titanium silicide proposed by the present invention. Using the process method proposed by the present invention The C49 titanium silicide structure can be completely converted into 5 in the second rapid heating process. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). --------------- ix (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 2732twf.doc / 006 A7 _____B7_ V. Description of the Invention (C) Titanium Silicide Structure C54 to reduce the structure caused by C49 Titanium Silicide The phenomenon of chip resistance caused by the existence of 'enhanced the conductivity of the wafer, and the silicon nitride film used can also be used to block plasma damage during high-density plasma chemical vapor deposition dielectric layers' and as Etching stop layer for Borderless Contact. In addition, this silicon nitride film is also compatible with the self-aligned contact window process, which can avoid excessive deviation of the opening and other components when forming a self-aligned contact window. damage. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Figure 1D is a schematic cross-sectional view of conventionally made self-aligned metal titanium silicide. Figures 2A to 2E are schematic cross-sectional views of an improved self-aligned metal titanium silicide according to the present invention. Explanation of the marks in the figure: 10, 20: substrate 12, 22: gate 14 of M0S, 24: source / drain region of M0S 15, 25: spacer wall 16, 26: field oxide region 18, 28: titanium metal Layers 30a, 40a: C49 titanium silicide structure 30b, 40b: C54 titanium silicide structure 6 This paper is applicable to national standards (CNS) Α4ίϋ 210X 297297 ~ --------- Shimu ------ —1Τ /. (Please read the precautions on the back before filling out this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 2732twf.doc / 006 A7 __B7__ V. Description of the Invention ($) 42: Examples of high compression film Referring to FIG. 2A to FIG. 2E, there are shown schematic cross-sectional views of manufacturing self-aligned metal silicon silicide on a sub-0.25 micron line width in a logic process according to a preferred embodiment of the present invention. As shown in FIG. 2A, a titanium Au layer 28 is deposited by sputtering on a substrate 20 containing at least MOS and having defined active and field oxidation regions 26. The thickness of this metal layer 28 is about 200A to 1000A. Then, in a nitrogen-containing environment, a first rapid heating process is performed. The process temperature is about 600 ° C to 650 ° C, so that the titanium metal layer deposited on the surface of the substrate 20 reacts with the silicon-rich substrate 20 to form crystals. The titanium silicide 40a having a structure of C49 is located above the gate electrode 22 and the source / drain region 24, as shown in FIG. 2B. Since titanium metal reacts with nitrogen in the environment to form titanium nitride, the excess unreacted titanium or titanium nitride on the gap wall 25 around the field oxide region 26 and the gate electrode 22 is selectively etched to strip it. Divide, as shown in Figure 2C. Please refer to Figure 2D. At this time, a layer of high compression film 42 is formed on the entire surface of the base structure. The material of this high compression film can be selected from silicon nitride and silicon oxynitride, because these two materials have good stretch. The compactness and compactness can tightly cover and compress the C49 titanium silicide 40a located under this high compression film. Next, a second rapid heating process is performed. As shown in Figure 2E, the temperature of this process is about 700 ° C to 750 ° C, and the structure of C49 titanium silicide 40a can be greatly converted to the structure of C54 titanium silicide 40b. That is, a method for manufacturing self-aligned metal titanium silicide according to the present invention. From the above-mentioned preferred embodiments of the present invention, it can be known that the application of the present invention has the following 7 paper standards applicable to the Chinese National Standard (CNS) A4 specification (210X297 public # j ~ " ~ --- ^ --- ^ ----- d .------ ΐτ (Please read the precautions on the back before filling out this page) 2732twf.doc / 006 A7 B7 V. Description of the Invention (Strong) Advantages: First, the improvement method proposed by the present invention can be Significantly increase the conversion rate of C49 W titanium titanium to C54 sanded titanium 'This is because the high compression film can stretch and densely cover the C49 titanium silicide layer, so the compression force of external force can help C49 to C54 to achieve improvement Wafer properties. Secondly, the high compression film formed in accordance with the present invention can also be used to prevent plasma damage during high-density chemical vapor deposition dielectric layers, as well as silicon nitride films formed in subsequent processes. The etching stop layer of the contact window is left blank. In addition, the silicon nitride film is also compatible with the self-aligned contact window process, which can avoid excessive deviation of the opening and damage to other components when forming the self-aligned contact window. The present invention has been disclosed as above with a preferred embodiment. However, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the scope of the attached patent application. The definition shall prevail. --------- ^ ------ tT (Please read the notes on the back before filling in this page) The Central Standards Bureau of the Ministry of Economic Affairs Off-line Consumer Cooperatives Seal System 4 A Ns