經濟部中^、诺隹局另工消費合作祍印災 Δ 7 41 9T29_Ξ__ 五、發明説明（/ ) 發明領域： 本發明係關於一種積體電路之自動對準金屬矽化物製 程(salicide)，特別是關於一種於積體電路之自動對準金屬 矽化物製程中，以製作多層間隙壁結構（multilayer spacer)，及使用非均向性餓刻（anisotropic etch)和均向 性蝕刻（isotropic etch)造成間隙壁側向凹陷，來防止閘極 與源/汲極間因自動對準金屬矽化物橋接(bridging)，而造 成短路(short)的問題。 發明背景= 積體電路製程中當元件積集度（integrity)增加，M0S 元件尺寸縮小而導致閘極之電阻值上升，而且M0S元件的源 極與汲極的電阻逐漸上升至與M0S通道(channel)的電阻相 當，故爲了調降閘極、源極與汲極的片電阻（sheet resistance)，並確保金屬與M0S間的淺接面（shallow junction)完整，一種稱爲「自動對準金屬砂化物(self-aligned si 1 icide) 製程」 的應用 ，便逐漸普遍於 〇. 5 微米 以下的VLSI製程，此製程又簡稱爲Sal icide。 請參閱圖一，於半導體基板1上形成M0S電晶體結構， 包括閘氧化層4、複晶矽閘極(polygate)5、源極/汲極3、 及輕摻雜汲極(Light Doped Drain; LDD)2，其中亦包含間 極間隙壁6，習知技藝中該間隙壁結構6通常係由單層介電 材質所構成，而至多不會超過兩層介電材質。欲製作自動對 準金屬矽化物以降低電阻值，首先於基板表面濺鑛沉積一層 金屬薄膜(refractory metal fUm)7，然後藉由快速熱處理 2 —丨 J----：------t------ΐτ------0 (請先閱讀背面之注意事項再填寫本頁) 本纸佐反度適用中國國家標準（CNS ) A4规格（210X 297公釐） 經濟部中央嘌隼尚玛工消赍合作社印製 五、發明説明（>) 步驟(Rapid Thermal Processing; RTP)，使該金屬薄膜 7 與複晶矽閘極5表面及源極/汲極3之基板表面接觸處的矽 產生反應，而形成金屬矽化物；接著，移除未反應之金屬薄 膜，並再以一次快速熱處理步驟形成低阻值之金屬矽化物， 而完成自動對準金屬矽化物製程。 然而，於上述之習用製程中，不論單層或雙層間隙壁6 在金屬濺鐽沉積後，都與金屬薄膜7直接接觸，在複晶矽閘 極尺寸愈來愈小的情況下，往往需要提高反應溫度來形成低 阻值之金屬矽化物。當熱處理溫度提高的情況下，金屬薄膜 7如鈦(Ti)或鈷(C〇)或鉑(Pt)等因直接覆蓋於閘極5及間隙 壁6上，所以有機會也在含矽成分的間隙壁6上形成金屬矽 化物，且高溫下複晶矽閘極與源極/汲極中的矽亦可能擴散 至間隙壁，而如圖一 B所示，形成閘極5與源極/汲極3處 之金屬矽化物8a，及間隙壁6表面之金屬矽化物8b。因而， 後續去除未反應之金屬薄膜時，該間隙壁6上的金屬矽化物 8b無法有效去除，故導致閘極5與源極/汲極3間因自動對 準金屬砂化物8a、8b橋接(bridging)，而產生短路(short) 的問題。 發明之概述： 本發明之目的是提供一種積體電路之自動對準金屬矽 化物製程，以製作多層間隙壁結構，及使用非均向性蝕刻和 均向性蝕刻造成間隙壁表面側向凹陷，來防止閘極與源極/ 汲極間短路的問題。 本發明是利用下列技術手段來達到上述之各項目的：首 j----:,------裝------訂------線 {請先聞讀背面之注意事項再填寫本頁) 本舐張尺度適用中國國家標準（CNS ) Λ4規格（2丨0X297公釐） 經濟部中央樣準局VHX消費合作社印梵 ,,4+9 7 2g- 419729_^__ 五、發明説明（、） 先，提供一已具有閘極結構的半導體基板，在其上依序沉積 至少三層之介電層，並藉由至少一次非均向性蝕刻及至少一 次均向性蝕刻形成閘極之間隙壁結構，其中均向性蝕刻會對 其中某種介電層材質造成正向及側向凹陷；接著，以離子植 入在基板上形成源/汲極；再接著，濺鍍一層鈦或鈷或鉑金 屬薄膜，經熱處理後於閘極及基板表面上形成不連續的自動 對準金屬矽化物。 圖式簡要說明： 圖一 A〜B爲習知技藝中積體電路之自動對準金屬矽化 物製程剖面示意圖。 圖二爲本發明中第一及第二實施例之自動對準金屬矽 化物前段製程剖面示意圖。 圖三A〜C爲本發明中第一實施例之自動對準金屬矽化 物中段製程剖面示意圖。 圖四A〜B爲本發明中第二實施例之自動對準金屬矽化 物中段製程剖面示意圖。 圖五爲本發明中第一實施例之自動對準金屬矽化物後 段製程剖面示意圖。 圖六爲本發明中第二實施例之自動對準金屬矽化物後 I—^------¢------ΐτ----^---^ (諳先閱讀背面之注意事項再填寫本頁) 段製程剖面示意圖。 圖號說明： 1-半導體基板 2- LDD 3-源/汲極 4- 閘氧化層 5_複晶矽閘極 6- 間隙壁 _ 4 本紙張尺度適用中國围家標隼（CNS〉A4規格（210X297公釐） A7 B7 8a，8b-金屬砂化物 20- LDD 40-閘氧化層 60-第一介電層 80-第三介電層 100-金屬矽化物 —W 9729 - — - - — .. —... ▲ · · - I — 五、發明説明（0 ) 7-鈦或鈷或鉑金屬 10-半導體基板 30-源/汲極 50-複晶矽閘極 70-第二介電層 90-第四介電層 發明詳細說明： 本發明將以四層介電層間隙壁結構做爲實施例來詳細 說明本發明。然而，本發明不限應用於四層介電層間隙壁結 構，而係適用於至少三層介電層間隙壁結構。 · 【第一實施例】請參考圖二，首先，提供一半導體基板 10 ’所述半導體基板10上已定義有複晶矽閘極結構50、閘 氧化層40，並完成LDD離子佈植而形成LDD 20。接著，於 所述半導體基板1G上，依序沉積材質不連續之第一介電層 60、第二介電層70、第三介電層8G及第四介電層90，本 實施例中第一介電層60係爲氧化矽層(Si〇2)，以化學氣相沉 積法(CVD)形成，其厚度係介於1G0〜3GQ埃之間；第二介 電層70係爲氮化矽層(Si抓），以化學氣相沉積法(CVD)形 成，其厚度係介於100〜5GG埃之間；第三介電層80係爲 氧化矽層(si〇2)，以化學氣相沉積法(cro)形成，其厚度係介 於100〜500埃之間;第四介電層90係爲氧化砂層(Si3^〇， 以化學氣相沉積法(CVD)形成，其厚度係介於1〇〇〜印0埃 之間。 接著，請參考圖三A，對於所述之第四介電層90及第三 ----ί------裝------訂------線 {討先間讀背面之注意事項再續荇本頁) ιΊ •ii <ν 氺紙讥尺政述州十闷阄家標準U’NS ) Λ4規格（21〇；< 297公尨） 經濟部中夬標嗥局員工消f合作枉印¾ 419729 i 44 9 T 2各 五、發明説明（f) 介電層80進彳了一般介電層之非均向性蝕刻（anisotropic etch)，以完成部份之閘極間隙壁結構蝕刻係停止在第二介 電層70上。再接著，請參考圖三B，利用氧化矽與氮化矽 之蝕刻選擇比，對於所述之第三介電層80進行均向性蝕刻 (isotropic etch)，而在第三介電層80的上方及側邊形成 正向及側向凹陷。隨後，請參考圖三C，再進行一次非均向 性蝕刻，以形成完整之複晶矽閘極之間隙壁結構，其中所述 間隙壁表面具有局部凹陷；然後，即可進行離子佈植，以形 成源極及汲極30，並以回火步驟(anneal)穩定源/汲極30 的結構。 最後，請參考圖五，以磁控DC濺鍍方式沉積一層厚度 約在200〜1〇〇〇埃的金屬鈦(Ti)，亦可選用鈷(Co)或鉑(Pt) 等；然後，進行第一快速熱處理步驟(RTP-1)，在高溫中使 所述金屬膜反應形成自動對準金屬矽化物，即金屬矽化物 100，其中RTP-1的溫度係介於40Q〜80G°C ;之後，以濕 蝕刻移除未反應之剩餘鈦金屬，再進行溫度介於6GG〜900T 之第二快速熱處理步驟(RTP-2)。由於本實施例所製作之間 隙壁具有一處側向凹陷，被濺鍍之金屬層在該側向凹陷處呈 現不連續’因此熱處理後不會於該凹陷處形成自動對準金屬 矽化物’故可避免閘極50與源極/汲極30間自動對準金屬 矽化物橋接。 【第二實施例】本實施例與第一實施例之不同處在於以 不同之蝕刻順序形成閘極間隙壁。首先，請再次參考圖二， 提供一半導體基板10，所述半導體基板1Q上已定義有複晶 6 本纸張尺度適用中國國家標辛（CNS ) Λ4规格（2ΪΟ.Χ 297公後） I-----V------裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 419729 五、發明説明（t) 矽閘極結構50、閘氧化層40，並完成LDD離子佈植而形成 LDD 20。接著，於所述半導體基板10上，依序沉積材質不 連續之第一介電層60、第二介電層70 '第三介電層80及 第四介電層90，本實施例中第一介電層60係爲氧化矽層 (SiOO，以化學氣相沉積法(CVD)形成，其厚度係介於1〇〇〜 300埃之間；第二介電層7G係爲氮化矽層(Si抓），以化學氣 相沉積法(CVD)形成，其厚度係介於1G0〜5GQ埃之間；第 三介電層8G係爲氧化矽層(Si〇2)，以化學氣相沉積法(CVD) 形成，其厚度係介於1G0〜5GG埃之間；第四介電層90係 爲氧化矽層(Si3N4)，以化學氣相沉積法(CVD)形成，其厚度 係介於100〜500埃之間。 經濟部中央橾準局員工消費合作让印裝 (請先閱讀背面之注意事項再填寫本頁) 接著，請參考圖四A，對於所述之第四介電層90、第三 介電層80、第二介電層70及第一介電層60進行一般介電 層之非均向性蝕刻(anisotropic etch)，以完成完整之閘極 間隙壁結構。再接著，請參考圖四B，利用氧化矽與氮化砂 之蝕刻選擇比，對於所述之第三介電層80及第一介電層60 進行均向性触刻（isotropic etch)，而在第三介電層80及 第一介電層60的上方及側邊形成正向及側向凹陷，以形成 表面具有局部凹陷之複晶矽閘極間隙壁結構；然後，即可進 行離子佈植，以形成源極及汲極30，並以回火步驟(anneal) 穩定源/汲極30的結構。 最後，請參考圖六，以磁控DC濺鍍方式沉積一層厚度 約在200〜1000埃的金屬鈦(Ti)，亦可選用鈷(Co)或舶(Pt) 等；然後，進行第一快速熱處理步驟(RTP-1)，在高溫中使 7 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2!0X 2〔彡7公揸） A7 五、發明説明（) 所述金屬鈦反應形成自動對準金屬矽化物，即金屬矽化物 1⑽，其中RTP-1的溫度係介於40(T8()0°C ;之後，以濕蝕 刻移除未反應之剩餘鈦金屬，再進行溫度介於600〜900°C 之第二快速熱處理步驟(RTP-2)。由於本實施例所製作之間 隙壁具有兩處側向凹陷，被濺鍍之金屬層在該側向凹陷處呈 現不連續’因此熱處理後不會於該凹陷處形成自動對準金屬 矽化物，故可避免閘極50與源極/汲極30間自動對準金屬 矽化物橋接。 上述是以四層介電層間隙壁結構做爲實施例，然而，本 發明不限應用於四層介電層間隙壁結構，而可適用於三層及 三層以上材質不連續之多層介電層間隙壁結構，其中所述多 層介電層間隙壁之總厚度係不超過2000埃。其中三層及三 層以上之多層介電層的材質可依製程之設計，採用氧化矽 (oxide)、氮化砂(nitride)、氧化氮化砂(oxynitride)等， 而該多層介電層的最外一層則係選用氮化砂（silicon nitride)、氧化氮^化砂(oxynitride)等含氮成分之砂化物。 本發明之特徵在於：1.提供至少三層材質不連續之介 電層製作間隙壁；2.藉由不限順序之至少一次非均向性蝕 刻及至少一次均向性蝕刻，形成表面具有局部凹陷之間隙壁 結構。而由上述之特徵可達成防止閘極與源極/汲極間因自 動對準金屬矽化物相連而短路之目的。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明瞭，適當而作 些微的改變與調整’仍將不失本發明之要義所在，亦不脫離 _____-_^——The Ministry of Economic Affairs ^, the Novotel Bureau, another industrial and consumer cooperation, the seal of disaster Δ 7 41 9T29_Ξ__ V. Description of the invention (/) Field of the invention: The present invention relates to an automatic alignment metal silicide process for integrated circuits. It is about an auto-aligned metal silicide process for integrated circuits to make multilayer spacer structures, and the use of anisotropic etch and isotropic etch The gap wall is recessed laterally to prevent the short circuit caused by the self-aligned metal silicide bridging between the gate and the source / drain. Background of the Invention = When the integration of the component increases in the integrated circuit manufacturing process, the size of the M0S component shrinks and the resistance of the gate increases, and the resistance of the source and drain of the M0S component gradually increases to the channel of the M0S. ) Have the same resistance, so in order to reduce the sheet resistance of the gate, source, and drain, and ensure that the shallow junction between the metal and M0S is complete, a type called "automatic metal sand alignment" The application of "self-aligned si 1 pesticide" process has gradually become common in VLSI processes below 0.5 microns, and this process is also referred to as Salicide. Referring to FIG. 1, a MOS transistor structure is formed on a semiconductor substrate 1, which includes a gate oxide layer 4, a polycrystalline silicon gate (polygate) 5, a source / drain 3, and a lightly doped drain (Light Doped Drain; LDD) 2, which also includes an inter-electrode spacer wall 6. In the conventional art, the spacer structure 6 is usually composed of a single-layer dielectric material, and at most it does not exceed two layers of dielectric material. To make automatic alignment metal silicide to reduce the resistance value, first deposit a metal film (refractory metal fUm) 7 on the surface of the substrate, and then by rapid heat treatment 2 — 丨 J ----: ------ t ------ ΐτ ------ 0 (Please read the notes on the back before filling in this page) The reversal of this paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) Ministry of Economic Affairs Printed by Central Purity Shangma Industrial Co., Ltd. V. Invention Step (Rapid Thermal Processing; RTP), the metal thin film 7 and the surface of the polysilicon gate 5 and the substrate of the source / drain 3 The silicon at the surface contact reacts to form a metal silicide. Then, the unreacted metal thin film is removed, and a low-resistance metal silicide is formed by a rapid heat treatment step to complete the automatic alignment metal silicide process. However, in the above-mentioned conventional manufacturing process, regardless of whether the single-layer or double-layer spacer 6 is in direct contact with the metal thin film 7 after the metal is sputtered, it is often necessary to reduce the size of the polycrystalline silicon gate. Increasing the reaction temperature to form a low resistance metal silicide. When the heat treatment temperature is increased, the metal thin film 7 such as titanium (Ti), cobalt (C0), or platinum (Pt) is directly covered on the gate electrode 5 and the barrier wall 6, so there is a chance that it is also contained in the silicon-containing component. Metal silicide is formed on the barrier wall 6, and the silicon in the polycrystalline silicon gate and the source / drain may also diffuse to the barrier wall at a high temperature. As shown in FIG. 1B, the gate 5 and the source / drain are formed. A metal silicide 8a at the pole 3 and a metal silicide 8b on the surface of the spacer 6 are provided. Therefore, when the unreacted metal thin film is subsequently removed, the metal silicide 8b on the spacer 6 cannot be effectively removed, so that the gate 5 and the source / drain 3 are automatically aligned to bridge the metal sand 8a, 8b ( bridging), and the problem of shorts. Summary of the Invention: The purpose of the present invention is to provide an automatic alignment metal silicide process for integrated circuits to fabricate a multi-layered spacer structure, and use the anisotropic etching and the isotropic etching to cause the surface of the spacer to be laterally depressed. To prevent the short circuit between the gate and source / drain. The present invention uses the following technical means to achieve the above-mentioned objects: first j ----:, -------- install -------- order ------ line {please read the back first Please pay attention to this page and fill in this page again) This leaflet scale is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) Yinfan, VHX Consumer Cooperative, Central Sample Bureau, Ministry of Economic Affairs, 4 + 9 7 2g- 419729 _ ^ __ V. Description of the Invention (,) First, a semiconductor substrate having a gate structure is provided, and at least three dielectric layers are sequentially deposited thereon, and at least one anisotropic etching and at least one isotropic layer are formed thereon. The spacer structure of the gate is formed by etching, and the isotropic etching will cause a positive and lateral depression of one of the dielectric layer materials; then, the source / drain is formed on the substrate by ion implantation; and then, the sputtering A layer of titanium, cobalt, or platinum metal film is plated, and a discontinuous self-aligned metal silicide is formed on the gate and the substrate surface after heat treatment. Brief description of the drawings: Figures A ~ B are cross-sectional schematic diagrams of the process of automatically aligning metal silicides of integrated circuits in conventional techniques. FIG. 2 is a schematic cross-sectional view of the front-end process of the automatic alignment metal silicide according to the first and second embodiments of the present invention. 3A to 3C are schematic cross-sectional views of a process for automatically aligning a middle section of a metal silicide according to the first embodiment of the present invention. Figures 4A ~ B are schematic cross-sectional views of the middle process of the automatic alignment metal silicide in the second embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a process for automatically aligning metal silicide in the first embodiment of the present invention. Figure 6 is the second embodiment of the present invention after automatic alignment of metal silicide I — ^ ------ ¢ ------ ΐτ ---- ^ --- ^ (谙 Read the first Note that please fill in this page again). Description of drawing number: 1-semiconductor substrate 2- LDD 3-source / drain 4-gate oxide layer 5_multi-crystalline silicon gate 6-spacer_ 4 This paper size is applicable to China Weijia standard (CNS> A4 specification ( 210X297 mm) A7 B7 8a, 8b-metal sand compound 20- LDD 40-gate oxide layer 60-first dielectric layer 80-third dielectric layer 100-metal silicide—W 9729-—--— .. —... ▲ · ·-I — V. Description of the Invention (0) 7- Titanium or Cobalt or Platinum Metal 10- Semiconductor Substrate 30- Source / Drain 50- Compound Silicon Gate 70- Second Dielectric Layer 90 -Detailed description of the fourth dielectric layer invention: The present invention will be described in detail by taking a four-layer dielectric layer spacer structure as an example. However, the present invention is not limited to a four-layer dielectric layer spacer structure, and It is suitable for at least three dielectric spacer structures. [First Embodiment] Please refer to FIG. 2. First, a semiconductor substrate 10 is provided. The semiconductor substrate 10 has a polycrystalline silicon gate structure 50, The gate oxide layer 40 is gated, and LDD ion implantation is completed to form LDD 20. Then, on the semiconductor substrate 1G, discontinuous materials are sequentially deposited. The first dielectric layer 60, the second dielectric layer 70, the third dielectric layer 8G, and the fourth dielectric layer 90. In this embodiment, the first dielectric layer 60 is a silicon oxide layer (SiO2). It is formed by chemical vapor deposition (CVD), and its thickness is between 1G0 ~ 3GQ. The second dielectric layer 70 is a silicon nitride layer (Si), and is formed by chemical vapor deposition (CVD). The thickness is between 100 and 5 GG; the third dielectric layer 80 is a silicon oxide layer (SiO2), which is formed by a chemical vapor deposition (cro) method, and the thickness is between 100 and 500 Angstroms. The fourth dielectric layer 90 is an oxide sand layer (Si3 ^ 〇, formed by a chemical vapor deposition (CVD) method, and its thickness is between 100 and 0 Angstroms. Next, please refer to FIG. 3A For the fourth dielectric layer 90 and the third ---- ί ------ installation ------ order ------ line {discuss the precautions on the back before reading (Continued on this page) ιii • ii < ν 讥 Paper Ruler State Standards U'NS 4 Specification (21〇; < 297 Public Offices) Employees of the Ministry of Economic Affairs, China Bureau of Standards and Commerce Seal ¾ 419729 i 44 9 T 2 each 5. Explanation of the invention (f) The dielectric layer 80 has been incorporated into the non-uniformity of the general dielectric layer Etching (anisotropic etch), to complete the portion of the gate line spacer structure the etch stops on the second dielectric layer 70. Then, referring to FIG. 3B, using the etching selection ratio of silicon oxide and silicon nitride, the third dielectric layer 80 is subjected to isotropic etch, and the third dielectric layer 80 is subjected to isotropic etch. The upper and side edges form forward and side depressions. Subsequently, referring to FIG. 3C, another anisotropic etching is performed to form a complete spacer structure of the polycrystalline silicon gate, wherein the surface of the spacer has a local depression; then, ion implantation can be performed. The source and drain 30 are formed, and the structure of the source / drain 30 is stabilized by an annealing process. Finally, please refer to Fig. 5. A layer of metal titanium (Ti) with a thickness of 200 ~ 1000 Angstroms is deposited by magnetron DC sputtering, and cobalt (Co) or platinum (Pt) can also be used. The first rapid heat treatment step (RTP-1), the metal film is reacted to form an auto-aligned metal silicide at a high temperature, that is, the metal silicide 100, wherein the temperature of the RTP-1 is between 40Q ~ 80G ° C; Then, the remaining unreacted titanium metal is removed by wet etching, and then a second rapid heat treatment step (RTP-2) with a temperature between 6GG ~ 900T is performed. Since the gap wall produced in this embodiment has a lateral depression, the sputtered metal layer shows discontinuity at the lateral depression, so no automatic alignment metal silicide will be formed at the depression after heat treatment. This prevents the metal silicide bridge from automatically aligning between the gate 50 and the source / drain 30. [Second Embodiment] The difference between this embodiment and the first embodiment is that the gate spacers are formed in different etching sequences. First, please refer to FIG. 2 again to provide a semiconductor substrate 10, which has a compound crystal 6 defined on the semiconductor substrate 1Q. The paper size is applicable to the Chinese National Standard Xin (CNS) Λ4 specification (2ΪΟ.χ 297). I- ---- V ------ install ------ order ------ line (please read the precautions on the back before filling this page) 419729 V. Description of the invention (t) Silicon gate The structure 50, the gate oxide layer 40, and the LDD ion implantation are completed to form the LDD 20. Next, on the semiconductor substrate 10, a first dielectric layer 60, a second dielectric layer 70 ', a third dielectric layer 80, and a fourth dielectric layer 90, which are discontinuous in material, are sequentially deposited. A dielectric layer 60 is a silicon oxide layer (SiOO, formed by chemical vapor deposition (CVD), and the thickness is between 100 and 300 angstroms. The second dielectric layer 7G is a silicon nitride layer. (Si scratch), formed by chemical vapor deposition (CVD), the thickness of which is between 1G0 ~ 5GQ angstroms; the third dielectric layer 8G is a silicon oxide layer (SiO2), which is deposited by chemical vapor CVD method, the thickness of which is between 1G0 ~ 5GG angstrom; the fourth dielectric layer 90 is a silicon oxide layer (Si3N4), which is formed by chemical vapor deposition (CVD), and the thickness is between 100 and 100 ~ 500 Angstroms. Consumers' cooperation for printing by the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Then, please refer to Figure 4A. For the fourth dielectric layer 90, The third dielectric layer 80, the second dielectric layer 70, and the first dielectric layer 60 are subjected to anisotropic etch of a general dielectric layer to complete a complete gate spacer structure. Next, referring to FIG. 4B, an isotropic etch is performed on the third dielectric layer 80 and the first dielectric layer 60 by using an etching selection ratio of silicon oxide and nitride nitride. Positive and lateral depressions are formed on the third dielectric layer 80 and the first dielectric layer 60 on the sides and sides to form a polycrystalline silicon gate spacer structure with a local depression on the surface; then, ion implantation can be performed. To form a source and a drain 30, and stabilize the structure of the source / drain 30 by an annealing process. Finally, please refer to FIG. 6 to deposit a layer having a thickness of about 200 to 1000 angstroms by magnetron DC sputtering. The metal titanium (Ti) can also be selected from cobalt (Co) or Pt; then, the first rapid heat treatment step (RTP-1) is performed to apply 7 paper sizes to the Chinese National Standard (CNS) at high temperature. Λ4 specification (2! 0X 2 [彡 7 公 揸) A7 5. Description of the invention () The metal titanium reacts to form an auto-aligned metal silicide, namely metal silicide 1⑽, where the temperature of RTP-1 is between 40 ( T8 () 0 ° C; After that, remove the unreacted remaining titanium metal by wet etching, and then perform the temperature between 600 ~ 900 ° C The second rapid heat treatment step (RTP-2). Because the gap wall produced in this embodiment has two lateral depressions, the sputtered metal layer appears discontinuous at the lateral depressions, so it will not The self-aligned metal silicide is formed at the recess, so that the automatic alignment metal silicide bridge between the gate 50 and the source / drain 30 can be avoided. The above uses the four-layer dielectric spacer structure as an example. However, The present invention is not limited to a four-layer dielectric spacer structure, but can be applied to a three-layer or more discontinuous multi-layer dielectric spacer structure. The total thickness of the multi-layer dielectric spacer is Not more than 2000 Angstroms. Among them, the material of the multi-layer dielectric layer with three or more layers can be designed according to the manufacturing process, and silicon oxide (nitride), nitrided oxide (nitride), oxynitride, etc. are used. The outermost layer is selected from nitrogen-containing sands such as silicon nitride and oxygen oxide. The invention is characterized in that: 1. providing at least three dielectric discontinuous layers of material to make the partition wall; and 2. forming at least one surface with partial anisotropic etching and at least one isotropic etching in an unlimited order Depressed spacer structure. The above features can prevent the short circuit between the gate and the source / drain due to the automatic alignment of the metal silicide. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that appropriate and slight changes and adjustments will not lose the essence of the present invention. , And do not leave _____-_ ^ ——
¾先閲讀背面之注意事項再'本頁J 裝.¾ Read the precautions on the back before installing on this page.
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A7 B7 五、發明説明（^) 本發明之精神和範圍，故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 (誚先閱讀背面之注意事項再填艿本頁)A7 B7 V. Description of the Invention (^) The spirit and scope of the present invention should be regarded as further implementation of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. (Please read the notes on the back before filling this page)
本咕^尺度鸿圯个《因家標苹（<^阽）六4规格（210/297公犮）Ben Gu ^ Hong Hong a "Because of the standard apple (& ^^) 6 4 specifications (210/297 Gong)