CN100466255C - Semiconductor structure and its manufacture method - Google Patents
Semiconductor structure and its manufacture method Download PDFInfo
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- CN100466255C CN100466255C CNB2006100752831A CN200610075283A CN100466255C CN 100466255 C CN100466255 C CN 100466255C CN B2006100752831 A CNB2006100752831 A CN B2006100752831A CN 200610075283 A CN200610075283 A CN 200610075283A CN 100466255 C CN100466255 C CN 100466255C
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Abstract
The disclosed semi-conductor structure comprises: a substrate with a first/second trap area as the first/second conductive type; a first MOS transistor that belongs to the first conductive type and is arranged on the second trap area; and a second MOS transistor that belongs to the second conductive type and is set on the first trap area, wherein the first MOS transistor comprises a grid structure set on the second trap area, and a strain layer as first conductive type set on the opening of second trap area. The difference of lattice constant between the strain layer near the bottom of opening and substrate is less than the difference between the strain layer away the opening bottom and the substrate.
Description
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, relate in particular to the strained layer that mixes as a kind of semiconductor structure of source/drain electrode and preparation method thereof.
Background technology
Metal oxide semiconductor transistor is a very important element in the present very lagre scale integrated circuit (VLSIC) (VLSI circuit).The scope of its application very extensively, microprocessor, semiconductor memory component, power component or the like such as, all can metal oxide semiconductor transistor as its basic formation unit.
In general nanoscale technology, in order to increase the element efficiency of metal oxide semiconductor transistor, can be prior to forming opening in the grid structure substrate on two sides, the semi-conducting material (as SiGe) that will produce strain is then inserted in the opening with as source/drain electrode, improves electronics or the hole mobility (mobility) in raceway groove.
Figure 1A～1B is the making flow process profile of existing a kind of metal oxide semiconductor transistor.At first, please refer to Figure 1A, substrate 100 is provided.Be formed with well region 101 in the substrate 100.Then, utilize the technology of generally knowing to form grid structure 102 on well region 101, it comprises the gate dielectric layer 104 and grid 106 that is formed in regular turn in the substrate 100.Then, on the sidewall of grid structure 102, form clearance wall 108.Subsequently, be that mask carries out etch process with grid structure 102 with clearance wall 108, remove part substrate 100 and formation opening 110.
Then, please refer to Figure 1B, form strained layer 112 with as source/drain electrode in opening 110, and make the surface of strained layer 112 be higher than the surface of substrate 100, its raised area label is 113.Afterwards, on grid structure 102 and strained layer 112, form self-aligned metal silicate layer 114.
Because the surface of strained layer 112 is higher than the surface of substrate 100, therefore can reduce or eliminate the stress influence that metal silicide layer 114 is produced.In addition, in order to improve the suffered stress of strained layer 112, be example with the P-type mos transistor, can in opening 110, insert germanium concentration greater than 20% sige alloy layer, or the thickness of sige alloy layer increased, that is form the darker opening 110 of the degree of depth.
Yet the thickness of sige alloy layer can be inversely proportional to the concentration of germanium, that is to say, the concentration of germanium is higher, and the thickness of sige alloy layer is thinner.In addition, the concentration of germanium is higher, and the lattice constant of sige alloy layer also can heal greatly, makes that the lattice dimensions difference of sige alloy layer and substrate is bigger, and produces defective easily between the knot of sige alloy layer and substrate, and then influence element efficiency.In addition, when carrying out self-aligned metal silicate technology, germanium also can enter in the metal silicide layer and reduce its quality.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor structure, it utilizes the inconsistent strained layer of lattice constant as source/drain electrode, differs too much because of the lattice size of strained layer and substrate avoiding, and produces defective at the knot of strained layer and substrate.
Semiconductor structure of the present invention comprises first metal oxide semiconductor transistor of a substrate, first conductivity type and second metal oxide semiconductor transistor of second conductivity type.First well region of first conductivity type and second well region of second conductivity type are arranged in the substrate, and wherein first metal oxide semiconductor transistor is disposed on second well region, and second metal oxide semiconductor transistor is disposed on first well region.First metal oxide semiconductor transistor comprises first strained layer of the first grid structure and first conductivity type.Wherein, the first grid structural arrangements and has first opening in second well region of its both sides on second well region.First strained layer is disposed in first opening, this first strained layer in the difference between the lattice constant of the lattice constant of the part of contiguous first open bottom and substrate less than it away from the difference between the lattice constant of the lattice constant of the part of first open bottom and substrate.
In a preferred embodiment of the invention, the lattice constant distribution gradient of aforementioned first strained layer.
In certain embodiments, above-mentioned first conductivity type is the P type, and first strained layer in the lattice constant of the part of contiguous first open bottom less than lattice constant away from the part of first open bottom.The material of this kind first strained layer for example is a sige alloy.
In further embodiments, above-mentioned first conductivity type is the N type, and first strained layer in the lattice constant of the part of contiguous first open bottom greater than lattice constant away from the part of first open bottom.The material of this kind first strained layer for example is a carborundum.
In an embodiment of the present invention, above-mentioned second metal oxide semiconductor transistor comprises the second grid structure that is disposed on first well region, and the source/drain region of second conductivity type, and it is disposed in first well region of second grid structure both sides.This moment, the aforesaid semiconductor structure can also comprise the silicon layer that is disposed on first strained layer, and a metal silicide layer, and it is disposed on aforementioned silicon layer, source/drain region, first grid structure and the second grid structure.
In another embodiment, above-mentioned second metal oxide semiconductor transistor comprises the second grid structure that is disposed on first well region, and the source/drain region of second conductivity type, be disposed at the sidewall and the below of second opening in first well region of second grid structure both sides.This moment, the aforesaid semiconductor structure can also comprise the silicon layer that is disposed on first strained layer, and a metal silicide layer, and it is disposed on aforementioned silicon layer, source/drain region, first grid structure and the second grid structure.
In another embodiment, above-mentioned second metal oxide semiconductor transistor comprises the second grid structure that is disposed on first well region, and second strained layer of second conductivity type, and it is disposed in second opening in first well region of second grid structure both sides.This second strained layer in the difference between the lattice constant of the lattice constant of the part of contiguous second open bottom and substrate preferably less than it away from the difference between the lattice constant of the lattice constant of the part of second open bottom and substrate.When aforementioned first conductivity type be the P type, when second conductivity type is the N type, first strained layer in the lattice constant of the part of contiguous first open bottom less than its lattice constant away from the part of first open bottom, and second strained layer in the lattice constant of the part of contiguous second open bottom greater than its lattice constant away from the part of second open bottom.When first conductivity type be the N type, when second conductivity type is the P type, first strained layer in the lattice constant of the part of contiguous first open bottom greater than its lattice constant away from the part of first open bottom, and second strained layer in the lattice constant of the part of contiguous second open bottom less than its lattice constant away from the part of second open bottom.In addition, the lattice constant of second strained layer for example is a distribution gradient.The semiconductor structure of this embodiment can also comprise the silicon layer that is disposed on first, second strained layer, and a metal silicide layer, and it is disposed on silicon layer and aforementioned first, second grid structure.
Semiconductor structure manufacture method of the present invention is as follows.One substrate at first is provided, has wherein formed first well region of first conductivity type and second well region of second conductivity type, form the first grid structure again on second well region, the part substrate that removes first grid structure both sides then is to form first opening.Then, provide first mist to carry out epitaxy technique, in first opening, form first strained layer that contains a silicon and an IV family element, wherein first mist comprises first siliceous gas and second gas that contains an IV family element, and the content of second gas in first mist increases in time.Afterwards, on first well region, form the metal oxide semiconductor transistor of second conductivity type.
In certain embodiments, aforementioned first conductivity type is the P type, and an IV family atoms of elements radius is greater than the atomic radius of silicon, so that first strained layer becomes the compressive strain layer.
In certain embodiments, aforementioned first conductivity type is the N type, and an IV family element is the carbon of atomic radius less than the silicon atom radius, so that first strained layer becomes tensile strained layer.
In one embodiment, above-mentioned first mist can also comprise first impurity gas, and it is the rete of first conductivity type that first strained layer be can be formed directly in.The formation method of the metal oxide semiconductor transistor on first well region for example is prior to forming the second grid structure on first well region, form the source/drain region of second conductivity type again in first well region of second grid structure both sides.At this moment, above-mentioned semiconductor structure manufacture method also can be included on first strained layer and form silicon layer, forms steps such as metal silicide layer again on this silicon layer, first grid structure, second grid structure and source/drain region.
In another embodiment, the formation method of aforementioned metal oxide semi conductor transistor can be as follows.At first on first well region, form the second grid structure, in first well region of second grid structure both sides, form second opening again, in first well region of second opening sidewalls and below, form one source/drain region then.At this moment, above-mentioned semiconductor structure manufacture method also can be included on first strained layer and form silicon layer, forms steps such as metal silicide layer again on this silicon layer, source/drain region, first grid structure and second grid structure.
In another embodiment, the formation method of aforementioned metal oxide semi conductor transistor can be as follows.At first on first well region, form the second grid structure, the part substrate that removes second grid structure both sides again is to form second opening, provide second mist to carry out epitaxy technique, in second opening, to form second strained layer that contains silicon and the 2nd IV family element again.Wherein, second mist comprises aforementioned first gas and the 3rd gas that contains the 2nd IV family element, and the content of the 3rd gas in second mist increases in time.When first conductivity type be the P type, when second conductivity type is the N type, an IV family atoms of elements radius is greater than the atomic radius of silicon, and the 2nd IV family element is the carbon of atomic radius less than the silicon atom radius; And when first conductivity type be the N type, when second conductivity type is the P type, an IV family element is the carbon of atomic radius less than the silicon atom radius, and the 2nd IV family atoms of elements radius is greater than the atomic radius of silicon.In addition, above-mentioned second mist can also comprise second impurity gas, makes second strained layer can directly form the rete of second conductivity type.In this embodiment, the manufacture method of aforesaid semiconductor structure can also be included on first, second strained layer and form silicon layer, forms the step of metal silicide layer again on this silicon layer and first and second grid structure.
The present invention is in the epitaxy technique of formation as the strained layer of the source/drain electrode of metal oxide semiconductor transistor, the non-silicon IV family's element source gas that order is fed and the ratio of silicon source gas increase in time, so that formed strained layer in the difference between the lattice constant of the lattice constant of the part of adjacent openings bottom and substrate less than it away from the difference between the lattice constant of the lattice constant of the part of open bottom and substrate, therefore difference is excessive between the lattice dimensions of having avoided existing strained layer because of the adjacent openings bottom and the lattice dimensions of substrate, and in the problem of the knot generation defective of strained layer and substrate.In addition, the present invention forms metal silicide layer again prior to forming silicon layer on the strained layer on silicon layer, so can avoid the non-silicon IV family element in the strained layer to enter metal silicide layer and reduce its quality.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A～1B is the making flow process profile of existing a kind of metal oxide semiconductor transistor;
Fig. 2 is the generalized section of the semiconductor structure of one embodiment of the invention;
Fig. 3 A～3C is the making flow process profile of metal oxide semiconductor transistor 202;
Fig. 4 is the generalized section of the semiconductor structure of another embodiment of the present invention;
Fig. 5 is the generalized section of the semiconductor structure of further embodiment of this invention.
The simple symbol explanation
100,200: substrate
206: isolation structure
102,212,218: grid structure
104,212b, 218b: gate dielectric layer
106,212a, 218a: grid
108,212c, 218c: clearance wall
110,214,220,231: opening
114,226: metal silicide layer
202,204,204 ', 204 ": metal oxide semiconductor transistor
101,208,210: well region
211,217,223: doped region
112,216,222: strained layer
219,225: source/drain electrode extension area
224a, 224b: silicon layer
227,229: source/drain region
228a, 228b: etch stop layer
Embodiment
In each following embodiment, identical member will give identical Reference numeral, and its manufacture method of will arranging in pairs or groups of the semiconductor structure among each embodiment comes the present invention is done explanation.
Fig. 2 is the generalized section of the semiconductor structure of one embodiment of the invention.This semiconductor structure comprises the metal oxide semiconductor transistor 202 of substrate 200, first conductivity type, the metal oxide semiconductor transistor 204 and the isolation structure 206 of second conductivity type.Have the well region 208 of first conductivity type and the well region 210 of second conductivity type in the substrate 200.Metal oxide semiconductor transistor 202 is disposed on the well region 210, the strained layer 216 that comprises the grid structure 212 and first conductivity type, wherein grid structure 212 comprises the grid 212a, the grid 212a that are disposed in the substrate 200 and the gate dielectric layer 212b between the substrate 200, and the clearance wall 212c on grid 212a and the gate dielectric layer 212b sidewall.Grid structure 212 is disposed on the well region 210, and has opening 214 in the well region 210 of its both sides.The material of grid 212a for example is polysilicon or metal, and the material of gate dielectric layer 212b for example is silica, silicon nitride or silicon oxynitride, and the material of clearance wall 212c then for example is a silicon nitride.
The strained layer 216 of first conductivity type is disposed in the opening 214 with the part as the source/drain region of metal oxide semiconductor transistor 202, this strained layer 216 in the difference between the lattice constant of the lattice constant of the part of adjacent openings 214 bottoms and substrate 200 less than it away from the difference between the lattice constant of the lattice constant of the part of opening 214 bottoms and substrate 200, and its lattice constant distribution gradient for example.When first conductivity type was the P type, strained layer 216 was the compressive strain layer, and it is in the lattice constant of the part of the adjacent openings 214 bottoms lattice constant more than or equal to substrate 200, and less than its lattice constant away from the part of opening 214 bottoms.When first conductivity type was the N type, strained layer 216 was a tensile strained layer, and it is in the lattice constant of the part of the adjacent openings 214 bottoms lattice constant smaller or equal to substrate 200, and greater than its lattice constant away from the part of opening 214 bottoms.In addition, metal oxide semiconductor transistor 202 also comprises the source/drain electrode extension area 219 of the doped region 217 and first conductivity type of first conductivity type.Doped region 217 be disposed at open region 214 belows and around, as another part of the source/drain region of metal oxide semiconductor transistor 202.Source/drain electrode extension area 219 is disposed in the well region 210 of clearance wall 212c below.
Metal oxide semiconductor transistor 204 is disposed on the well region 208.Isolation structure 206 is disposed in the substrate 200 to define the active area of element, and it for example is that shallow trench isolation is from (shallow trenchisolation, STI) component isolation structure of structure or other pattern.In the present embodiment, metal oxide semiconductor transistor 204 comprises the strained layer 222 of the grid structure 218 and second conductivity type.Grid structure 218 is disposed on the well region 208, and has opening 220 in the well region 208 of its both sides.Grid structure 218 comprises the grid 218a, the grid 218a that are disposed in the substrate 200 and the gate dielectric layer 218b between the substrate 200, and the clearance wall 218c on grid 218a and the gate dielectric layer 218b sidewall.The material of grid 218a for example is polysilicon or metal, and the material of gate dielectric layer 218b for example is silica, silicon nitride or silicon oxynitride, and the material of clearance wall 218c for example is a silicon nitride.
Strained layer 222 is disposed in the opening 220 with the part as the source/drain region of metal oxide semiconductor transistor 204.Similarly, strained layer 222 in the difference between the lattice constant of the lattice constant of the part of adjacent openings 220 bottoms and substrate 200 less than it away from the difference between the lattice constant of the lattice constant of the part of opening 220 bottoms and substrate 200, and lattice constant distribution gradient for example.But, the lattice constant variation tendency of strained layer 222 is opposite with strained layer 216.That is, when first conductivity type is that P type (promptly second conductivity type is the N type), strained layer 216 is during for the compressive strain layer, strained layer 222 is a tensile strained layer, it is in the lattice constant of the part of the adjacent openings 220 bottoms lattice constant smaller or equal to substrate 200, and greater than its lattice constant away from the part of opening 220 bottoms.When first conductivity type is that N type (promptly second conductivity type is the P type), strained layer 216 is during for tensile strained layer, strained layer 222 is the compressive strain layer, it is in the lattice constant of the part of the adjacent openings 220 bottoms lattice constant more than or equal to substrate 200, and less than its lattice constant away from the part of opening 220 bottoms.In addition, metal oxide semiconductor transistor 204 also comprises the source/drain electrode extension area 225 of the doped region 223 and second conductivity type of second conductivity type, wherein doped region 223 is disposed at open region 220 belows and sidewall, as another part of the source/drain region of metal oxide semiconductor transistor 204.Source/drain electrode extension area 225 is disposed in the well region 208 of clearance wall 218c below.
Special one carry be, in the present embodiment, when first conductivity type be the P type, when second conductivity type is the N type, the material of the strained layer 216 of tool compressive strain for example is the sige alloy of lattice constant greater than pure silicon, and the material of the strained layer 222 of tool tensile strain for example is the carborundum of lattice constant less than pure silicon.Otherwise, when first conductivity type be the N type, when second conductivity type is the P type, the material of strained layer 216 is a carborundum for example, and the material of strained layer 222 for example is a sige alloy.
In addition, since strained layer 216/222 in the difference between the lattice constant of the lattice constant of the part of adjacent openings 214/220 bottom and substrate 200 less than away from the difference between the lattice constant of the lattice constant of the part of opening 214/220 bottom and substrate 200, therefore the strained layer 216/222 of opening 214/220 bottom more can not produce defective because lattice dimensions difference is excessive with the knot of substrate 200, and then influences element efficiency.
In addition, semiconductor structure of the present invention can also dispose the silicon layer 224a and the 224b of corresponding conductivity type on strained layer 216 and 222, and disposes metal silicide layer 226 on silicon layer 224a, 224b and grid structure 212,218.The thickness of silicon layer 224a, 224b for example be between
Between.The material of metal silicide layer 226 for example is tungsten silicide, titanium silicide, cobalt silicide, molybdenum silicide, nickle silicide, palladium silicide or platinum silicide.Moreover, can also go up configuration contact hole etching stop layer 228a and 228b in substrate 200 surfaces.The material of contact hole etching stop layer 228a and 228b is as being silicon nitride.Contact hole etching stop layer 228a and 228b can also be as the stressor layers that metal oxide semiconductor transistor 202,204 is provided compression stress or tensile stress, with the usefulness of further raising metal oxide semiconductor transistor 202,204.
Below with an example of the making flow process of the semiconductor structure in the key diagram 2, because this semiconductor structure left and right sides two halves structural similarity, so the following technology that its left half of structure is described earlier.
Fig. 3 A～3C illustrates the making flow process profile of metal oxide semiconductor transistor 202.At first, please refer to Fig. 3 A, substrate 200 is provided, formed the well region (not illustrating) of first conductivity type, the well region 210 and the isolation structure 206 of second conductivity type in the substrate 200, wherein isolation structure 206 defines the active area of element.The formation method of the well region 210 of the well region of first conductivity type and second conductivity type for example is the ion implantation technology of respectively substrate 200 being carried out first conductivity type and second conductivity type.The formation method of isolation structure 206 for example is a fleet plough groove isolation structure technology.Then, form grid 212a and gate dielectric layer 212b on well region 210, its method for example is prior to forming grid dielectric materials layer and gate material layers in the substrate in regular turn, again with photoetching etching method patterning grid material layer and grid dielectric materials layer in regular turn.
Please continue the A with reference to Fig. 3, form the doped region 211 of first conductivity type in the well region 210 of grid 212a both sides, it for example is to be that mask carries out ion implantation technology with grid 212a, first conductivity type dopant is injected substrate 200 and forms.Then, on the sidewall of grid 212a and gate dielectric layer 212b, form clearance wall 212c again.Grid 212a, gate dielectric layer 212b and clearance wall 212c are collectively referred to as grid structure 212 herein.
Then, please refer to Fig. 3 B, the part substrate 200 that removes grid structure 212 both sides is to form opening 214, and this moment, doped region 211 had part to be removed, and formation source/drain electrode extension area 219.The formation method of opening 214 for example is prior to formation patterning photoresist layer (not illustrating) in the substrate 200, and this patterning photoresist layer exposes grid structure 212 and the predetermined zone that forms opening 214.Then, be that mask carries out etch process with grid structure 212 with patterning photoresist layer, to remove the substrate 200 of part.Above-mentioned etch process can be isotropic etching, anisotropic etching process or oblique (tilted) etch process.The degree of depth of opening 214 for example be between
Between, preferably between
Between.
Subsequently, please refer to Fig. 3 C, is that mask carries out ion implantation technology with grid structure 212, first conductivity type dopant is injected the substrate 200 of opening 214 belows and sidewall, to form doped region 217, it is the part as the source/drain region of metal oxide semiconductor transistor 202.Special one what carry is that above-mentioned ion implantation technology is carried out before also can changing into and forming opening 214, and then removes part substrate 200 forming opening 214 and doped region 217, but the degree of depth that the degree of depth of opening 214 must be injected less than ion.
Please continue C with reference to Fig. 3, provide first mist to carry out epitaxy technique, form strained layer 216 in opening 214, wherein first mist comprises first siliceous gas and second gas that contains an IV family element, and the content of second gas in first mist increases in time.Above-mentioned epitaxy technique is a selective epitaxial growth process for example, and first gas for example is silicomethane or two silicon ethane.In addition, first mist preferably also comprises first impurity gas, so that strained layer 216 directly forms the rete of first conductivity type, as another part of the source/drain region of metal oxide semiconductor transistor 202.When first conductivity type is the P type, for producing bigger lattice constant forming the strained layer 216 of tool compressive strain, a selected IV family element be atomic radius greater than silicon atom radius person, for example be germanium.When first conductivity type was the N type, for producing less lattice constant to form the strained layer 216 of tool tensile strain, a selected IV family element was the carbon of atomic radius less than the silicon atom radius.
In addition, the manufacture method of the manufacture method of metal oxide semiconductor transistor 204 and metal oxide semiconductor transistor 202 is roughly the same, difference is that metal oxide semiconductor transistor 202 is first conductivity type, and metal oxide semiconductor transistor 204 is second conductivity type, and to form strained layer 222 employed be to comprise first gas and second mist that contains the 3rd gas of the 2nd IV family element.Certainly, second mist also can also comprise second impurity gas, so that strained layer 222 directly forms the rete of second conductivity type, as the part of the source/drain region of metal oxide semiconductor transistor 204.For forming required compressive strain layer of PMOS and the required tensile strained layer of NMOS respectively, when first conductivity type be the P type, when second conductivity type is the N type, the one IV family atoms of elements radius is greater than the silicon atom radius, with lattice constant that must be bigger, and the 2nd IV family element is the carbon of atomic radius less than the silicon atom radius, to get less lattice constant.Otherwise, when first conductivity type be the N type, when second conductivity type is the P type, an IV family element is the carbon of atomic radius less than the silicon atom radius, and the 2nd IV family atoms of elements radius is greater than the silicon atom radius.
Special one carry be, when above-mentioned first conductivity type be the P type, when second conductivity type is the N type, second gas is germane for example, and the content of second gas in first mist for example is to increase to 40% by 0 in time in epitaxy technique, and first impurity gas for example is a diborane.The 3rd gas is methane or ethane for example, and the content of the 3rd gas in second mist for example is to increase to 20% by 0 in time in epitaxy technique, and second impurity gas for example is a hydrogen phosphide.
Otherwise, when above-mentioned first conductivity type be the N type, when second conductivity type is the P type, second gas is methane or ethane for example, and the content of second gas in first mist for example is to increase to 20% by 0 in time in epitaxy technique, and first impurity gas for example is a hydrogen phosphide.The 3rd gas is germane for example, and the content of the 3rd gas in second mist for example is to increase to 40% by 0 in time in epitaxy technique, and second impurity gas for example is a diborane.
What deserves to be mentioned is, above-mentioned metal oxide semiconductor transistor 202,204 is not limited to separately make, also the manufacturing process of above-mentioned metal oxide semiconductor transistor 202 and the manufacturing process of metal oxide semiconductor transistor 204 can be integrated, to simplify processing step.
Forming metal oxide semiconductor transistor 202 (or 204) afterwards, can also optionally go up and form silicon layer 224a (or 224b), as shown in Figure 2 in strained layer 216 (or 222).The formation method of silicon layer 224a (or 224b) for example is in epitaxy technique, in forming strained layer 216 (or 222) afterwards, stop supplies second (or 3rd) gas, and continue siliceous first gas and first (or second) impurity gas of supply, be formed up to desired thickness up to silicon layer 224a (or 224b).After forming silicon layer 224a and 224b, metal silicide layer 226 can also optionally be formed, as shown in Figure 2 on silicon layer 224a, 224b and grid structure 212,218.The formation method of metal silicide layer 226 for example is self-aligned metal silicate (self-align silicide, salicide) technology.After forming metal silicide layer 226, also contact hole etching stop layer 228 can be formed in substrate 200, as shown in Figure 2.The formation method of contact hole etching stop layer 228 for example is a chemical vapour deposition technique.
In above-mentioned CMOS structure, except can forming equally the first conductivity type metal oxide semiconductor transistor 202 and 204 collocation of the second conductivity type metal oxide semiconductor transistor of the inconsistent strained layer of lattice constant, also can be with of the second conductivity type metal oxide semiconductor transistor collocation of the first conductivity type metal oxide semiconductor transistor 202 with other structure.
Fig. 4 is the generalized section of the semiconductor structure of another embodiment of the present invention.In the present embodiment, be disposed on the well region 208 with the second conductivity type metal oxide semiconductor transistor 204 ' of the first conductivity type metal oxide semiconductor transistor, 202 collocation, source/the drain region 227 that comprises the aforesaid grid structure 218 and second conductivity type, wherein source/drain region 227 is disposed in the well region 208 of grid structure 218 both sides.Metal oxide semiconductor transistor 204 ' also comprises the source/drain electrode extension area 225 of second conductivity type, and it is disposed in the well region 208 of clearance wall 218c below.
Similarly, the semiconductor structure of present embodiment also can dispose silicon layer 224 on strained layer 216, and disposes metal silicide layer 226 on silicon layer 224, grid structure 212,218 and source/drain region 227.Wherein, the material of the thickness of silicon layer 224 and metal silicide layer 226 for example is aforementioned person.Moreover, can also be in metal silicide layer 226 tops configuration contact hole etching stop layer 228a and 228b, its material for example is a silicon nitride.
Formation method about metal oxide semiconductor transistor 202 is done description in previous embodiment, does explanation no longer in addition in this.In the present embodiment, the formation method of metal oxide semiconductor transistor 204 ' for example is prior to forming grid structure 218 on the well region 208, form the source/drain region 227 of second conductivity type again in the well region 208 of grid structure 218 both sides, its method for example is an ion implantation.
Fig. 5 is the generalized section of the semiconductor structure of further embodiment of this invention.In the present embodiment, the second conductivity type metal oxide semiconductor transistor 204 with 202 collocation of the first conductivity type metal oxide semiconductor transistor " also be disposed on the well region 208; comprise the source/drain region 229 of the aforesaid grid structure 218 and second conductivity type, wherein source/drain region 229 is disposed in the well region 208 of opening 231 belows and sidewall.Metal oxide semiconductor transistor 204 " also comprise the source/drain electrode extension area 225 of second conductivity type, it is disposed in the well region 208 of clearance wall 218c below.
Similarly, semiconductor structure of the present invention also can dispose silicon layer 224 on strained layer 216, and on silicon layer 224, grid structure 212,218 and source-drain electrode area 229, dispose metal silicide layer 226, wherein the material of the thickness of silicon layer 224 and metal silicide layer 226 for example is aforementioned person.Moreover, can also be in metal silicide layer 226 tops configuration contact hole etching stop layer 228a and 228b, wherein the thickness of contact hole etching stop layer 228b is enough to fill up opening 231 at least, with to metal oxide semiconductor transistor 204 " channel region enough stress is provided and improves its carrier mobility.The material of contact hole etching stop layer 228a and 228b for example is a silicon nitride.
Formation method about metal oxide semiconductor transistor 202 is done description in previous embodiment, does explanation no longer in addition in this.In the present embodiment, metal oxide semiconductor transistor 204 " the formation method for example be: prior to forming grid structure 218 on the well region 208, remove the part substrate 200 of grid structure 218 both sides again, to form opening 231.Then, form the source/drain region 229 of second conductivity type in the well region 208 of opening 231 belows and sidewall, its method for example is an ion implantation.
What deserves to be mentioned is, above-mentioned metal oxide semiconductor transistor 204 ' or 204 " be not limited to equally separate making with metal oxide semiconductor transistor 202; also can be with the manufacture method and the metal oxide semiconductor transistor 204 ' or 204 of metal oxide semiconductor transistor 202 " manufacture method integrate, to simplify processing step.
Special one carry be, in an embodiment more of the present invention, metal oxide semiconductor transistor 202 can also be had analog structure but metal oxide semiconductor transistor (not illustrating) collocation of different conductivity with another and metal oxide semiconductor transistor 202.The difference of the two is: have the inconsistent strained layer 216 of aforementioned lattice constant in the metal oxide semiconductor transistor 202, its lattice constant is distribution gradient for example; And the lattice constant of the strained layer in this metal oxide semiconductor transistor is a definite value.
In sum, the present invention is in the epitaxy technique of formation as the strained layer of the source/drain electrode of metal oxide semiconductor transistor, make extension increase in time with the content of the gas that contains non-silicon IV family element in the mist, so that formed strained layer in the difference between the lattice constant of the lattice constant of the part of adjacent openings bottom and substrate less than it away from the difference between the lattice constant of the lattice constant of the part of open bottom and substrate, and can avoid causing the exert an influence defective of element efficiency of knot between strained layer and the substrate because of lattice dimensions difference is excessive.
In addition, the present invention forms metal silicide layer again prior to forming silicon layer on the strained layer on silicon layer, can avoid aforementioned non-silicon IV family element to enter metal silicide layer and reduce its quality in self-aligned metal silicate technology.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with claims the person of being defined be as the criterion.
Claims (25)
1, a kind of semiconductor structure comprises:
Substrate wherein has first well region of first conductivity type and second well region of second conductivity type;
First metal oxide semiconductor transistor of first conductivity type is disposed on this second well region, and this first metal oxide semiconductor transistor comprises:
The first grid structure is disposed on this second well region, has first opening in this second well region of these first grid structure both sides; And
First strained layer of first conductivity type, be disposed in this first opening, this first strained layer in the difference between the lattice constant of the lattice constant of the part of contiguous this first open bottom and this substrate less than it away from the difference between the lattice constant of the lattice constant of the part of this first open bottom and this substrate; And
Second metal oxide semiconductor transistor of second conductivity type is disposed on this first well region.
2, semiconductor structure as claimed in claim 1, wherein the lattice constant distribution gradient of this first strained layer.
3, semiconductor structure as claimed in claim 1, wherein this first conductivity type is the P type, and this first strained layer in the lattice constant of the part of contiguous this first open bottom less than its lattice constant away from the part of this first open bottom.
4, semiconductor structure as claimed in claim 3, wherein the material of this first strained layer comprises sige alloy.
5, semiconductor structure as claimed in claim 1, wherein this first conductivity type is the N type, and this first strained layer in the lattice constant of the part of contiguous this first open bottom greater than its lattice constant away from the part of this first open bottom.
6, semiconductor structure as claimed in claim 5, wherein the material of this first strained layer comprises carborundum.
7, semiconductor structure as claimed in claim 1, wherein this second metal oxide semiconductor transistor comprises:
The second grid structure is disposed on this first well region; And
Source/the drain region of second conductivity type is disposed in this first well region of these second grid structure both sides.
8, semiconductor structure as claimed in claim 7 also comprises:
Silicon layer is disposed on this first strained layer; And
Metal silicide layer is disposed on this silicon layer, this source/drain region, this first grid structure and this second grid structure.
9, semiconductor structure as claimed in claim 1, wherein this second metal oxide semiconductor transistor comprises:
The second grid structure is disposed on this first well region; And
Source/the drain region of second conductivity type is disposed at the sidewall and the below of second opening in this first well regions of this second grid structure both sides.
10, semiconductor structure as claimed in claim 9 also comprises:
Silicon layer is disposed on this first strained layer; And
Metal silicide layer is disposed on this silicon layer, this source/drain region, this first grid structure and this second grid structure.
11, semiconductor structure as claimed in claim 1, wherein this second metal oxide semiconductor transistor comprises:
The second grid structure is disposed on this first well region; And
Second strained layer of second conductivity type is disposed in second opening in this first well regions of this second grid structure both sides.
12, semiconductor structure as claimed in claim 11, wherein
This second strained layer in the difference between the lattice constant of the lattice constant of the part of contiguous this second open bottom and this substrate less than it away from the difference between the lattice constant of the lattice constant of the part of this second open bottom and this substrate;
When this first conductivity type be the P type, when this second conductivity type is the N type, this first strained layer in the lattice constant of the part of contiguous this first open bottom less than its lattice constant away from the part of this first open bottom, and this second strained layer in the lattice constant of the part of contiguous this second open bottom greater than its lattice constant away from the part of this second open bottom; And
When this first conductivity type be the N type, when this second conductivity type is the P type, this first strained layer in the lattice constant of the part of contiguous this first open bottom greater than its lattice constant away from the part of this first open bottom, and this second strained layer in the lattice constant of the part of contiguous this second open bottom less than its lattice constant away from the part of this second open bottom.
13, semiconductor structure as claimed in claim 12, wherein the lattice constant distribution gradient of this second strained layer.
14, semiconductor structure as claimed in claim 11 also comprises:
Silicon layer is disposed on this first strained layer and this second strained layer.
Metal silicide layer is disposed on this silicon layer, this first grid structure and this second grid structure.
15, a kind of manufacture method of semiconductor structure comprises:
Substrate is provided, has wherein formed first well region of first conductivity type and second well region of second conductivity type;
On this second well region, form the first grid structure;
This substrate of part that removes these first grid structure both sides is to form first opening;
Provide first mist to carry out epitaxy technique, in this first opening, form first strained layer that contains a silicon and an IV family element, wherein this first mist comprises first siliceous gas and second gas that contains an IV family element, and the content of this second gas in this first mist increases in time; And
On this first well region, form the metal oxide semiconductor transistor of second conductivity type.
16, the manufacture method of semiconductor structure as claimed in claim 15, wherein this first conductivity type is the P type, and an IV family atoms of elements radius is greater than the atomic radius of silicon.
17, the manufacture method of semiconductor structure as claimed in claim 15, wherein this first conductivity type is the N type, and an IV family element is a carbon.
18, the manufacture method of semiconductor structure as claimed in claim 15, wherein this first mist also comprises first impurity gas, makes this first strained layer directly form the rete of first conductivity type.
19, the manufacture method of semiconductor structure as claimed in claim 18, wherein the formation method of this metal oxide semiconductor transistor comprises:
On this first well region, form the second grid structure; And
In this first well region of these second grid structure both sides, form the source/drain region of second conductivity type.
20, the manufacture method of semiconductor structure as claimed in claim 19 also comprises:
On this first strained layer, form silicon layer; And
On this silicon layer, this first grid structure, this second grid structure and this source/drain region, form metal silicide layer.
21, the manufacture method of semiconductor structure as claimed in claim 18, wherein the formation method of this metal oxide semiconductor transistor comprises:
On this first well region, form the second grid structure;
In this first well region of these second grid structure both sides, form second opening; And
Formation source/drain region in this first well region of this second opening sidewalls and below.
22, the manufacture method of semiconductor structure as claimed in claim 21 also comprises:
On this first strained layer, form silicon layer; And
On this silicon layer, this source/drain region, this first grid structure and this second grid structure, form metal silicide layer.
23, the manufacture method of semiconductor structure as claimed in claim 18, wherein the formation method of this metal oxide semiconductor transistor comprises:
On this first well region, form the second grid structure;
This substrate of part that removes these second grid structure both sides is to form second opening; And
Provide second mist to carry out epitaxy technique, in this second opening, form second strained layer that contains silicon and the 2nd IV family element, wherein this second mist comprises this first gas and the 3rd gas that contains the 2nd IV family element, and the content of the 3rd gas in this second mist increases in time
Wherein, when this first conductivity type be the P type, when this second conductivity type is the N type, an IV family atoms of elements radius is greater than the atomic radius of silicon, and the 2nd IV family element is a carbon; And when this first conductivity type be the N type, when this second conductivity type is the P type, an IV family element is a carbon, and the 2nd IV family atoms of elements radius is greater than the atomic radius of silicon.
24, the manufacture method of semiconductor structure as claimed in claim 23, wherein this second mist also comprises second impurity gas, makes this second strained layer directly form the rete of second conductivity type.
25, the manufacture method of semiconductor structure as claimed in claim 24 also comprises:
On this first strained layer and this second strained layer, form silicon layer; And
On this silicon layer, this first grid structure and this second grid structure, form metal silicide layer.
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| US8236658B2 (en) * | 2009-06-03 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming a transistor with a strained channel |
| CN104900662B (en) * | 2014-03-04 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN108022842B (en) * | 2016-11-03 | 2023-02-28 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN110391231B (en) | 2018-04-16 | 2020-09-22 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| US5977592A (en) * | 1997-01-31 | 1999-11-02 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure and capable of greatly reducing its occupied area |
| US20030122199A1 (en) * | 2001-12-18 | 2003-07-03 | Kabushiki Kaisha Toshiba | Semiconductor device and fabricating method for the same |
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| US5977592A (en) * | 1997-01-31 | 1999-11-02 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure and capable of greatly reducing its occupied area |
| US6914307B2 (en) * | 2000-11-21 | 2005-07-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US20030122199A1 (en) * | 2001-12-18 | 2003-07-03 | Kabushiki Kaisha Toshiba | Semiconductor device and fabricating method for the same |
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