CN1720480A

CN1720480A - Array base palte, liquid crystal indicator and driving method thereof with array base palte

Info

Publication number: CN1720480A
Application number: CNA2003801046106A
Authority: CN
Inventors: 金熙燮; 朴源祥; 金相日; 司空同轼; 梁英喆; 洪性奎; 金钟来
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2002-12-21
Filing date: 2003-12-17
Publication date: 2006-01-11
Anticipated expiration: 2023-12-17
Also published as: KR100907481B1; CN100409092C; KR20040055393A

Abstract

A kind of array base palte comprises gate line (GL), data line (DL), switching device (920), transmission electrode (940), reflecting electrode (950) and compensation wiring (928).Pixel region (PA) comprise first and second zones (A1, A2).Switching device (920) is connected to gate line (GL) and data line (DL).Transmission electrode (940) is connected to switching device (920).Transmission electrode (940) is formed in the first area (A1).Reflecting electrode (950) and transmission electrode (940) insulation.Reflecting electrode (950) is formed in the second area (A2) of contiguous first area (A1).Compensation wiring (928) is connected to switching device (920).Facing to reflecting electrode (950), insulation course is inserted between them in second area (A2) in compensation wiring (928).Therefore, the transmissivity of the reflectivity of reflecting electrode (950) and transmission electrode (940) improves simultaneously, the box gap that the while liquid crystal indicator is consistent.

Description

Array base palte, liquid crystal indicator and driving method thereof with array base palte

Technical field

The present invention relates to array base palte, have the liquid crystal indicator of this array base palte and be used to drive the method for this liquid crystal indicator, more particularly, relate to a kind of array base palte that is used to improve light service efficiency and throughput rate, have the liquid crystal indicator of this array base palte and drive the method for this liquid crystal indicator.

Background technology

Liquid crystal indicator comprises reflection-type liquid-crystal display device and transmissive liquid crystal display device.Reflection-type liquid-crystal display device uses exterior light (first light hereinafter referred to as) for display image.For display image, transmissive liquid crystal display device comprises the light source that is used to produce interior lights (second light hereinafter referred to as).Recently, developed transflective type liquid crystal display device.Transflective type liquid crystal display device has the advantage of transmission-type and reflection-type two aspects, such as high quality graphic, low-power consumption etc.

When exterior light was sufficient, transflective type liquid crystal display device was used first light (or exterior light), and when exterior light is inadequate, used second light that produces from light source.

Transflective type liquid crystal display device comprises array base palte, filter substrate and liquid crystal layer.Filter substrate is facing to array base palte.Liquid crystal indicator is inserted between filter substrate and the array base palte.

The array base palte of liquid crystal indicator comprises a plurality of unit picture elements that are arranged in matrix form.Each unit picture element comprises data line, gate line and thin film transistor (TFT).Gate line is vertical substantially with data line.Thin film transistor (TFT) is arranged in the zone that is limited by data line and gate line.Thin film transistor (TFT) is electrically connected to data line and gate line.Transmission electrode and reflecting electrode are electrically connected to thin film transistor (TFT).Transmission electrode is a transparent and electrically conductive.Reflecting electrode has high reflectance.Zone on the transmission electrode comprises reflector space and regional transmission.Reflecting electrode only is formed on the reflector space.

Insulation course is inserted between thin film transistor (TFT) and the transmission electrode, thereby only transmission electrode is electrically connected to the drain electrode of thin film transistor (TFT).Concrete, insulation course comprises contact hole.Transmission electrode is electrically connected by contact hole mutually with drain electrode.

Therefore, when data voltage and driving voltage put on data line and gate line respectively, thin film transistor (TFT) response data voltage and driving voltage and work, thus data voltage and driving voltage are applied to transmission electrode and reflecting electrode by thin film transistor (TFT).

Usually, in transflective type liquid crystal display device, the box gap of reflector space is different from the box gap of regional transmission.That is, the box gap of reflector space is that half of regional transmission box gap is to improve display quality.

Adjust the thickness of insulation course, thereby form different box gaps according to the zone.

Yet it is difficult adjusting the box gap, makes destroyed and throughput rate liquid crystal indicator of the consistance in box gap reduce.

Summary of the invention

The invention provides a kind of array base palte that is used to improve display quality and throughput rate.

The present invention also provides a kind of liquid crystal indicator with described array base palte.

The present invention also provides a kind of method that drives described liquid crystal indicator.

According to an aspect of described array base palte, this array base palte comprises gate line, data line, switching device, transmission electrode, reflecting electrode and compensation wiring.Thereby this data line and described gate line intersect and limit the pixel region that comprises first and second zones.This switching device is electrically connected to described gate line and described data line.This transmission electrode is electrically connected to described switching device.Described transmission electrode is formed in the described first area.This reflecting electrode and described transmission electrode electrical isolation.Described reflecting electrode is formed in the described second area of contiguous described first area.Described compensation wiring is electrically connected to described switching device.Described compensation is routed in and faces toward described reflecting electrode in the described second area, and insulation course is inserted between described compensation wiring and the described reflecting electrode.

According to described array base palte on the other hand, this array base palte comprises first grid polar curve, second grid line, data line, first switching device, second switch device, transmission electrode, reflecting electrode and compensation wiring.Second grid line and described first grid polar curve electrical isolation.Thereby data line and described first and second gate lines intersect and limit the pixel region that comprises first and second zones.First switching device is electrically connected to described first grid polar curve and described data line.The second switch device is electrically connected to described second grid line.The transmission electrode that is formed in the described first area is electrically connected to described second switch device.Reflecting electrode and described transmission electrode electrical isolation.Described reflecting electrode is formed in the described second area of contiguous described first area.The compensation wiring is electrically connected to described first switching device.Described compensation wiring is facing to described reflecting electrode and described transmission electrode, and insulation course is inserted between them.

According to an aspect of described liquid crystal indicator, liquid crystal indicator comprises first and second substrates and is inserted in liquid crystal layer between first and second substrates.First substrate comprises gate line, data line, switching device, transmission electrode, reflecting electrode and compensation wiring.Thereby this data line and described gate line intersect and limit the pixel region that comprises first and second zones.This switching device is electrically connected to described gate line and described data line.The transmission electrode that is formed in the described first area is electrically connected to described switching device.This reflecting electrode and described transmission electrode electrical isolation.Described reflecting electrode is formed in the described second area of contiguous described first area.Described compensation wiring is electrically connected to described switching device.Described compensation is routed in and faces toward described reflecting electrode in the described second area, and insulation course is inserted between described compensation wiring and the described reflecting electrode simultaneously.Second substrate comprises the public electrode facing to transmission electrode and reflecting electrode.Liquid crystal layer is inserted between first and second substrates.

According to described liquid crystal indicator on the other hand, liquid crystal indicator comprises first and second substrates and liquid crystal layer.First substrate comprises first grid polar curve, second grid line, data line, first switching device, second switch device, transmission electrode, reflecting electrode and compensation wiring.Second grid line and described first grid polar curve electrical isolation.Thereby data line and described first and second gate lines intersect and limit the pixel region that comprises first and second zones.First switching device is electrically connected to described first grid polar curve and described data line.The second switch device is electrically connected to described second grid line.The transmission electrode that is formed in the described first area is electrically connected to described second switch device.Reflecting electrode and described transmission electrode electrical isolation.Described reflecting electrode is formed in the described second area of contiguous described first area.The compensation wiring is electrically connected to described first switching device.Described compensation wiring faces toward described reflecting electrode and described transmission electrode, and insulation course is inserted between compensation wiring and the reflecting electrode and compensates between wiring and the transmission electrode simultaneously.Second substrate comprises the public electrode facing to transmission electrode and reflecting electrode.Liquid crystal layer is inserted between first and second substrates.

According to described liquid crystal indicator on the other hand, liquid crystal indicator comprises first and second substrates and liquid crystal layer.First substrate comprises first and second switching devices, transmission electrode and reflecting electrode.Described first switching device is electrically connected to data line and gate line.Described second switch device is electrically connected to described first switching device.Described transmission electrode and described reflecting electrode are electrically connected to described first and second switching devices or opposite respectively.Second substrate comprises the public electrode facing to described first and second electrodes.Liquid crystal layer is inserted between described first and second substrates.

According to described liquid crystal indicator on the other hand, liquid crystal indicator comprises first and second substrates and liquid crystal layer.First substrate comprises switching device, the transmission electrode that is electrically connected to described switching device that is electrically connected to data line and gate line, the reflecting electrode that is electrically connected to described switching device, reaches the metal line facing to described reflecting electrode, and insulation course is inserted between described metal line and the described reflecting electrode.Second substrate comprises the public electrode facing to described transmission electrode and described reflecting electrode.Liquid crystal layer is inserted between described first and second substrates.

According to described liquid crystal indicator on the other hand, liquid crystal indicator comprises first and second substrates and liquid crystal layer.First substrate comprises the pixel region that has switching device and be electrically connected to a plurality of pixel electrodes of described switching device.Second substrate comprises a plurality of public electrodes.Corresponding each the described pixel electrode of each described public electrode.Liquid crystal layer is inserted between described first and second substrates.

According to an aspect of the method for described driving liquid crystal indicator, grid voltage is applied to gate line.Respond described grid voltage, the data voltage that output provides from data line.Apply described data voltage to transmission electrode as transmission voltage.Apply the reflected voltage that produces from described data voltage to reflecting electrode.Described reflected voltage is lower than described data voltage.Then, apply reference voltage to public electrode facing to described reflecting electrode and described transmission electrode.

According to the method for described driving liquid crystal indicator on the other hand, apply primary grid voltage to first grid polar curve.Respond described primary grid voltage, first data voltage that output provides from data line.Apply the transmission voltage that produces from described first data voltage to transmission electrode.Described transmission voltage is higher than described first data voltage.Apply the reflected voltage that produces from described first data voltage to reflecting electrode.Described reflected voltage is lower than described first data voltage.Then, apply reference voltage to public electrode facing to described reflecting electrode and described transmission electrode.

Therefore, the reflectivity of reflecting electrode and the transmissivity of transmission electrode improve simultaneously, the box gap that the while liquid crystal indicator is consistent.

Description of drawings

In conjunction with the accompanying drawings with reference to following detailed, above-mentioned and other advantage of the present invention will become very obvious, in the accompanying drawing:

Fig. 1 is the synoptic diagram that the liquid crystal indicator of first exemplary embodiment according to the present invention is shown;

Fig. 2 is the cross-sectional view that the liquid crystal indicator of Fig. 1 is shown;

Fig. 3 is the arrangenent diagram of unit picture element that the liquid crystal indicator of Fig. 1 is shown;

Fig. 4 is the equivalent circuit diagram of the unit picture element of Fig. 3;

Fig. 5 illustrates according to the transmissivity of the voltage that puts on transmission electrode and reflecting electrode and the curve of reflection coefficient;

Fig. 6 is the cross-sectional view that the liquid crystal indicator of second exemplary embodiment according to the present invention is shown;

Fig. 7 is an arrangenent diagram, shows the unit picture element of the liquid crystal indicator of Fig. 6;

Fig. 8 is the equivalent circuit diagram of the unit picture element of Fig. 7;

Fig. 9 is a cross-sectional view, shows the liquid crystal indicator of the 3rd exemplary embodiment according to the present invention;

Figure 10 is a schematic plan view, shows the array base palte of Fig. 9;

Figure 11 is a schematic plan view, shows the filter substrate of Fig. 9;

Figure 12 is a cross-sectional view, and the liquid crystal indicator of the 4th exemplary embodiment according to the present invention is shown;

Figure 13 is a schematic plan view, shows the array base palte of Figure 12;

Figure 14 is the equivalent circuit diagram of the unit picture element of Figure 12;

Figure 15 is a planimetric map, shows the array base palte of the 5th exemplary embodiment according to the present invention;

Figure 16 is a cross-sectional view, and the liquid crystal indicator of the 6th exemplary embodiment according to the present invention is shown;

Figure 17 is an arrangenent diagram, shows the part of the array base palte of Figure 16;

Figure 18 is the equivalent circuit diagram of the unit picture element of Figure 17;

Figure 19 is an arrangenent diagram, shows the array base palte of the liquid crystal indicator of the 7th exemplary embodiment according to the present invention;

Figure 20 is an equivalent circuit diagram, shows the unit picture element of liquid crystal indicator;

Figure 21 is an arrangenent diagram, shows the array base palte of the liquid crystal indicator of the 8th exemplary embodiment according to the present invention;

Figure 22 is an equivalent circuit diagram, shows the unit picture element of the liquid crystal indicator of Figure 21; And

Figure 23 is the waveform (wave pattern) of Figure 22.

Embodiment

Describe the preferred embodiments of the present invention below with reference to accompanying drawings in detail.

＜embodiment 1 〉

Fig. 1 is a synoptic diagram, shows the liquid crystal indicator of first exemplary embodiment according to the present invention, and Fig. 2 is the cross-sectional view that shows the liquid crystal indicator of Fig. 1.

With reference to Fig. 1 and 2, the liquid crystal indicator 400 of first exemplary embodiment comprises array base palte 100, filter substrate 200 and liquid crystal layer 300 according to the present invention.Filter substrate 200 is facing to array base palte 100.Liquid crystal layer 300 is inserted between array base palte 100 and the filter substrate 200.

Array base palte 100 comprises a plurality of pixels.Pixel is formed on first substrate 110, makes pixel line up matrix form.Each pixel comprises data line DL and gate lines G L.Data line DL extends upward in first party, and gate lines G L is extending upward with the vertical substantially second party of first direction.Array base palte 100 also comprises the first film transistor 120 and second thin film transistor (TFT) 130.The first film transistor 120 is arranged in the zone that is limited by data line DL and gate lines G L.The first film transistor 120 is electrically connected with data line DL and gate lines G L.Second thin film transistor (TFT) 130 is electrically connected with the first film transistor 120 and gate lines G L.The first film transistor 120 is electrically connected to the transmission electrode 150 that the material by transparent and electrically conductive constitutes.Second thin film transistor (TFT) 130 is electrically connected to the have high reflectance reflecting electrode 160 of (reflectance).

Particularly, the first film transistor 120 comprises first source electrode 123, first grid electrode 121 and first drain electrode 125.First source electrode 123 is electrically connected with data line DL.First grid electrode 121 is electrically connected with gate lines G L.First drain electrode is electrically connected with transmission electrode 150.Second thin film transistor (TFT) 130 comprises second source electrode 133, second grid electrode 131 and second drain electrode 135.Second source electrode 133 is electrically connected with first drain electrode 125.Second grid electrode 131 is electrically connected with gate lines G L.Second drain electrode 135 is electrically connected with reflecting electrode 160.

Insulation course 140 is inserted between the first film transistor 120 and the transmission electrode 150.Insulation course 140 also is inserted between second thin film transistor (TFT) 130 and the reflecting electrode 160.

Because insulation course 140, transmission electrode 150 is electrically connected with first drain electrode 125, and reflecting electrode 160 is electrically connected with second drain electrode 135.Particularly, insulation course 140 comprises first and second contact holes 141 and 143.First and

second drain electrodes

125 and 135 expose by first and

second contact holes

141 and 143 respectively.Thus, transmission electrode 150 is electrically connected with first drain electrode 125 by first contact hole 141, and reflecting electrode 160 is electrically connected with second drain electrode 135 by second contact hole 143.

Transmission electrode 150 and reflecting electrode 160 are electrically connected mutually by second thin film transistor (TFT) 130.

The zone that forms transmission electrode 150 is corresponding to regional transmission, and the zone that forms reflecting electrode 160 is corresponding to reflector space.

Filter substrate 200 comprises color-filter layer 220 and public electrode 230.Color-filter layer 220 comprises red color filter, green color filter and blue color filter.Color-filter layer 220 is formed on second substrate 210.Public electrode 230 is formed on the color-filter layer 220.Public electrode 230 is made of the material of transparent and electrically conductive.Liquid crystal layer 300 is inserted between array base palte 100 and the filter substrate 200.

Like this, the first film transistor 120 is electrically connected to the first liquid crystal capacitor Clc1 that is limited by transmission electrode 150, liquid crystal layer 300 and public electrode 230.Second thin film transistor (TFT) 130 is electrically connected to the second liquid crystal capacitor Clc2 that is limited by reflecting electrode 160, liquid crystal layer 300 and public electrode 230.

Fig. 3 is an arrangenent diagram, shows the unit picture element of the liquid crystal indicator of Fig. 1, and Fig. 4 is the equivalent circuit diagram of the unit picture element of Fig. 3.

With reference to Fig. 3 and 4, unit picture element is included in the upwardly extending m bar of first party data line DLm, and with the vertical substantially upwardly extending n bar of the second party gate lines G Ln of first direction.The first film transistor 120 is formed in the zone that is limited by (m-1) and m bar data line DLm-1 and DLm and (n-1) and n bar gate lines G Ln-1 and GLn.

The first film transistor 120 comprises first source electrode 123 that is electrically connected with m bar data line DLm, the first grid electrode 121 that is electrically connected with n bar gate lines G Ln and first drain electrode 125 that is electrically connected with transmission electrode 150.Transmission electrode 150 is facing to the public electrode (not shown) of filter substrate, and liquid crystal layer is inserted between transmission electrode 150 and the public electrode, thereby forms the first liquid crystal capacitor Clc1.Transmission electrode 150 is gone back crossover (n-1) bar gate lines G Ln-1, the insulation course (not shown) is inserted between transmission electrode 150 and (n-1) bar gate lines G Ln-1, thereby forms the first reservoir capacitor Cst1 that is electrically connected to the first liquid crystal capacitor Clc1 in parallel.

Second thin film transistor (TFT) 130 also is formed in the zone that is limited by (m-1) and m bar data line DLm-1 and DLm and (n-1) and n bar gate lines G Ln-1 and GLn.

Second thin film transistor (TFT) 130 comprises second source electrode 133 that is electrically connected with first drain electrode 125, the second grid electrode 131 that is electrically connected with n bar gate lines G Ln and second drain electrode 135 that is electrically connected with reflecting electrode 160.Reflecting electrode 160 is facing to public electrode, and liquid crystal layer is inserted between reflecting electrode 160 and the public electrode simultaneously, forms the second liquid crystal capacitor Clc2 thus.Reflecting electrode 160 also with (n-1) bar gate lines G Ln-1 crossover, the insulation course (not shown) is inserted between reflecting electrode 160 and (n-1) bar gate lines G Ln-1, forms the second reservoir capacitor Cst2 that is electrically connected to the second liquid crystal capacitor Clc2 in parallel thus.

Fig. 5 illustrates according to the transmissivity of the voltage that acts on transmission and reflecting electrode and the curve of reflectivity.The X-axis of curve is corresponding to transmissivity and reflectivity (%), and the Y-axis correspondence acts on the voltage of transmission electrode and reflecting electrode.Solid line G1 is corresponding to transmissivity, and dotted line G2 is corresponding to reflectivity.

With reference to Fig. 5, in regional transmission, when the voltage of about 4.2V acted on transmission electrode, transmissivity was saturated to about 40% maximal value.In reflector space, when the voltage of about 2.6V acts on reflecting electrode, the maximal value of reflectivity corresponding about 38%.

As shown in Figure 5, differ from one another corresponding to the voltage of maximum reflectivity with corresponding to the voltage of maximum transmission rate.Therefore, different voltage is applied to transmission electrode and reflecting electrode to improve transmissivity and reflectivity.That is, approximately the voltage of 4.2V is applied to transmission electrode, and approximately the voltage of 2.6V is applied to reflecting electrode, thereby improves the light service efficiency.

Refer again to Fig. 3 and 4, response is applied to the drive signal of n bar gate lines G Ln, and the data voltage that is applied to m bar data line DLm is sent to first drain electrode 125 of the first film transistor 120.Because the interior resistance of the first film transistor 120, data voltage reduces, and this data voltage that has reduced is applied to first drain electrode 125.This data voltage (first data voltage hereinafter referred to as) that has reduced is applied to second source electrode 133 of transmission electrode 150 (it is electrically connected with first drain electrode) and second thin film transistor (TFT) 130.The response drive signal, first data voltage is sent to second drain electrode 135 from second source electrode 133.Yet because the interior resistance of second thin film transistor (TFT) 130, first data voltage reduces once more and becomes second data voltage.So second data voltage is applied to the reflecting electrode 160 that is electrically connected with second drain electrode 135.

Like this, even when a data voltage is applied to m bar data line DLm, different voltage is applied to transmission electrode 150 and reflecting electrode 160.In addition, the interior resistance of second thin film transistor (TFT) 130 can be adjusted, thereby optimizes second data voltage.As a result, it is maximum that transmissivity and reflectivity all reach, thereby improve the light service efficiency of liquid crystal indicator 400.

In the present embodiment, transmission electrode 150 and reflecting electrode 160 and (n-1) bar gate lines G Ln-1 crossover, thus form first and second reservior capacitor Cst1 and the Cst2.

Yet, can form the wires apart with transmission electrode 150 and reflecting electrode 160 crossovers, thereby form first and second reservior capacitor Cst1 and the Cst2.

＜embodiment 2 〉

Fig. 6 is a cross-sectional view, shows the liquid crystal indicator of second exemplary embodiment according to the present invention.

With reference to Fig. 6, the liquid crystal indicator 600 of second exemplary embodiment comprises array base palte 500, filter substrate 200 and liquid crystal layer 300 according to the present invention.Filter substrate 200 is facing to array base palte 500.Liquid crystal layer 300 is inserted between array base palte 500 and the filter substrate 200.

Array base palte 500 comprises a plurality of pixels.Pixel is formed on first substrate 510, makes these pixels be arranged in matrix shape.Each pixel comprises data line (not shown) and gate line (not shown).Data line extends upward in first party, and gate line is extending upward with the vertical substantially second party of first direction.Array base palte 500 also comprises thin film transistor (TFT) 520.Thin film transistor (TFT) 520 is arranged in the zone that is limited by data line and gate line.Thin film transistor (TFT) 520 is electrically connected with data line and gate line.Thin film transistor (TFT) 520 comprises the source electrode 523 that is electrically connected with data line, the gate electrode 521 that is electrically connected with gate line and the drain electrode 525 that all is electrically connected with transmission electrode 540 and reflecting electrode 550.

Insulation course 530 is inserted between thin film transistor (TFT) 520 and the transmission electrode 540, the feasible drain electrode 525 that 540 of transmission electrodes is electrically connected to thin film transistor (TFT) 520.Insulation course 530 comprises contact hole 531, thereby transmission electrode 540 is electrically connected with drain electrode 525 by contact hole 531.

Reflecting electrode 550 and transmission electrode 540 part crossovers.That is, the part of reflecting electrode 550 is formed on the transmission electrode 540.Like this, reflecting electrode 550 is electrically connected with transmission electrode 540.

Reflecting electrode 550 is facing to son wiring (sub wiring) 527.Son wiring 527 is outstanding from gate line, thereby son wiring 527 is formed on on one deck with gate electrode 521.

Filter substrate 200 comprises color-filter layer 220 and public electrode 230.Color-filter layer 220 comprises red color filter, green color filter and blue color filter.Public electrode 230 is formed on the color-filter layer 220.Public electrode 230 is transparent and electrically conductives.Liquid crystal layer 300 is inserted between array base palte 500 and the filter substrate 200.

Like this, transmission electrode 540, liquid crystal layer 300 and public electrode 230 limit the first liquid crystal capacitor Clc1, and reflecting electrode 550, liquid crystal layer 300 and public electrode 230 limit the second liquid crystal capacitor Clc2.The first and second liquid crystal capacitor Clc1 and Clc2 are electrically connected parallel with one anotherly.The first and second liquid crystal capacitor Clc1 and Clc2 are electrically connected with thin film transistor (TFT) 520.In addition, the second liquid crystal capacitor Clc2 is electrically connected in parallel with the 527 sub-capacitor Cs that form that connected up by reflecting electrode 550, insulation course 530 and son.

Fig. 7 is an arrangenent diagram, shows the unit picture element of the liquid crystal indicator of Fig. 6, and Fig. 8 is the equivalent circuit diagram of the unit picture element of Fig. 7.

With reference to Fig. 7 and 8, unit picture element be included in the upwardly extending m bar of first party data line DLm, with the vertical substantially upwardly extending n bar of the second party gate lines G Ln of first direction.

Thin film transistor (TFT) 520 is formed in the zone that is limited by (m-1) and m bar data line DLm-1 and DLm and (n-1) and n bar gate lines G Ln-1 and GLn.Thin film transistor (TFT) 520 comprises the source electrode 523 that is electrically connected with m bar data line DLm, the gate electrode 521 that is electrically connected with n bar gate lines G Ln and the drain electrode 525 that is electrically connected with transmission electrode 540 and reflecting electrode 550.

Transmission electrode 540 is facing to public electrode, and liquid crystal layer is inserted between the two, thereby forms the second liquid crystal capacitor Clc2.Reflecting electrode 550 crossover (n-1) bar gate lines G Ln-1, insulation course is inserted between the two simultaneously.Therefore, formed the second reservoir capacitor Cst2 that is electrically connected to the second liquid crystal capacitor Clc2 in parallel.In addition, reflecting electrode 550 crossover n bar gate lines G Ln, insulation course is inserted between the two simultaneously.Therefore, formed sub-capacitor (sub capacitor) Cs that is electrically connected in parallel with the second liquid crystal capacitor Clc2 and the second holding capacitor Cst2.

When thin film transistor (TFT) 520 response is applied to the drive signal of n bar gate lines G Ln and when working, the data voltage that is applied to m bar data line DLm is sent to drain electrode 525.Then, data voltage is applied to transmission electrode 540 and the reflecting electrode 550 that is electrically connected with drain electrode 525.Particularly, first data voltage is applied to transmission electrode 540, and second data voltage is applied to reflecting electrode 550.Second data voltage is lower than first data voltage.That is, because the sub-capacitor Cs that is electrically connected with reflecting electrode 550, first data voltage reduces, thereby forms second data voltage.Then, second data voltage is applied to reflecting electrode 550.

As above-mentioned, even when a data voltage is applied to m bar data line DLm, different voltage is applied to transmission electrode 540 and reflecting electrode 550.As a result, it is maximum that transmissivity and reflectivity all reach, thereby improved the light service efficiency of liquid crystal indicator 600.

In the present embodiment, reflecting electrode 550 and n bar gate lines G Ln crossover, thus form sub-capacitor Cs.Yet, wires apart can with reflecting electrode 550 crossovers, thereby form sub-capacitor Cs.

＜embodiment 3 〉

Fig. 9 is a cross-sectional view, shows the liquid crystal indicator of the 3rd exemplary embodiment according to the present invention.Figure 10 is a schematic plan view, shows the array base palte of Fig. 9, and Figure 11 shows the schematic plan view of the filter substrate of Fig. 9.Liquid crystal indicator is identical with embodiment 1, except filter substrate 700.Like this, the same or analogous element of describing among identical Reference numeral indication and the embodiment 1 of element will be used, and any further explanation will be omitted.

With reference to Fig. 9 to 11, according to the liquid crystal indicator of the 3rd exemplary embodiment of the present invention comprise array base palte 100, facing to the filter substrate 700 of array base palte 100 and be inserted in array base palte 100 and filter substrate 700 between liquid crystal layer 300.

Filter substrate 700 comprises color-filter layer 720 that is formed on second substrate 710 and the public electrode 730 that is formed on the color-filter layer 720.Color-filter layer 720 comprises red color filter, green color filter and blue color filter.Public electrode 730 is transparent and electrically conductives.

Shown in Fig. 9 and 11, public electrode 730 comprises first and second public electrodes zone Ea1 and Ea2.First and second

public electrodes

731 and 732 are respectively formed in first and second public electrodes zone Ea1 and the Ea2.The transmission electrode of first public electrode, 731 corresponding array base paltes.The reflecting electrode of second public electrode, 732 corresponding array base paltes.First and second

public electrodes

731 and 732 electrically insulated from one another.That is, insulating regions Ia is inserted between first and second public electrodes zone Ea1 and the Ea2.

First and second reference voltages (reference voltage) are applied to first and second

public electrodes

731 and 732 respectively.Second reference voltage is lower than first reference voltage.

Shown in Fig. 9 and 11, array base palte 100 comprises first and second thin film transistor (TFT)s 120 and 130, thereby applies different voltage to transmission electrode 150 and reflecting electrode 160.That is, first data voltage is applied to transmission electrode, and second data voltage that is lower than first data voltage is applied to reflecting electrode.In this case, since first and second thin film transistor (TFT)s 120 and 130 between such as differences such as stray capacitance, discharge rates, so the preferred reference voltage levvl of the preferred reference voltage levvl of reflector space and regional transmission is different.

Like this, when preferred reference voltage is adjusted when adapting to regional transmission, leakage current flows through reflector space.When preferred reference voltage is adjusted when adapting to reflector space, leakage current flows through regional transmission.That is, first data voltage of liquid crystal layer that is applied to regional transmission is different between (+) frame just and negative (-) frame (frame), and second data voltage of liquid crystal layer that is applied to reflector space is in that just (+) frame is different with negative (-) interframe.

This voltage differences causes the brightness difference between reflector space and the regional transmission.In addition, voltage differences causes the brightness difference between positive frame and the negative frame.Like this, the image flicker that liquid crystal indicator 400 shows, thereby display quality variation.

For addressing this problem, first reference voltage is applied to first public electrode 731 facing to transmission electrode 150, and second reference voltage that is lower than first reference voltage is applied to second public electrode 732 facing to reflecting electrode 160.Like this, prevented first and second data voltages difference between positive frame and negative frame in regional transmission and reflector space respectively.

Liquid crystal layer 300 is inserted between array base palte 100 and the filter substrate 700, thereby forms liquid crystal indicator 800.

In the present embodiment, because transmission electrode 150 and reflecting electrode 160 define a plurality of electrode zones in the pixel region.Yet,, just can on the public electrode of filter substrate, form a plurality of public electrodes zone corresponding to electrode zone as long as form a plurality of electrode zones in the pixel region.

＜embodiment 4 〉

Figure 12 is a cross-sectional view, shows the liquid crystal indicator of the 4th exemplary embodiment according to the present invention, and Figure 13 is a schematic plan view, shows the array base palte of Figure 12.

With reference to Figure 12 and 13, the liquid crystal indicator 1000 of the 4th exemplary embodiment comprises array base palte 900, filter substrate 200 and is inserted between the two liquid crystal display layer 300 according to the present invention.

Array base palte 900 comprises first substrate 910, gate lines G L, data line DL, thin film transistor (TFT) 920, transmission electrode 940 and reflecting electrode 950.

Gate lines G L extends on first direction D1, and data line DL with the vertical substantially second direction D2 of first direction D1 on extend.Yet gate lines G L and data line DL are electrically insulated from each other.Pixel region PA is limited by gate lines G L and data line DL.

The thin film transistor (TFT) 920 of pixel region PA comprises the gate electrode 921 that is electrically connected with gate lines G L, the source electrode that is electrically connected with data line DL 922 and the drain electrode 923 that is electrically connected with transmission electrode 940.

Protective seam 930 is inserted between transmission electrode 940 and the thin film transistor (TFT) 920.Protective seam 930 comprises first contact hole 931 of the drain electrode 923 that is used for exposed film transistor 920.

Transmission electrode 940 is formed on the protective seam 930, makes transmission electrode 940 be electrically connected with drain electrode 923 by first contact hole 931.

Pixel region PA comprises first and second regional A1 and the A2.Transmission electrode 940 is formed in the A1 of first area.Reflecting electrode 950 and transmission electrode 940 electrical isolations, and reflecting electrode 950 is formed in the second area A2.

The first son wiring 925 is formed among the A1 of first area, makes win son wiring 925 and transmission electrode 940 electrical isolations and the first son wiring 925 facing to transmission electrode 940.The second son wiring 926 is formed among the second area A2, makes the second son wiring 926 and reflecting electrode 950 electrical isolations and the second son wiring 926 facing to reflecting electrode 950.The first and second son wirings 925 and 926 with gate lines G L while composition.That is, the first and second son wirings 925 and 926 and gate lines G L form simultaneously.

Compensation wiring 928 forms on first substrate 910.Compensation wiring 928 is electrically connected with the drain electrode 923 of thin film transistor (TFT) 920.Compensation wiring 928 compensates wiring 928 and reflecting electrode 950 electrical isolations simultaneously facing to reflecting electrode 950.

In Figure 12 and 13, for example, compensation wiring 928 and data line DL while composition.Yet, compensation wiring 928 can with gate lines G L composition simultaneously.

Filter substrate 200 comprises second substrate 210, be formed on the color filter 220 on second substrate 210 and be formed on public electrode 230 on the color filter 220.Filter substrate 200 and array base palte 900 are assembled together, and make public electrode 230 facing to transmission electrode 940 and reflecting electrode 950.Then, liquid crystal material is injected between filter substrate 200 and the array base palte 900, thereby forms liquid crystal layer 300.Like this, finished liquid crystal indicator 1000.

Between the transmission electrode 940 of public electrode 230 and first area A1 first is basic identical apart from the second distance d2 between d1 and public electrode 230 and the reflecting electrode 950.That is, liquid crystal indicator 1000 has consistent box gap in the first and second regional A1 and A2.

Figure 14 is the equivalent circuit diagram of the unit picture element of Figure 12.

With reference to Figure 12 to 14, unit picture element comprises gate lines G L and data line DL.Thin film transistor (TFT) 920 is electrically connected with gate lines G L and data line DL.Thin film transistor (TFT) 920 comprises drain electrode 923 (it is electrically connected to the first liquid crystal capacitor Clct), the first sub-capacitor Cstt, compensation condenser Ccpr and the second sub-capacitor Cstr.Compensation condenser Ccpr in series is electrically connected with the second liquid crystal capacitor Clcr.The first liquid crystal capacitor Clct, the first sub-capacitor Cstt, compensation condenser Ccpr are electrically connected with the recombiner condenser (composite capacitor) and the second sub-capacitor Cstr of the second liquid crystal capacitor Clcr parallel with one anotherly.

The electric capacity that forms between the public electrode 230 of the corresponding filter substrate 200 of the first liquid crystal capacitor Clct and the transmission electrode 940 of array base palte 900.

The electric capacity that forms between first son wiring 925 of the corresponding array base palte 900 of the first sub-capacitor Clst and the transmission electrode 940.

The electric capacity that forms between second son wiring 926 of the corresponding array base palte 900 of the second sub-capacitor Cstr and the reflecting electrode 950.

The electric capacity that forms between corresponding reflecting electrode 950 of the second liquid crystal capacitor Clcr and the public electrode 230.

The electric capacity that compensation condenser Ccpr correspondence forms between reflecting electrode 950 and compensation wiring 928.The electric capacity of compensation condenser Ccpr increases with the crossover area of reflecting electrode 950 and compensation wiring 928 with being directly proportional.

When the grid voltage that is applied to gate lines G L is sent to the gate electrode 921 of thin film transistor (TFT) 920, thin film transistor (TFT) 920 conductings.Like this, the data voltage Vd that is applied to source electrode 922 from data line DL is sent to drain electrode 923.Then, data voltage Vd is applied to transmission electrode 940 and compensation wiring 928.

For example the reference voltage of 0V is applied to the public electrode 230 of filter substrate 200.

When data voltage Vd was applied to transmission electrode 940 by thin film transistor (TFT) 920, the first liquid crystal capacitor Clct charged according to data voltage Vd.Yet the second liquid crystal capacitor Clcr charges according to the bucking voltage Vr that is lower than data voltage Vd.That is, data voltage Vd is shared by the compensation condenser Ccpr and the second liquid crystal capacitor Clcr, makes bucking voltage obtain according to expression 1.

Expression formula 1

Vr＝Vd×Ccpr/(Ccpr+Clcr)。

Shown in expression formula 1, the compensation condenser Ccpr and the second liquid crystal capacitor Clcr sum are greater than compensation condenser Ccpr, thereby bucking voltage Vr is lower than data voltage Vd.Like this, the data voltage Vd (or first data voltage) that is applied to transmission electrode 940 is higher than the bucking voltage Vr (or second data voltage) that is applied to reflecting electrode 950.

＜embodiment 5 〉

Figure 15 is a planimetric map, shows the array base palte of the liquid crystal indicator of the 5th exemplary embodiment according to the present invention.

With reference to Figure 15, the array base palte 901 of the liquid crystal indicator of the 5th exemplary embodiment comprises first substrate 910, gate lines G L, data line DL, thin film transistor (TFT) 920, transmission electrode 940, reflecting electrode 950 and compensation wiring 928 according to the present invention.

Gate lines G L extends on first direction D1, data line DL with the vertical substantially second direction D2 of first direction D1 on extend.Gate lines G L and data line DL electrically insulated from one another.Pixel region is limited by gate lines G L and data line DL.Compensation wiring 928 is facing to the reflecting electrode 950 in the pixel region.

Thin film transistor (TFT) 920 comprises that the gate electrode 921 that is electrically connected with gate lines G L, the source electrode that is electrically connected with data line DL 922 reach and compensation wiring 928 drain electrodes that are electrically connected 923.

Pixel region comprises first and second regional A1 and the A2.Transmission electrode 940 is formed in the A1 of first area.Reflecting electrode 950 is formed in the second area A2, makes reflecting electrode 950 and transmission electrode 940 electrical isolations.Transmission electrode 940 is electrically connected with compensation wiring 928 by second contact hole 935.Like this, transmission electrode 940 is electrically connected with the drain electrode 923 of thin film transistor (TFT) 923 by compensation wiring 928.

＜embodiment 6 〉

Figure 16 is a cross-sectional view, shows the liquid crystal indicator of the 6th exemplary embodiment according to the present invention, and Figure 17 shows the arrangenent diagram of a part of the array base palte of Figure 16.

With reference to Figure 16 and 17, according to the present invention the liquid crystal indicator 1100 of the 6th exemplary embodiment comprise array base palte 903, filter substrate 200 and be inserted in array base palte 903 and filter substrate 200 between liquid crystal layer 300.

Array base palte 903 comprises first substrate 910, first grid polar curve GLn-1, second grid line GLn, data line DL, the first film transistor T 1, the second thin film transistor (TFT) T2, transmission electrode 940, reflecting electrode 950 and compensation wiring 928, and " n " is the natural number greater than 2 here.

Array base palte 903 comprises a plurality of gate lines.First grid polar curve GLn-1 correspondence (n-1) bar gate line, the corresponding n bar of second grid line GLn gate line.

The first and second gate lines G Ln-1 and GLn extend along first direction D1, make the first and second gate lines G Ln-1 and GLn be separated from each other.Data line DL edge and the vertical substantially second direction D2 extension of first direction D1.Data line DL and the first and second gate lines G Ln-1 and GLn electrical isolation.Pixel region PA is limited by the first and second gate lines G Ln-1 and GLn and data line DL.

The first film transistor T 1 comprises the first grid electrode 961 that is electrically connected with first grid polar curve GLn-1, the source electrode 962 that is electrically connected to ground voltage and the drain electrode 963 that is electrically connected with transmission electrode 940.Pixel region PA comprises first and second regional A1 and the A2.Transmission electrode 940 is formed in the A1 of first area.Compensation wiring 928 faces toward transmission electrode 940 in the A1 of first area.

The second thin film transistor (TFT) T2 comprises that the second grid electrode 921 that is electrically connected with second grid line GLn, second source electrode 922 that is electrically connected with data line DL reach and compensation wiring 928 second drain electrodes 923 that are electrically connected.Reflecting electrode 950 is formed in the second area A2, makes reflecting electrode and transmission electrode 940 electrical isolations.Compensation wiring 928 faces toward reflecting electrode 940 in second area A2.

Protective seam 930 applies and is formed with thereon on first substrate 910 of the first and second thin film transistor (TFT) T1 and T2.Protective seam 930 suitable organic insulators.With transmission electrode 940 and compensation wiring 928 electrical isolations, and protective seam 930 is also with reflecting electrode 950 and compensation wiring 928 electrical isolation in second area A2 in the A1 of first area for protective seam 930.

Protective seam 930 comprises the contact hole 931 of first drain electrode 963 that is used to expose the first film transistor T 1.Transmission electrode 940 is formed on the protective seam 930, makes transmission electrode 940 be electrically connected with first drain electrode 963 by contact hole 931.

The first son wiring 925 is formed in the A1 of first area, makes win son wiring 925 and transmission electrode 940 insulation.The first son wiring 925 is facing to transmission electrode 940.The second sub-wiring 926 is formed in the second area A2, makes the second son wiring 926 and reflecting electrode 950 insulate.The second son wiring 926 is facing to reflecting electrode 950.

Filter substrate 200 comprises second substrate 210, be formed on the color filter 220 on second substrate 210 and be formed on public electrode 230 on the color filter 220.

Between the transmission electrode 940 among public electrode 230 and the first area A1 first is basic identical apart from the second distance d2 between the reflecting electrode 950 in d1 and public electrode 230 and the second area A2.That is, liquid crystal indicator 1100 has consistent box gap in the first and second regional A1 and A2.

Figure 18 is the equivalent circuit diagram of the unit picture element of Figure 17.

With reference to Figure 17 and 18, unit picture element comprises the first and second gate lines G Ln-1 and GLn and data line DL.The first and second gate lines G Ln-1 and GLn are separated from each other.The first film transistor T 1 comprises the first grid electrode that is electrically connected with first grid polar curve GLn-1 and is electrically connected to first source electrode of ground voltage.The second thin film transistor (TFT) T2 comprises second grid electrode that is electrically connected with second grid line GLn and second source electrode that is electrically connected with data line DL.

First drain electrode of the first film transistor T 1 is electrically connected with the first liquid crystal capacitor Clct and the first sub-capacitor Cstt.The first liquid crystal capacitor Clct and the first sub-capacitor Cstt are electrically connected with being connected in parallel to each other.Second drain electrode of the second thin film transistor (TFT) T2 is electrically connected with the second compensation condenser Ccpr and the second sub-capacitor Cstr.The second compensation condenser Ccpr and the second liquid crystal capacitor Clcr in series are electrically connected.The recombiner condenser of the second compensation condenser Ccpr and the second liquid crystal capacitor Clcr is electrically connected in parallel with the second sub-capacitor Cstr.

The first compensation condenser Ccpt is electrically connected with the first and second thin film transistor (TFT) T1 and T2.That is, first drain electrode of the first film transistor T 1 is electrically connected with first terminal (terminal) of the first compensation condenser Ccpt, and second drain electrode of the second thin film transistor (TFT) T2 is electrically connected with second terminal of the first compensation condenser Ccpt.

The electric capacity that forms between the public electrode 230 of the corresponding filter substrate 200 of the first liquid crystal capacitor Clct and the transmission electrode 940 of array base palte 903.

The electric capacity that forms between corresponding first son wiring 925 of the first sub-capacitor Cstt and the transmission electrode 940.

The electric capacity that forms between corresponding second son wiring 926 of the second sub-capacitor Cstr and the reflecting electrode 950.

The electric capacity that forms between corresponding transmission electrode 940 of the first compensation condenser Ccpt and the compensation wiring 928.

The electric capacity that forms between corresponding reflecting electrode 950 of the second compensation condenser Ccpr and the compensation wiring 928.

When primary grid voltage was applied to first grid polar curve GLn-1, primary grid voltage was sent to the first grid electrode of the first film transistor T 1, thus 1 conducting of the first film transistor T.Then, the ground voltage that is applied to first source electrode of the first film transistor T 1 is exported by first drain electrode.Yet the second thin film transistor (TFT) T2 is in shutoff (turn off) state, makes the voltage of second drain electrode of the second thin film transistor (TFT) T2 be lower than the voltage of first drain electrode of the first film transistor T 1.That is, the voltage of second drain electrode is born.

Like this, when 1 conducting of the first film transistor T, the transmission voltage Vt (or first data voltage) that is applied to transmission electrode 940 is higher than the reflected voltage (or second data voltage) that is applied to reflecting electrode 950.

When second grid voltage was applied to second grid line GLn, second grid voltage was sent to the second grid electrode of the second thin film transistor (TFT) T2.Like this, the second thin film transistor (TFT) T2 is switched on.

Primary grid voltage is applied to first grid polar curve GLn-1, is applied to second grid line GLn up to second grid voltage, makes the first film transistor T 1 be turned off, and the second thin film transistor (TFT) T2 is switched on simultaneously.When the first film transistor T 1 was turned off, transmission electrode 140 became floating (floatingstate).

Then, be applied to the second drain electrode output of the data voltage Vd of second source electrode from data line DL, thereby reflected voltage Vr and transmission voltage Vt are owing to data voltage Vd is enhanced by the second thin film transistor (TFT) T2.Transmission voltage Vt is higher than reflected voltage Vr.

First, second and third capacitor C 1, C2 and C3 such as following expression formula 2 qualification.

Expression formula 2

C1＝Cstr+(Ccpr×Clcr)/(Ccpr+Clcr)

C2＝Ccpt

C3＝Clct+Cstt。

Then, when the second thin film transistor (TFT) T2 was switched on, the transmission electrode Vt such as the following expression formula 3 that are applied to transmission electrode 940 were represented.

Expression formula 3

Vt＝1/(C1+2C2)×(2-C3/C2)×(C1+C2)×Vd

Shown in expression formula 3, transmission voltage Vt is higher than data voltage Vd.

＜embodiment 7 〉

Figure 19 is an arrangenent diagram, shows the array base palte of the liquid crystal indicator of the 7th exemplary embodiment according to the present invention, and Figure 20 is equivalent circuit diagram, shows the unit picture element of this liquid crystal indicator.

Figure 19 and 20 disclosed liquid crystal indicators come work by some reverse drive (dot reversion driving) method.

With reference to Figure 19, array base palte 905 comprises the first and second gate lines G Ln-1 and GLn, data line DL, first, second and the 3rd thin film transistor (TFT) T1, T2 and T3, transmission electrode 940, reflecting electrode 950 and compensation wiring 928.

The first film transistor T 1 comprises the first grid electrode that is electrically connected with first grid polar curve GLn-1, first source electrode that is electrically connected to ground voltage GT and first drain electrode that is electrically connected with transmission electrode 140.Pixel region comprises first and second regional A1 and the A2.Transmission electrode 940 is formed in the A1 of first area.Compensation wiring 928 also is formed in the A1 of first area.Compensation wiring 928 and transmission electrode 940 insulation, and in the A1 of first area, compensate wiring 928 facing to transmission electrode 940.

The second thin film transistor (TFT) T2 comprises that the second grid electrode that is electrically connected with second grid line GLn, second source electrode that is electrically connected with data line DL reach and compensation wiring 928 second drain electrodes that are electrically connected.Reflecting electrode 940 is formed in the second area A2, makes reflecting electrode 950 and transmission electrode 940 electrical isolations.Compensation wiring 928 is also insulated with reflecting electrode 950, and compensation connects up 928 facing to reflecting electrode 950 in second area A2.

The 3rd thin film transistor (TFT) T3 comprises that the 3rd gate electrode that is electrically connected with first grid polar curve GLn-1, the 3rd source electrode that is electrically connected with data line DL reach and compensation wiring 928 the 3rd drain electrodes that are electrically connected.

With reference to Figure 20, first drain electrode of the first film transistor T 1 is electrically connected with the first liquid crystal capacitor Clct and the first sub-capacitor Cstt.The first liquid crystal capacitor Clct and the first sub-capacitor Cstt are electrically connected parallel with one anotherly.

Second drain electrode of the second thin film transistor (TFT) T2 is electrically connected with the second sub-capacitor Cstr and the second compensation condenser Ccpr.The second compensation condenser Ccpr in series is electrically connected with the second liquid crystal capacitor Clcr.The recombiner condenser of the second compensation condenser Ccpr and the second liquid crystal capacitor Clcr is electrically connected in parallel with the second sub-capacitor Cstr.

The first film transistor T 1 is electrically connected with the second thin film transistor (TFT) T2 by the first compensation liquid crystal capacitor Ccpt.That is, first drain electrode of the first film transistor T 1 is electrically connected with first terminal of the first compensation condenser Ccpt, and second drain electrode of the second thin film transistor (TFT) T2 is electrically connected with second terminal of the first compensation condenser Ccpt.

Second terminal of the first compensation condenser Ccpt also is electrically connected with the 3rd drain electrode of the 3rd thin film transistor (TFT) T3.

When primary grid voltage was applied to first grid polar curve GLn-1, primary grid voltage was sent to the first grid electrode of the first film transistor T 1, so the first and the 3rd thin film transistor (TFT) T1 and T3 are switched on.Then, the ground voltage that is applied to first source electrode of the first film transistor T 1 is exported by first drain electrode of the first film transistor T 1, and the first data voltage Vd1 that is applied to the 3rd source electrode of the 3rd thin film transistor (TFT) T3 exports by the 3rd drain electrode of the 3rd thin film transistor (TFT) T3, and wherein the first data voltage Vd1 is for negative.

Then, ground voltage is sent to first terminal of the first compensation condenser Ccpt, and the first data voltage Vd1 is sent to second terminal of the first compensation condenser Ccpt, makes the compensation condenser Ccpt charging of winning.

When second grid voltage was applied to second grid line GLn, second grid voltage was sent to the second grid electrode of the second thin film transistor (TFT) T2, thus the second thin film transistor (TFT) T2 conducting.Primary grid voltage is applied to first grid polar curve GLn-1, is applied to second grid line GLn up to second grid voltage.Like this, when the second thin film transistor (TFT) T2 was switched on, the first film transistor T 1 was turned off simultaneously.Therefore, transmission electrode 940 keeps floating.

When the second thin film transistor (TFT) T2 was switched on, the second data voltage Vd2 that is applied to second source electrode from data line DL was sent to second drain electrode, and wherein the second data voltage Vd2 is for just.

When the second thin film transistor (TFT) T2 was switched on, the second data voltage Vd2 was applied to second terminal of the first compensation condenser Ccpt, and the transmission voltage Vt that is higher than the second data voltage Vd2 is applied to first terminal of the first compensation condenser Ccpt.

The transmission voltage Vt such as the following expression formula 4 that are applied to transmission electrode 940 during the second thin film transistor (TFT) T2 conducting are represented.

Expression formula 4

Vt＝Vd2+1/(C2+C3)×(-C3×Vd2+C2×Vd1)，

Wherein C1, C2 and C3 express in expression formula 2.

Shown in expression formula 4, transmission voltage Vt is higher than the second data voltage Vd2.

＜embodiment 8 〉

Figure 21 is an arrangenent diagram, shows the array base palte of the liquid crystal indicator of the 8th exemplary embodiment according to the present invention.Figure 22 is an equivalent circuit diagram, shows the unit picture element of the liquid crystal indicator of Figure 21, and Figure 23 is the waveform of Figure 22.

The disclosed liquid crystal indicator of Figure 21 to 23 comes work by row reverse drive (column reversiondriving) method.

With reference to Figure 21, the array base palte 907 of the liquid crystal indicator of the 8th exemplary embodiment comprises first grid polar curve GLn-1, second grid line GLn, the first and second thin film transistor (TFT) T1 and T2, transmission electrode 940, reflecting electrode 950 and compensation wiring (compensating wiring) 928 according to the present invention.

The first film transistor T 1 comprises the first grid electrode that is electrically connected with first grid polar curve GLn-1, first source electrode that is electrically connected with data line DL and first drain electrode that is electrically connected with transmission electrode 140.

Pixel region comprises first and second regional A1 and the A2.Transmission electrode 940 is formed in the A1 of first area.Compensation wiring 928 is facing to transmission electrode 940 in the first area.Compensation wiring 928 and transmission electrode 940 electrical isolations.

The second thin film transistor (TFT) T2 comprises that the second grid electrode that is electrically connected with second grid line GLn, second source electrode that is electrically connected with data line DL reach and compensation wiring 928 second drain electrodes that are electrically connected.

Reflecting electrode 950 is formed in the second area A2, makes reflecting electrode 950 and transmission electrode 940 electrical isolations.The compensation wiring is also facing to reflecting electrode 950 in second area A2.

With reference to Figure 22, unit picture element comprises the first and second gate lines G Ln-1 and GLn and data line DL.The first film transistor T 1 comprises first grid electrode that is electrically connected with first grid polar curve GLn-1 and first source electrode that is electrically connected with data line DL.The second thin film transistor (TFT) T2 comprises second grid electrode that is electrically connected with second grid line GLn and second source electrode that is electrically connected with data line DL.

The first film transistor T 1 also comprises first drain electrode and the first sub-capacitor Cstt that is electrically connected with the first liquid crystal capacitor Clct.The first liquid crystal capacitor Clct and the first sub-capacitor Cstt are electrically connected parallel with one anotherly.

The second thin film transistor (TFT) T2 also comprises second drain electrode that is electrically connected with the second sub-capacitor Cstr and the second compensation condenser Ccpr.The second compensation condenser Ccpr in series is electrically connected with the second liquid crystal capacitor Clcr.The recombiner condenser of the second compensation condenser Ccpr and the second liquid crystal capacitor Clcr is electrically connected in parallel with the second sub-capacitor Cstr.The recombiner condenser of the first liquid crystal capacitor Clct and the first sub-capacitor Cstt is electrically connected with first terminal of the first compensation condenser Ccpt, and second drain electrode of the second thin film transistor (TFT) T2 is electrically connected with second terminal of the first compensation condenser Ccpt.

When primary grid voltage was applied to first grid polar curve GLn-1, primary grid voltage was sent to the first grid electrode of the first film transistor T 1, thereby the first film transistor T 1 is switched on.Like this, the first data voltage Vd1 that is applied to first source electrode of the first film transistor T 1 is sent to first drain electrode of the first film transistor T 1.The first data voltage Vd1 quite is applied to the transmission voltage Vt of transmission electrode 940.

The second thin film transistor (TFT) T2 is in off state, thereby second drain electrode of the second thin film transistor (TFT) T2 remains below the voltage status of first drain electrode of the first film transistor T 1.That is, the voltage of second drain electrode is for negative.

Like this, the reflected voltage Vr (or second data voltage) that is applied to reflecting electrode 950 is lower than transmission voltage Vt (or first data voltage).

When second grid voltage was applied to second grid line GLn, second grid voltage was sent to the second grid electrode of the second thin film transistor (TFT) T2, thus the second thin film transistor (TFT) T2 conducting.

Primary grid voltage is applied to first grid polar curve GLn-1, is applied to second grid line GLn up to second grid voltage, make the second thin film transistor (TFT) T2 be switched on, and the first film transistor T 1 is turned off simultaneously.Like this, when the first film transistor T 1 was turned off, transmission electrode 940 became floating.

When the second thin film transistor (TFT) T2 was switched on, the second data voltage Vd2 that is applied to second source electrode from data line DL was sent to second drain electrode.

The first and second data voltage Vd1 and Vd2 are for just, and the first data voltage Vd1 is lower than the second data voltage Vd2.

Because the second data voltage Vd2, reflected voltage Vr and transmission voltage Vt are enhanced and are higher than the second data voltage Vd2.Transmission voltage Vt is higher than reflected voltage Vr.

Expression formula 5

Vt＝1/(C1+C2)×[(2-C3/C2)×(C1+C2)×Vd2+(C1+C2)×Vd1]，

Wherein C1, C2 and C3 represent in expression formula 2.

Shown in expression formula 5, transmission voltage Vt is higher than the second data voltage Vd2.

Industrial applicibility

According to the present invention, first voltage is applied to the transmission electrode that forms in the first area of pixel region, and second voltage that is lower than first voltage is applied to the reflecting electrode that forms in the second area of pixel region.

Like this, the reflectivity of reflecting electrode and the transmissivity of transmission electrode improve simultaneously, the box gap that the while liquid crystal indicator is consistent.

In addition, do not need extra technology, thereby throughput rate is improved.

Although described exemplary embodiment of the present invention, but be appreciated that the present invention should not be limited to these exemplary embodiments, within the spirit and scope of the present invention that claims limited, those of ordinary skill in the art can make various variations and change.

Claims

1. array base palte comprises:

Gate line;

Data line, thus it intersects with described gate line and limits the pixel region comprise first and second zones;

Switching device, it is electrically connected to described gate line and described data line;

Transmission electrode, it is electrically connected to described switching device, and described transmission electrode is formed in the described first area;

Reflecting electrode, itself and described transmission electrode electrical isolation, described reflecting electrode are formed in the described second area of contiguous described first area; And

The compensation wiring, it is electrically connected to described switching device, and described compensation is routed in and faces toward described reflecting electrode in the described second area, and insulation course is inserted between described compensation wiring and the described reflecting electrode.

2. array base palte as claimed in claim 1, the suitable thin film transistor (TFT) of wherein said switching device, this thin film transistor (TFT) comprise the gate electrode that is electrically connected to described gate line, are electrically connected to the source electrode of described data line and are electrically connected to described transmission electrode and the drain electrode of described compensation wiring.

3. array base palte as claimed in claim 1, wherein said compensation wiring and described data line are formed by identical layer.

4. array base palte comprises:

First grid polar curve;

The second grid line, itself and described first grid polar curve electrical isolation;

Data line, thus it intersects with described first and second gate lines and limits the pixel region comprise first and second zones;

First switching device, it is electrically connected to described first grid polar curve and described data line;

The second switch device, it is electrically connected to described second grid line;

Transmission electrode, it is electrically connected to described second switch device, and described transmission electrode is formed in the described first area;

Compensation wiring, it is electrically connected to described first switching device, and described compensation wiring is facing to described reflecting electrode and described transmission electrode, and insulation course is inserted between described compensation wiring and the described reflecting electrode and between described compensation wiring and the described transmission electrode.

5. array base palte as claimed in claim 4, the suitable the first film transistor of wherein said first switching device, this first film transistor comprise the gate electrode that is electrically connected to described second grid line, be electrically connected to the source electrode of described data line and be electrically connected to the drain electrode of described compensation wiring.

6. array base palte as claimed in claim 4, suitable second thin film transistor (TFT) of wherein said second switch device, this second thin film transistor (TFT) comprise the gate electrode that is electrically connected to described first grid polar curve, be electrically connected to the source electrode of ground voltage and be electrically connected to the drain electrode of described transmission electrode.

7. array base palte as claimed in claim 6, also comprise the 3rd thin film transistor (TFT), the 3rd thin film transistor (TFT) comprises the gate electrode that is electrically connected to described first grid polar curve, be electrically connected to the source electrode of described data line and be electrically connected to the drain electrode of described compensation wiring.

8. array base palte as claimed in claim 4, suitable second thin film transistor (TFT) of wherein said second switch device, this second thin film transistor (TFT) comprise the gate electrode that is electrically connected to described first grid polar curve, are electrically connected to the source electrode of described data line and are electrically connected to described transmission electrode and the drain electrode of described compensation wiring.

9. array base palte as claimed in claim 4 also comprises circuit, and this circuit makes described first grid polar curve keep first drive signal to receive second drive signal up to described second grid line.

10. array base palte as claimed in claim 4, wherein said compensation wiring and described data line are formed by identical layer.

11. a liquid crystal indicator comprises:

I) first substrate comprises:

Gate line;

The compensation wiring, it is electrically connected to described switching device, and described compensation is routed in and faces toward described reflecting electrode in the described second area, and insulation course is inserted between described compensation wiring and the described reflecting electrode;

Ii) second substrate, it comprises the public electrode facing to described transmission electrode and described reflecting electrode; And

Iii) liquid crystal layer, it is inserted between described first and second substrates.

12. a liquid crystal indicator comprises:

I) first substrate comprises:

First grid polar curve;

Compensation wiring, it is electrically connected to described first switching device, and described compensation wiring is facing to described reflecting electrode and described transmission electrode, and insulation course is inserted between described compensation wiring and the described reflecting electrode and between described compensation wiring and the described transmission electrode;

13. a liquid crystal indicator comprises:

First substrate, it comprises first and second switching devices, transmission electrode and reflecting electrode, described first switching device is electrically connected to data line and gate line, described second switch device is electrically connected to described first switching device, and described transmission electrode and described reflecting electrode are electrically connected to described first and second switching devices or opposite respectively;

Second substrate, it comprises the public electrode facing to described first and second electrodes; And

Liquid crystal layer, it is inserted between described first and second substrates.

14. liquid crystal indicator as claim 13, suitable first nmos pass transistor of wherein said first switching device, this transistor comprises first electrode that is electrically connected to described data line, be electrically connected to second electrode of described gate line and be electrically connected to the third electrode of described transmission electrode, and

Suitable second nmos pass transistor of described second switch device, this transistor comprise the 4th electrode that is electrically connected to described third electrode, be electrically connected to the 5th electrode of described gate line and be electrically connected to the 6th electrode of described reflecting electrode.

15. as the liquid crystal indicator of claim 13, first voltage that wherein is applied to described reflecting electrode is lower than second voltage that is applied to described transmission electrode.

16. a liquid crystal indicator comprises:

First substrate, it comprises switching device, the transmission electrode that is electrically connected to described switching device that is electrically connected to data line and gate line, the reflecting electrode that is electrically connected to described switching device, reaches the metal line facing to described reflecting electrode, and insulation course is inserted between described metal line and the described reflecting electrode;

Second substrate, it comprises the public electrode facing to described transmission electrode and described reflecting electrode; And

17. as the liquid crystal indicator of claim 16, thereby the outstanding described metal line that forms facing to described reflecting electrode of wherein said gate line.

18. a liquid crystal indicator comprises:

First substrate, it comprises the pixel region that has switching device and be electrically connected to a plurality of pixel electrodes of described switching device;

Second substrate, it comprises a plurality of public electrodes, corresponding each the described pixel electrode of each described public electrode; And

19. as the liquid crystal indicator of claim 18, wherein said pixel electrode comprises:

Transmission electrode, its feasible this transmission electrode of first light transmission that provides from the rear side of described first substrate; And

Reflecting electrode, second light that provides from the front side of described second substrate is provided for it.

20. as the liquid crystal indicator of claim 19, wherein said public electrode comprises:

First public electrode, it is facing to described transmission electrode; And

Second public electrode, itself and the described first public electrode electrical isolation, described second public electrode is facing to described reflecting electrode.

21. as the liquid crystal indicator of claim 20, wherein first voltage is applied to described first public electrode, and second voltage that is lower than described first voltage is applied to described second public electrode.

22. a method that drives liquid crystal indicator comprises:

Apply grid voltage to gate line;

Respond described grid voltage, the data voltage that output provides from data line;

Apply described data voltage to transmission electrode as transmission voltage;

Apply the reflected voltage that produces from described data voltage to reflecting electrode, described reflected voltage is lower than described data voltage; And

Apply reference voltage to public electrode facing to described reflecting electrode and described transmission electrode.

23. a method that drives liquid crystal indicator comprises:

Apply primary grid voltage to first grid polar curve;

Respond described primary grid voltage, first data voltage that output provides from data line;

Apply the transmission voltage that produces from described first data voltage to transmission electrode, described transmission voltage is higher than described first data voltage;

Apply the reflected voltage that produces from described first data voltage to reflecting electrode, described reflected voltage is lower than described first data voltage; And

24. as the method for claim 23, applying described first voltage before the described first grid polar curve, also comprising:

Apply second grid voltage to the second grid line;

Respond described second grid voltage output ground voltage;

Apply described ground voltage to described transmission electrode; And

Apply the voltage that is lower than described ground voltage and arrive described reflecting electrode.

25. as the method for claim 24, wherein said second grid line keeps second driving voltage, is applied to described second grid line up to described first driving voltage.

26. as the method for claim 23, applying described first voltage before the described first grid polar curve, also comprising:

Apply second grid voltage to the second grid line;

Respond described second grid voltage and export ground voltage;

Respond described second grid voltage and second data voltage that provides from described data line is provided;

Apply described ground voltage to described transmission electrode; And

Apply described second data voltage to described reflecting electrode.

27. as the method for claim 26, the phase place of wherein said second data voltage is opposite with the phase place of described first data voltage.

28. the method as claim 23 also comprises:

Apply second grid voltage to described second grid line;

Apply described second data voltage to described transmission electrode; And

Applying primary grid voltage before the first grid polar curve, apply the reduction that reduces from described second data voltage data voltage to described reflecting electrode.

29. as the method for claim 28, wherein said second data voltage has identical phase place with described first data voltage.