CN1719732A - Time pulse return apparatus of low voltage differential signal and method thereof - Google Patents
Time pulse return apparatus of low voltage differential signal and method thereof Download PDFInfo
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Abstract
This invention relates to a time-pulse data following up device and a method, which receives outside reference signals and data signals, the varying, trace of data signals forms an eye pattern. The device includes a phase-lock circuit, a bilateral tracing circuit and an eye pattern central position signal generation circuit, among which, the phase-lock circuit is used to generate multiple phase-lock circuit output signals, the bilateral tracing circuit is used for receiving at least part of multiple phase-lock circuit output signals to generate position signals of left boundary and right boundary of the eye pattern. The eye pattern control position signal generating circuit outputs an eye pattern central position signal corresponding to the central position based on the signal and generates different sampling signals of multiple phases of the data signal.
Description
(1) technical field
Relevant a kind of Low Voltage Differential Signal (the low voltage differential signal of the present invention, LVDS) time pulse return apparatus and method thereof especially utilize phase-lead to fall behind the design as the time pulse return apparatus of Low Voltage Differential Signal of detector and phase interpolator about one.
(2) background technology
After lcd screen was come out, (low voltage differentialsignal, LVDS) data signal had become most common form between main frame and display to adopt Low Voltage Differential Signal.Low Voltage Differential Signal (LVDS) is that with the difference of traditional single-ended signal it has characteristics such as low-voltage and power saving.But, caused the noise of data-signal to increase and the synchronous difficulty of data-signal along with the high speed of data-signal transmits.In order to address these problems, there are many kinds of frameworks to be suggested.The framework that reads that had for example before had is just supposed signal when transmission when design, the eye pattern distribution scenario that presents is symmetrical.Though but the circuit that designs under this hypothesis is simple, can't avoid passage different with environmental impact in practical application, for example influence that causes of the material difference of used transmission line.And for example another kind of framework has used so-called oversampling mode for the accuracy that improves data-signal.This mode is that a stroke count number of it is believed that has been read to make a decision several times again, but if when making the high-speed transfer of data, the speed that means reading of data must be than fast several times again of transfer of data, need circuit more at a high speed so on the one hand, not only power consumption, and bring the electromagnetic interference (EMI) effect, the correctness of data has reduced again when high-speed data reads on the other hand.
(3) summary of the invention
In view of this, the purpose of this invention is to provide a kind of time pulse return apparatus and method thereof of Low Voltage Differential Signal, can make data-signal through after the Channel Transmission, still can be with data-signal read the center of position as for eye pattern.The noise that is caused in the time of can improving transmission of data signals and nonsynchronous problem.Make the correctness that receives data-signal improve and the reduction error rate.
According to purpose of the present invention, a kind of time pulse return apparatus of Low Voltage Differential Signal is proposed, the clock signal return mechanism receives an external reference signal and a data-signal.Data-signal belongs to Low Voltage Differential Signal.The clock signal return mechanism comprises a phase-locked loop, a bilateral tracing circuit and an eye pattern center signal generating circuit.The phase-locked loop is in order to receive external reference signal, to export a plurality of phase-locked loops output signal.A plurality of phase-locked loops output signal frequency is identical with the frequency of external reference signal.And a plurality of phase-locked loops output signal has different phase places respectively.Bilateral tracing circuit receives to a plurality of phase-locked loops output signal of small part, and according to data-signal, output eye pattern left margin position signalling and eye pattern right margin position signalling.Eye pattern center signal generating circuit is in order to receiving to a plurality of phase-locked loops output signal of small part, and according to eye pattern left margin position signalling and eye pattern right margin position signalling one eye pattern center signal takes place.Eye pattern center signal generating circuit also according to eye pattern center signal with the different sampled signal of a plurality of phase places of data signals.
According to purpose of the present invention, a kind of method of clock pulse data answer of Low Voltage Differential Signal is proposed.Be used for a clock pulse signal return mechanism.The clock signal return mechanism is in order to receive an external reference signal and a data-signal.The clock signal return mechanism comprises a phase-locked loop, a data edges generator, a bilateral tracing circuit and an eye pattern center signal generating circuit.Bilateral tracing circuit comprises a reset control circuit, an eye pattern left margin position signal generator and an eye pattern right margin position signal generator.The phase-locked loop receives external reference signal to export a plurality of phase-locked loops output signal.The data edges generator receives data-signal to export a pulse wave signal.Eye pattern left margin position signal generator receives to small part a plurality of phase-locked loops output signal and pulse wave signal so that a left phase interpolation output signal and output one eye pattern left margin position signalling to take place.Eye pattern right margin position signal generator receives to small part a plurality of phase-locked loops output signal and pulse wave signal so that a right phase interpolation output signal and output one eye pattern right margin position signalling to take place.Eye pattern center signal generating circuit receives to a plurality of phase-locked loops of small part output signal, and according to eye pattern left margin position signalling and eye pattern right margin position signalling to export an eye pattern center signal.And the signal variation track of data-signal forms an eye pattern, and method of the present invention is with making the output of clock signal return mechanism correspond to the eye pattern center signal of a center of eye pattern.By the phase place that compares pulse wave signal and the phase place of left phase interpolation output signal, obtain eye pattern left margin position signalling earlier.By the phase place that compares pulse wave signal and the phase place of right phase interpolation output signal, obtain eye pattern right margin position signalling again.Then, find out the center of eye pattern by eye pattern left margin position signalling and eye pattern right margin position signalling.And according to the center of eye pattern eye pattern center signal takes place.At last according to eye pattern center signal, the different sampled signal of a plurality of phase places of data signals.Wherein, a little phase-locked loops output signal frequency is identical with the frequency of external reference signal, and a little phase-locked loops output signal has different phase places.Wherein, if a signal period of external reference signal corresponds to n data bit interval of data-signal, n is a positive integer, and then the phase difference of two adjacent a little phase-locked loops output signals is the 360/2n degree.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.
(4) description of drawings
Fig. 1 is the calcspar according to the time pulse return apparatus of a kind of Low Voltage Differential Signal of a preferred embodiment of the present invention.
Fig. 2 is the enforcement circuit diagram of phase-locked loop.
Fig. 3 is the enforcement circuit diagram of data edges generator and bilateral tracing circuit.
Fig. 4 is the enforcement circuit diagram of phase interpolator.
Fig. 5 is the output waveform figure of the first phase place interpolation device, 405 simulations.
Fig. 6 is the graph of a relation that signal CLK-L1, CLK-R1, CLK-L2, CLK-R2 follow the left and right border of eye pattern.
Fig. 7 is the enforcement circuit diagram of eye pattern center signal generating circuit.
Fig. 8 is former sampled signal and the comparison diagram of the sampled signal that takes place by the present invention.
Fig. 9 is the structure chart of time pulse return apparatus.
Figure 10 is the preferable enforcement circuit that differential wave is changeed the single-ended signal circuit.
(5) embodiment
In the present embodiment, (low voltage differential signal, clock pulse interval LVDS) has 7 data interval to Low Voltage Differential Signal, promptly is to have 7 data in the clock pulse interval of a Low Voltage Differential Signal (LVDS).The arteries and veins frequency range of the external reference signal OF that imports among the embodiment is 20-100MHz, and the data bit rates that transmits then is 140-700Mbps.Use a phase interpolator in the present invention.The effect of phase interpolator is that the signal of two inputs is done phase interpolation, and can do the adjustment that phase place increases or reduces by the signal of control signal after with phase interpolation of input.
Please refer to Fig. 1, it is the calcspar according to the time pulse return apparatus of a kind of Low Voltage Differential Signal of a preferred embodiment of the present invention.Time pulse return apparatus 200 receives external reference signal OF and data-signal D.Data-signal D belongs to Low Voltage Differential Signal (LVDS), has 7 data interval.Clock signal return mechanism 200 comprises a phase-locked loop 201 (PLL), a data edges generator 204 (dataedge generator), a bilateral tracing circuit 202 and an eye pattern center signal generating circuit 203 (eye center generator).Bilateral tracing circuit 202 comprises a reset control circuit (resetcontrol circuit) 205, one an eye pattern left margin position signal generator 206 and an eye pattern right margin position signal generator 207.Phase-locked loop 201 receives external reference signal OF to export a plurality of phase-locked loop output signal CLK.Data edges generator 204 receives data-signal D to export a pulse wave signal P.Eye pattern left margin position signal generator 206 receives to a plurality of phase-locked loop output signal CLK of small part and pulse wave signal P so that a left phase interpolation output signal S_PI_L (do not draw 1 in) and output one eye pattern left margin position signalling LW to take place.Eye pattern right margin position signal generator 207 receives to a plurality of phase-locked loop of small part output signal CLK and pulse wave signal P so that a right phase interpolation output signal S_PI_R (do not draw 1 in) and output one eye pattern right margin position signalling RW to take place.Eye pattern center signal generating circuit 203 receives to a plurality of phase-locked loop of small part output signal CLK, and according to eye pattern left margin position signalling LW and eye pattern right margin position signalling RW to export an eye pattern center signal CE (do not draw 1 in).And the signal variation track of data-signal D forms an eye pattern.The present invention makes 200 outputs of clock signal return mechanism correspond to the eye pattern center signal CE of a center of eye pattern.Earlier by phase place that compares pulse wave signal P and the phase place of left phase interpolation output signal S_PI_L, to obtain eye pattern left margin position signalling LW.Again by phase place that compares pulse wave signal P and the phase place of right phase interpolation output signal S_PI_R, to obtain eye pattern right margin position signalling RW.Then, find out the center of eye pattern again according to eye pattern left margin position signalling LW and eye pattern right margin position signalling RW.And according to the center of eye pattern eye pattern center signal CE takes place.At last according to eye pattern center signal CE, the different sampled signal of a plurality of phase places of data signals D.Wherein, the frequency of a plurality of phase-locked loop output signal CLK is identical with the frequency of external reference signal OF, and a plurality of phase-locked loop output signal CLK has different phase places respectively.Wherein, if the signal period of external reference signal OF corresponds to n the data bit interval of data-signal D, then the phase difference of two adjacent a little phase-locked loops 201 output signals is the 360/2n degree.N is 7 in the embodiment of the invention.Next, please refer to Fig. 9, it is the structure chart of time pulse return apparatus.To be divided into a kind of time pulse return apparatus 200 that three parts further specify preferred embodiment of the present invention respectively by figure.How to make data-signal D through after the Channel Transmission, still can be with the sampled signal of data-signal D center as for eye pattern.
First partly, please be earlier with reference to Fig. 2, and it is the enforcement circuit diagram of phase-locked loop.Wherein, phase-locked loop 201 comprises that a bias generator (Bias Generator) 301, one phase frequency comparator (PFD) 302, a charge-discharge circuit (charge pump) 303, one replica biased circuit (Replica Bias) 304, one voltage control oscillator (VCO) 305, one first group of differential wave change single-ended signal circuit (DSC) 306312.Phase frequency comparator 302 is in order to relatively one of this external reference signal OF and a plurality of phase-locked loop output signal CLK, so that a charge/discharge control signal to take place.Charge-discharge circuit 303 is to obtain one first output voltage according to the charge/discharge control signal.Replica biased circuit 304 duplicates first output voltage, to obtain one second output voltage.Voltage control oscillator 305 is exported a plurality of phase-locked loop output signal CLK according to first output voltage and second output voltage.Because the reference clock pulse that LVDS transmits can transmit 7 positions (bits) in one-period, so in these voltage control oscillator 305 frameworks, use 7 differential waves to change single-ended signal circuit 306-312.These 7 differential waves are changeed single-ended signal circuit 306-312 and are generally called first group of differential wave and change single-ended signal circuit 306-312 originally executing example.A plurality of phase-locked loop output signal CLK of voltage control oscillator 305 outputs will equally spacedly drop on the data interval of each LVDS, and by first group of differential wave commentaries on classics single-ended signal circuit 306-312 output of these 7 delay-level 14 phase places (included CLK_P0-CLK-P6, the CLK_N0-CLK_N6 of a plurality of phase-locked loop output signal CLK) can take place.In other words, the signal period of external reference signal OF corresponds to n data bit interval, and n is 7 in this example, and then the phase difference of two adjacent a plurality of phase-locked loop output signal CLK is the 360/2n degree.A plurality of phase-locked loop output signal CLK also through first group of differential wave change single-ended signal circuit 306-312 can obtain single-ended signal D0-D6 ,/D0-/D6 (a plurality of phase-locked loop output signal CLK also comprise single-ended signal D0-D6 ,/D0-/D6).Please refer to Figure 10, it is the preferable enforcement circuit that differential wave is changeed the single-ended signal circuit.Therefore, by voltage control oscillator 305 and first group of differential wave commentaries on classics single-ended signal circuit 306-312 a plurality of phase-locked loop output signal CLK take place.Make a plurality of phase-locked loop output signal CLK comprise differential wave CLK_P0-CLK_P6, CLK_N0-CLK_N6 and single-ended signal D0-D6 ,/D0-/D6.And single-ended signal D0-D6 ,/voltage level of D0-/D6 is the voltage level of general digital signal, and differential wave CLK_P0-CLK_P6, CLK_N0-CLK_N6 are the voltage level of Low Voltage Differential Signal.
Second partly, please refer to Fig. 3, and it is the enforcement circuit diagram of data edges generator and bilateral tracing circuit.Eye pattern left margin position signal generator 206 comprises that one first phase-lead falls behind detector (phaseearly/late detector-L) 402 and 1 first phase interpolator (phase interpolator-L) 405.Eye pattern right margin position signal generator 207 comprises that one second phase-lead falls behind detector (phase early/late detector-R) 404 and 1 second phase interpolator (phaseinterpolator-R) 406.The differential wave (to differential wave CLK_P0-CLK_P6, the CLK_N0-CLK_N6 of small part) and eye pattern left margin position signalling LW of first phase interpolator 405 in order to receive to small part is to export a left phase interpolation output signal S_PI_L.The differential wave (to differential wave CLK_P0-CLK_P6, the CLK_N0-CLK_N6 of small part) and eye pattern right margin position signalling RW of second phase interpolator 406 in order to receive to small part is to export a right phase interpolation output signal S_PI_R.In other words, the effect of first phase interpolator 405 and second phase interpolator 406 is that the signal of two inputs (to differential wave CLK_P0-CLK_P6, the CLK_N0-CLK_N6 of small part) is done phase interpolation, and can the signal behind the phase interpolation (left phase interpolation output signal S_PI_L, right phase interpolation output signal S_PI_R) be done the adjustment that phase place increases or reduces by the control signal (being eye pattern left margin position signalling LW and eye pattern right margin position signalling RW) of input.Further specify, please refer to Fig. 4, it is the enforcement circuit diagram of phase interpolator.Second phase interpolator 406 with Fig. 3, input CLK1 ,/CLK1 receives differential wave CLK_N6, the CLK_P6 among a plurality of phase-locked loop input signal CLK, and another input CLK2 ,/CLK2 receives differential wave CLK_P0, the CLK_N0 among a plurality of phase-locked loop input signal CLK.W[i in addition] ,/W[i], i=0-11, then representative can be controlled the switch of its electric current of flowing through.When the number of the switch conduction electric current of then flowing through more for a long time is big more, the speed that just can control signal rises reaches the purpose of control phase.With first phase interpolator 405 of Fig. 3, its W[i] ,/W[i] receive the output of 6-bit shiftregister-L as control.Please be simultaneously with reference to Fig. 5, it is the output waveform figure of first phase interpolator, 405 simulations.Curve＜0 〉,＜1,＜2,＜3 be respectively differential wave CLK_P0, CLK-P1, CLK_P2, the CLK_P3 among a plurality of phase-locked loop input signal CLK of output signal of voltage control oscillator 305, and curve A, B, C, D, E are the output signal of two groups of differential waves behind phase interpolation by differential wave CLK_N6, CLK_P6 among a plurality of phase-locked loop input signal CLK, CLK_P0, CLK_N0.And curve A: 6-bit shift register-L (offset buffer) output has 5 situations of 1 o'clock.Curve B: 6-bit shift register-L output has 4 situations of 1 o'clock.Curve C: 6-bit shiftregister-L output has 3 situations of 1 o'clock.Curve D: 6-bit shift register-L output has 2 situations of 1 o'clock.Curve E:6-bit shift register-L output has 1 situation of 1 o'clock.So in the middle of the differential wave CLK_P0-CLK_P1, can be divided into 6 intervals, also can be divided into 6 phase places.
First phase-lead falls behind detector 402 and comprises first bit shift register 407 (6-bit shiftregister-L).Second phase-lead falls behind detector 402 and comprises second bit shift register 408 (6-bitshift register-R).First phase-lead falls behind detector 402 and compares the phase place of pulse wave signal P and the phase place of left phase interpolation output signal S_PI_L, and second phase-lead falls behind detector 404 and compares the phase place of pulse wave signal P and the phase place of right phase interpolation output signal S_PI_R.Just first phase-lead falls behind detector 402 and second phase-lead backwardness detector 404 and is used for two phase of input signals of comparison, and its result after relatively is stored in first bit shift register 407 and second bit shift register 408 respectively.First bit shift register 407 and second bit shift register 408 determine that first phase interpolator 405, second phase interpolator 406 output phase next time will increase, minimizing or motionless.First phase-lead falls behind the left eye boundary Control signal CLK-L1 of detector 402 generations and the right eye boundary Control signal CLK-R1 of backward detector 404 generations of second phase-lead can make win bit shift register 407 and second bit shift register, 408 output eye pattern left margin position signalling LW and eye pattern right margin position signalling RW respectively.First phase interpolator 405 and second phase interpolator 406 receive eye pattern left margin position signalling LW and eye pattern right margin position signalling RW exporting left phase interpolation output signal S_PI_L and the right phase interpolation output signal S_PI_R that move at past eye pattern center, that is make the position on the left and right border of eye pattern contract toward in.Opposite, the signal first reset signal CLK-L2 that reset control circuit 205 takes place and the second reset signal CLK-R2 can make output that the phase-lead of winning falls behind detector 402 and second phase-lead backwardness detector 404 toward moving away from the eye pattern center, that is make the position on the left and right border of eye pattern expand outward.Utilize this mode that contracts toward in, opens outward, eye pattern opens minimum left and right border in the time of can obtaining environment change.Please refer to Fig. 6, it is the graph of a relation that signal CLK-L1, CLK-R1, CLK-L2, CLK-R2 follow the left and right border of eye pattern.
Further, the mode of seeking the eye pattern left boundary is, when data-signal D variation occurs in the scope on the eye pattern left side, the position that promptly is data-signal D variation is the right at left phase interpolation output signal S_PI_L, then first phase-lead falls behind detector 402 and can subtract 1 by the output that eye pattern left margin position signalling LW controls first bit shift register 407, make the phase place of left phase interpolation output signal S_PI_L increase, become new left phase interpolation output signal S_PI_L, that is to say the phase place of the phase lag left side phase interpolation output signal S_PI_L of pulse wave signal P, then first phase-lead falls behind detector 206 controls first phase interpolator 405, makes the phase place of new left phase interpolation output signal S_PI_L increase.
If the position that data-signal D changes is the left side of changeing single-ended signal circuit (DSC-L) 409 output signals at first phase interpolator 405 through first differential wave among Fig. 3, this moment, the eye pattern left side can enter locking-in state (this locking-in state is controlled by the output of the DFF-L1 among Fig. 3), made the phase invariant of left phase interpolation output signal S_PI_L.When the eye pattern left side enters locking-in state, must appear at the right of the left phase interpolation output signal S_PI-L of first phase interpolator, 405 outputs by next data-signal D, that is to say the phase place of the phase-lead left side phase interpolation output signal S_PI_L of pulse wave signal P, just can remove locking-in state.
Similarly, the mode of seeking border, eye pattern the right is that the position that data-signal D changes is the left side at right phase interpolation output signal S_PI_R.Then second phase-lead falls behind detector 404 and controls 408 outputs of second bit shift register by eye pattern right margin position signalling RW and can add 1, make the phase place of right phase interpolation output signal S_PI_R reduce, become new border, eye pattern the right, that is to say the phase place of the phase-lead left side phase interpolation output signal S_PI_R of pulse wave signal P, then second phase-lead falls behind detector 207 controls second phase interpolator 406, makes the phase place of new left phase interpolation output signal S_PI_R reduce.
If the position that data-signal D changes is the right of changeing single-ended signal circuit (DSC-L) 410 output signals at second phase interpolator 406 through second differential wave among Fig. 3, this moment, eye pattern the right can enter locking-in state (this locking-in state is controlled by the output of the DFF-R1 among Fig. 3), made the phase invariant of right phase interpolation output signal S_PI_R.When eye pattern the right enters locking-in state, must change the left side that appears at the right phase interpolation output signal S_PI_R of first phase interpolator, 405 outputs by next data-signal D, that is to say the phase place of the phase lag left side phase interpolation output signal S_PI_L of pulse wave signal P, just can remove locking-in state.
Yet, change the left side or the right of dropping on eye pattern fully as data-signal D, for example during the arteries and veins frequency shift of the external reference signal OF that receives of phase-locked loop 201 or the leading always clock pulse in position that changes of data-signal D, can cause phase interpolator 405 or 406 on one side can't aim at the border of eye pattern like this, because the input X1 of first bit shift register 407 and second bit shift register 408 and X2 do not have the signal input.For fear of this situation, can provide first bit shift register 407 and the other signal input source of second bit shift register 408 by counter in the reset control circuit 205 (4-BIT COUNTER).Counter is counted at 15 o'clock and can be sent a pulse wave signal via the AND406 among Fig. 3 as the first reset signal CLK-L2 and the second reset signal CLK-R2.The signal (CLK-L2, CLK-R2) that provides by counter, its effect is followed by data-signal D and is changed the effect difference that signal CLK signal takes place to go out as a plurality of phase-locked loops, the first reset signal CLK-L2 that counter (4-BIT COUNTER) provides and the second reset signal CLK-R2 are not subjected to the DFF-L1 among Fig. 3 and the influence of DFF-R1 locking-in state, can force input first bit shift register 407 and second bit shift register 408, the output of win phase interpolator 405, second phase interpolator 406 is moved toward the direction away from the eye pattern border.In other words, reset control circuit 205, be used to one fixing during after, replacement eye pattern left margin position signal generator 206 and eye pattern right margin position signal generator 207.
Third part please refer to Fig. 7, and it is the enforcement circuit diagram of eye pattern center signal generating circuit.Eye pattern center signal generating circuit 203 comprises a third phase position interpolater (center phaseinterpolator) 901 and one voltage control delay circuit (VCDL) 902.Third phase position interpolater 901 in order to foundation eye pattern left margin position signalling LW, eye pattern right margin position signalling RW with to differential wave CLK_P0-CLK-P6, the CLK_N0-CLK_N6 of small part, so that eye pattern center signal CE to take place.The different sampled signal of a plurality of phase places takes place according to eye pattern center signal CE in voltage control delay circuit 902.Further specify, interpolater 901 received eye pattern left margin position signalling LW and eye pattern right margin position signalling RW in third phase position pass through the data sampling signal that third phase position interpolater 901 is positioned at the eye pattern center, by 7 grades voltage control delay circuit 902 outputs, reach 7 data in each input clock pulse interval of sample again.Here because have 24 control signals, so the signal that third phase position interpolater 901 is done phase interpolation is the blank signal (for example CLK_P5, CLK_P0) among differential wave CLK_P0-CLK_P6, the CLK_N0-CLK_N6.And first phase interpolator 405 and second phase interpolator 406 are because of having only 12 control signals, so do the adjacent signals that the signal of phase interpolation is differential wave CLK_P0-CLK_P6, CLK_N0-CLK_N6 (for example CLK-P5, CLK_P6).Please refer to Fig. 8, it is former sampled signal and the comparison diagram of the sampled signal that takes place by the present invention.Through after the transmission, the position of data interval falls behind the interval corresponding position of clock signal by procedure simulation data-signal D, that is data-signal D changes always the left side at eye pattern.Original data sampling position is D1, be B1 through the sample position being moved behind the circuit of the present invention, the setting-up time (setup time) that can see the sample position B1 that makes new advances was longer as the setting-up time time of data sampling than the clock signal D1 that original simple lock loop takes place, thus can be more accurate read data.
The time pulse return apparatus that the above embodiment of the present invention disclosed, utilize the design of backward detector of phase-lead and phase interpolator as the time pulse return apparatus of Low Voltage Differential Signal, can solve data-signal through after the Channel Transmission, still can be with data-signal read the center of position as for eye pattern, the noise that is caused in the time of can improving transmission of data signals and nonsynchronous problem make the correctness that receives data-signal improve and the reduction error rate.
Though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (10)
1. the clock signal return mechanism of a Low Voltage Differential Signal, this clock signal return mechanism receives an external reference signal and a data-signal, and this data-signal belongs to this Low Voltage Differential Signal, and this clock signal return mechanism comprises:
One phase-locked loop, in order to receive this external reference signal, to export a plurality of phase-locked loops output signal, this phase-locked loop output signal frequency is identical with the frequency of this external reference signal, and this phase-locked loop output signal has different phase places respectively;
One bilateral tracing circuit receives to this phase-locked loop output signal of small part, and according to a pulse wave signal and this phase-locked loop output signal that this data-signal took place, to export an eye pattern left margin position signalling and an eye pattern right margin position signalling; And
One eye pattern center signal generating circuit, in order to receive to this phase-locked loop output signal of small part, one eye pattern center signal takes place according to this eye pattern left margin position signalling and this eye pattern right margin position signalling in this eye pattern center signal generating circuit, the different sampled signal of a plurality of phase places that this eye pattern center signal generating circuit also according to this eye pattern center signal this data-signal takes place.
2. device as claimed in claim 1 is characterized in that, this phase-locked loop comprises:
One phase frequency comparator is in order to relatively one of this external reference signal and this phase-locked loop output signal, so that a charge/discharge control signal to take place;
One charge-discharge circuit, according to this charge/discharge control signal to obtain one first output voltage; And
One replica biased circuit duplicates this first output voltage, to obtain one second output voltage;
One voltage control oscillator is exported this phase-locked loop output signal according to this first output voltage and this second output voltage.
3. device as claimed in claim 2, it is characterized in that, this voltage control oscillator also comprises one first group of differential wave commentaries on classics single-ended signal circuit that a plurality of differential waves commentaries on classics single-ended signal circuit of serial connection are constituted, when this phase-locked loop during in locking-in state, this first group of differential wave changeed the single-ended signal circuit and exported this phase-locked loop output signal, if the signal period of this external reference signal corresponds to n data bit interval, n is positive integer, and then the phase difference of two these adjacent phase-locked loop output signals is the 360/2n degree.
4. device as claimed in claim 3 is characterized in that, this bilateral tracing circuit comprises:
One data edges generator, in order to receive this data-signal, a pulse wave signal takes place according to the edge of this data-signal in this data edges generator;
One eye pattern left margin position signal generator receives to this phase-locked loop output signal and this pulse wave signal of small part, and to export this eye pattern left margin position signalling, this eye pattern left margin position signal generator comprises:
One first phase interpolator is in order to this phase-locked loop output signal and this eye pattern left margin position signalling that receives to small part, to export a left phase interpolation output signal; And
One first phase-lead falls behind detector, in order to receive this phase-locked and loop output signal that this pulse wave signal, this left side phase interpolation output signal to small part, to export this eye pattern left margin position signalling, this first phase interpolator is adjusted this left side phase interpolation output signal according to this eye pattern left margin position signalling;
One eye pattern right margin position signal generator receives to this phase-locked loop output signal and this pulse wave signal of small part, and to export this eye pattern right margin position signalling, this eye pattern right margin position signal generator comprises:
One second phase interpolator is in order to this phase-locked loop output signal and this eye pattern right margin position signalling that receives to small part, to export a right phase interpolation output signal; And one second phase-lead falls behind detector, in order to receive this pulse wave signal, to this phase-locked loop output signal and this right side phase interpolation output signal of small part, to export this eye pattern right margin position signalling, this second phase interpolator is adjusted this right side phase interpolation output signal according to this eye pattern right margin position signalling; And a reset control circuit, be used to one fixing during after, reset this eye pattern left margin position signal generator and this eye pattern right margin position signal generator.
5. device as claimed in claim 4 is characterized in that, this eye pattern center signal generating circuit comprises:
One third phase position interpolater is in order to receive this eye pattern left margin position signalling, this eye pattern right margin position signalling and this phase-locked loop output signal to small part, so that this eye pattern center signal to take place; And a voltage control delay circuit, this different sampled signal of a plurality of phase places takes place according to this eye pattern center signal.
6. device as claimed in claim 5, it is characterized in that, this reset control circuit comprises a counter, this counter receives this data-signal, in this counter is during this is fixing after the data of reception fixed number, this reset control circuit is exported one first reset signal and one second reset signal to this eye pattern left margin position signal generator and this eye pattern right margin position signal generator.
7. device as claimed in claim 6, it is characterized in that, this first phase-lead falls behind detector and according to two these phase-locked loop output signals one first wayside signaling takes place, during this first wayside signaling activation, this first phase-lead falls behind detector relatively phase place of this pulse wave signal and the phase place of this left side phase interpolation output signal, if the phase place that the phase lag of this pulse wave signal should left side phase interpolation output signal, then the backward detector of this first phase-lead is controlled this first phase interpolator, make the phase place of this left side phase interpolation output signal increase, otherwise, then do not change the phase place of this left side phase interpolation output signal.
8. device as claimed in claim 7, it is characterized in that this first phase-lead falls behind detector and receives this first reset signal, when this first reset signal activation, then eye pattern left margin position signalling is controlled this first phase interpolator, makes the phase place of this left side phase interpolation output signal reduce.
9. device as claimed in claim 6, it is characterized in that, this second phase-lead falls behind detector and according to two these phase-locked loop output signals one second wayside signaling takes place, during this second wayside signaling activation, this second phase-lead falls behind detector relatively phase place of this pulse wave signal and the phase place of this right side phase interpolation output signal, if the phase place that the phase-lead of this pulse wave signal should left side phase interpolation output signal, then the backward detector of this second phase-lead is controlled this second phase interpolator, make the phase place of this right side phase interpolation output signal reduce, otherwise, then do not change the phase place of this right side phase interpolation output signal.
10. device as claimed in claim 9, it is characterized in that, this second phase-lead falls behind detector and receives this second reset signal, when this second reset signal activation, then this eye pattern right margin position signalling is controlled this second phase interpolator, makes the phase place of this right side phase interpolation output signal increase.
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| CNB2004100628816A CN100481728C (en) | 2004-07-05 | 2004-07-05 | Time pulse return apparatus of low voltage differential signal and method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102739250A (en) * | 2011-04-07 | 2012-10-17 | 中山大学 | Current correcting digital-to-analog converter |
| CN106330596A (en) * | 2015-07-03 | 2017-01-11 | 中兴通讯股份有限公司 | Signal detection method and signal detection device |
| CN113129950A (en) * | 2019-12-30 | 2021-07-16 | 群联电子股份有限公司 | Signal receiving circuit, memory storage device and signal receiving method |
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2004
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102739250A (en) * | 2011-04-07 | 2012-10-17 | 中山大学 | Current correcting digital-to-analog converter |
| CN102739250B (en) * | 2011-04-07 | 2015-04-22 | 中山大学 | Current correcting digital-to-analog converter |
| CN106330596A (en) * | 2015-07-03 | 2017-01-11 | 中兴通讯股份有限公司 | Signal detection method and signal detection device |
| CN113129950A (en) * | 2019-12-30 | 2021-07-16 | 群联电子股份有限公司 | Signal receiving circuit, memory storage device and signal receiving method |
| CN113129950B (en) * | 2019-12-30 | 2023-07-04 | 群联电子股份有限公司 | Signal receiving circuit, memory storage device and signal receiving method |
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