CN102739250B - Current correcting digital-to-analog converter - Google Patents
Current correcting digital-to-analog converter Download PDFInfo
- Publication number
- CN102739250B CN102739250B CN201110094543.0A CN201110094543A CN102739250B CN 102739250 B CN102739250 B CN 102739250B CN 201110094543 A CN201110094543 A CN 201110094543A CN 102739250 B CN102739250 B CN 102739250B
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrically connected
- lock
- group
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention relates to a current correcting digital-to-analog converter which comprises a signal transmitting group, a digital-to-analog converting circuit, a current compensation circuit, and a voltage output end, wherein the signal transmitting group is provided with a plurality of control signal ends, the digital-to-analog converting circuit comprises a first inverter group, a first transistor group, and a resistor. The first inverter group is electrically connected to the signal transmitting group, the first transistor group is electrically connected to the first inverter group, and the resistor is electrically connected to the first transistor group. The current compensation circuit comprises an AND gate group, a second inverter group, and a second transistor group, wherein the AND gate group is electrically connected to the control signal ends of the signal transmitting group, the second inverter group is electrically connected to the AND gate group, the second transistor group is electrically connected to the second inverter group. The first transistor group, the second transistor group, and the resistor are all electrically connected to the voltage output end.
Description
Technical field
The present invention relates to a kind of digital analog converter, particularly relate to a kind of current correction digital analog converter.
Background technology
Digital analog converter is the conversion equipment one or more groups digital signal being converted to analog signal, the analog output signal of digital analog converter is very easily subject to external environment, the impact of technique drift and circuit design and produce the phenomenon of signal skew, so will significantly affect the linearity of analog output signal, therefore the differential type digital analog converter disclosed by No. 7242338B2nd, United States Patent (USP) is in order to improve this phenomenon, refer to Fig. 4, this differential type digital analog converter 20 has one first signal input buffer device 21, one secondary signal input buffer 22, multiple bit element switch 23, at least one thermometer-code switch 24, multiple R-2R electric resistance structure 25, one first output 26 and one second output 27, wherein those bit element switchs 23 and this thermometer-code switch 24 are electrically connected this first signal input buffer device 21 and this secondary signal input buffer 22, respectively this R-2R electric resistance structure 25 is electrically connected respectively this bit element switch 23 and this thermometer-code switch 24, this first output 26 and this second output 27 are electrically connected those R-2R electric resistance structures 25, this differential type digital analog converter 20 by those bit element switchs 23 to determine whether this first signal input buffer device 21 and this secondary signal input buffer 22 input one first reference signal and one second reference signal respectively to compensate the terminal voltage of this first output 26 and this second output 27, only, those R-2R electric resistance structures 25 are easy to be subject to the impact of technique drift and resistance value are changed between R to 2R, situation of not mating respectively between this R-2R electric resistance structure 25 will significantly reduce the linearity of this differential digital analog converter 20.
As can be seen here, above-mentioned existing digital analog converter with in use in structure, obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development, and common product does not have appropriate structure to solve the problem, this is obviously the anxious problem for solving of relevant dealer always.Therefore how to found a kind of novel digital analog converter, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
Main purpose of the present invention is, a kind of current correction digital analog converter is provided, by this current compensation circuit, current compensation action is carried out to this D/A conversion circuit, and adopt this first control signal end, this the second control signal end, 3rd control signal end, 4th control signal end and the 5th control signal end are as the current compensation input of this current compensation circuit, by those control signal ends and this current compensation circuit should and the electric connection of lock group design, effectively can promote the electric current linearity of this D/A conversion circuit, and make this digital analog converter reach effect of high accurancy and precision.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of current correction digital analog converter that the present invention proposes, it comprises: a signal transmission group, and it has one first control signal end, one second control signal end, one the 3rd control signal end, one the 4th control signal end and one the 5th control signal end; One D/A conversion circuit, it has one first inverter group, a first transistor group and a resistance, this first inverter group is electrically connected this signal transmission group, and this first transistor group is electrically connected this first inverter group, and this resistance is electrically connected this first transistor group; One current compensation circuit, it has one and lock group, one second inverter group and a transistor seconds group, should and lock group be electrically connected this first control signal end of this signal transmission group, this second control signal end, the 3rd control signal end, the 4th control signal end and the 5th control signal end, this second inverter group is electrically connected to be somebody's turn to do and lock group, and this transistor seconds group is electrically connected this second inverter group; And a voltage output end, this first transistor group, this resistance and this transistor seconds group are electrically connected this voltage output end.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid current correction digital analog converter, wherein said current compensation circuit should and lock group there is one first and lock, one second and lock, one the 3rd and lock, one the 4th and lock, one the 5th and lock, one the 6th and lock, one the 7th and lock, one the 8th and lock, one the 9th and lock and the tenth and lock, wherein this first and lock be electrically connected this first control signal end and this second control signal end, this second and lock be electrically connected this first control signal end and the 3rd control signal end, 3rd and lock be electrically connected the 4th control signal end, 4th and lock be electrically connected the 4th control signal end and the 5th control signal end, 5th and lock be electrically connected the 3rd control signal end and the 5th control signal end, 6th and lock be electrically connected the 3rd control signal end and the 4th control signal end, this first and lock there is an output, this output is electrically connected the 3rd and lock, 7th and lock, 8th and lock, 9th and lock and the tenth and lock.
Aforesaid current correction digital analog converter, this second inverter group of wherein said current compensation circuit has one first inverter, one second inverter, one the 3rd inverter, one the 4th inverter, one the 5th inverter, one hex inverter and one the 7th inverter, this first inverter be electrically connected this first and lock, this second inverter be electrically connected this second and lock, 3rd inverter is electrically connected the 3rd and lock, 4th inverter is electrically connected the 7th and lock, 5th inverter is electrically connected the 8th and lock, this hex inverter is electrically connected the 9th and lock, 7th inverter is electrically connected the tenth and lock.
Aforesaid current correction digital analog converter, this transistor seconds group of wherein said current compensation circuit has a first transistor, one transistor seconds, one third transistor, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor, one the 8th transistor, one the 9th transistor, the tenth transistor, the 11 transistor, the tenth two-transistor, the 13 transistor and 1 the 14 transistor, this first inverter is electrically connected this first transistor, this second inverter is electrically connected this transistor seconds, 3rd inverter is electrically connected this third transistor, 4th inverter is electrically connected the 4th transistor, 5th inverter is electrically connected the 5th transistor, this hex inverter is electrically connected the 6th transistor, 7th inverter is electrically connected the 7th transistor, 8th electric transistor connects this first transistor, 9th electric transistor connects this transistor seconds, tenth electric transistor connects this third transistor, 11 electric transistor connects the 4th transistor, tenth two-transistor is electrically connected the 5th transistor, 13 electric transistor connects the 6th transistor, 14 electric transistor connects the 7th transistor.
Aforesaid current correction digital analog converter, this the first transistor group of wherein said D/A conversion circuit has a first transistor, one transistor seconds, one third transistor, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor, one the 8th transistor, one the 9th transistor and 1 the tenth transistor, this the first transistor is electrically connected the 9th transistor, this transistor seconds is electrically connected the tenth transistor, this third transistor, 4th transistor, 5th transistor, 6th transistor, 7th transistor, 8th transistor, 9th transistor and the tenth electric transistor connect this resistance and this voltage output end.
Aforesaid current correction digital analog converter, it separately has a bias input, and this bias input is electrically connected this first transistor group and this transistor seconds group.
Aforesaid current correction digital analog converter, wherein said signal transmission group separately has one the 6th control signal end, one the 7th control signal end and one the 8th control signal end, and this inverter group is electrically connected the 6th control signal end, the 7th control signal end and the 8th control signal end.
The present invention compared with prior art has obvious advantage and beneficial effect.
By technique scheme, current correction digital analog converter of the present invention at least has following advantages and beneficial effect: the present invention carries out current compensation action by this current compensation circuit to this D/A conversion circuit, and adopt this first control signal end, this the second control signal end, 3rd control signal end, 4th control signal end and the 5th control signal end are as the current compensation input of this current compensation circuit, by those control signal ends and this current compensation circuit should and the electric connection of lock group design, effectively can promote the electric current linearity of this D/A conversion circuit, and make this digital analog converter reach effect of high accurancy and precision.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is according to preferred embodiment of the present invention, a kind of circuit block diagram of current correction digital analog converter.
Fig. 2 is according to preferred embodiment of the present invention, the circuit diagram of the D/A conversion circuit of this current correction digital analog converter.
Fig. 3 is according to preferred embodiment of the present invention, the circuit diagram of the current compensation circuit of this current correction digital analog converter.
Fig. 4 is the circuit diagram of existing known digital analog converter.
10: current correction digital analog converter
11: signal transmission group
111: the first control signal end 112: the second control signal ends
113: the three control signal end 114: the four control signal ends
115: the five control signal end 116: the six control signal ends
117: the seven control signal end 118: the eight control signal ends
12: D/A conversion circuit
121: the first inverter group
1211: the first inverter 1212: the second inverters
1213: the three inverter 1214: the four inverters
1215: the five inverter 1216: the hex inverters
1217: the seven inverter 1218: the eight inverters
122: the first transistor group
122a: the first transistor 122b: transistor seconds
122c: third transistor 122d: the four transistor
122e: the five transistor 122f: the six transistor
122g: the seven transistor 122h: the eight transistor
122i: the nine transistor 122j: the ten transistor
122k: the ten one transistor 122l: the ten two-transistor
122m: the ten three transistor 122n: the 14 transistor
122o: the ten five transistor 122p: the 16 transistor
122q: the ten seven transistor 122r: the 18 transistor
123: resistance
13: current compensation circuit
131: and lock group
1311: the first and lock 1311a: output
1312: the second and lock 1313: the three and lock
1314: the four and lock 1315: the five and lock
1316: the six and lock 1317: the seven and lock
1318: the eight and lock 1319: the nine and lock
131a: the ten and lock
132: the second inverter group
1321: the first inverter 1,322 second inverters
1323: the three inverter 1324 the 4th inverters
1325: the five inverter 1326: the hex inverters
1327: the seven inverters
133: transistor seconds group
133a: the first transistor 133b: transistor seconds
133c: third transistor 133d: the four transistor
133e: the five transistor 133f: the six transistor
133g: the seven transistor 133h: the eight transistor
133i: the nine transistor 133j: the ten transistor
133k: the ten one transistor 133l: the ten two-transistor
133m: the ten three transistor 133n: the 14 transistor
14: voltage output end
15: bias input
20: differential type digital analog converter
21: the first signal input buffer devices
22: secondary signal input buffer
23: bit element switch 24 thermometer-code switch
25:R-2R electric resistance structure 26: the first output
27: the second outputs
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of current correction digital analog converter proposed according to the present invention, structure, feature and effect thereof, be described in detail as follows.
Refer to Fig. 1, shown in Fig. 2 and Fig. 3, it is a preferred embodiment of the present invention, a kind of current correction digital analog converter 10 comprises a signal transmission group 11, one D/A conversion circuit 12, one current compensation circuit 13 and a voltage output end 14, this signal transmission group 11 has one first control signal end 111, one second control signal end 112, one the 3rd control signal end 113, one the 4th control signal end 114 and one the 5th control signal end 115, this D/A conversion circuit 12 has one first inverter group 121, one the first transistor group 122 and a resistance 123, this first inverter group 121 is electrically connected this signal transmission group 11, this the first transistor group 122 is electrically connected this first inverter group 121, this resistance 123 is electrically connected this first transistor group 122, this current compensation circuit 13 has one and lock group 131, one second inverter group 132 and a transistor seconds group 133, this and lock group 131 are electrically connected this first control signal end 111, this the second control signal end 112, 3rd control signal end 113, 4th control signal end 114 and the 5th control signal end 115, this second inverter group 132 is electrically connected is somebody's turn to do and lock group 131, this transistor seconds group 133 is electrically connected this second inverter group 132, this the first transistor group 122, this transistor seconds group 133 and this resistance 123 are electrically connected this voltage output end 14, in the present embodiment, this the first transistor group 122 and this transistor seconds group 133 are by multiple metal-oxide half field effect transistor (metal-oxide-semiconductor field-effecttransistor, MOSFET) formed.
Referring again to Fig. 2, in the present embodiment, this signal transmission group 11 separately has one the 6th control signal end 116, one the 7th control signal end 117, and one the 8th control signal end 118, this first inverter group 121 is electrically connected the 6th control signal end 116, 7th control signal end 117 and the 8th control signal end 118, respectively this transmitting terminal can provide a digital controlled signal, this first inverter group 121 has the first inverter 1211 of this first control signal end 111 of an electric connection, second inverter 1212 of one this second control signal end 112 of electric connection, 3rd inverter 1213 of one electric connection the 3rd control signal end 113, 4th inverter 1214 of one electric connection the 4th control signal end 114, 5th inverter 1215 of one electric connection the 5th control signal end 115, the hex inverter 1216 of one electric connection the 6th control signal end 116, one is electrically connected the 7th inverter 1217 of the 7th control signal end 117 and the 8th inverter 1218 of electric connection a 8th control signal end 118, referring again to Fig. 2, this the first transistor group 122 of this D/A conversion circuit 12 has a first transistor 122a, one transistor seconds 122b, one third transistor 122c, one the 4th transistor 122d, one the 5th transistor 122e, one the 6th transistor 122f, one the 7th transistor 122g, one the 8th transistor 122h, one the 9th transistor 122i and the tenth transistor 122j, respectively this inverter is electrically connected respectively this transistor, preferably, this the first transistor 122a is electrically connected the 9th transistor 122i, this transistor seconds 122b is electrically connected the tenth transistor 122j, this third transistor 122c, 4th transistor 122d, 5th transistor 122e, 6th transistor 122f, 7th transistor 122g, 8th transistor 122h, 9th transistor 122i and the tenth transistor 122j is electrically connected this resistance 123 and this voltage output end 14, in the present embodiment, 9th transistor 122i and the tenth transistor 122j is in order to increase output impedance, to alleviate the current variation that this first control signal end 111 and this second control signal end 112 cause when signal switching, reduce noise interference, in addition, the drain electrode end of the 9th transistor 122i is highest significant position unit (Most Significant Bit, MSB) hold, the drain electrode end of the 8th transistor 122h is least significant bit (Least SignificantBit, LSB) hold, referring again to Fig. 2, this the first transistor group 122 separately has the 11 transistor 122k of this first transistor of electric connection 122a, the tenth two-transistor 122l of one this transistor seconds of electric connection 122b, the 13 transistor 122m of one this third transistor 122c of electric connection, the 14 transistor 122n of one electric connection the 4th transistor 122d, the 15 transistor 122o of one electric connection the 5th transistor 122e, the 16 transistor 122p of one electric connection the 6th transistor 122f, one the 17 transistor 122q and being electrically connected the 7th transistor 122g is electrically connected the 18 transistor 122r of the 8th transistor 122h, in the present embodiment, this current correction digital analog converter 10 separately has a bias input 15, this bias input 15 is electrically connected this first transistor group 122 and this transistor seconds group 133, this bias input 15 is in order to produce multiple current source, from least significant bit end to highest significant position, to the size of those current sources unit's end increase with the power side of 2, in addition, those transistors can be considered a switch, whether those switches in order to determine the circulation of those current sources.
Referring again to Fig. 3, due to the 6th control signal end 116, 7th control signal end 117 and the 8th control signal end 118 within the control signal time interval signal skew and not obvious, therefore the present embodiment selects this first control signal end 111, this the second control signal end 112, 3rd control signal end 113, 4th control signal end 114 and the 5th control signal end 115 are as the current compensation input of this current compensation circuit 13, in the present embodiment, this current compensation circuit 13 should and lock group 131 there is one first and lock 1311, one second and lock 1312, one the 3rd and lock 1313, one the 4th and lock 1314, one the 5th and lock 1315, one the 6th and lock 1316, one the 7th and lock 1317, one the 8th and lock 1318, one the 9th and lock 1319 and the tenth and lock 131a, wherein this first and lock 1311 be electrically connected this first control signal end 111 and this second control signal end 112, this second and lock 1312 be electrically connected this first control signal end 111 and the 3rd control signal end 113, 3rd and lock 1313 be electrically connected the 4th control signal end 114, 4th and lock 1314 be electrically connected the 4th control signal end 114 and the 5th control signal end 115, 5th and lock 1315 be electrically connected the 3rd control signal end 113 and the 5th control signal end 115, 6th and lock 1316 be electrically connected the 3rd control signal end 113 and the 4th control signal end 114, this first and lock 1311 there is an output 1311a, this output 1311a is electrically connected the 3rd and lock 1313, 7th and lock 1317, 8th and lock 1318, 9th and lock 1319 and the tenth and lock 131a, referring again to Fig. 3, this second inverter group 132 of this current compensation circuit 13 has one first inverter 1321, one second inverter 1322, one the 3rd inverter 1323, one the 4th inverter 1324, one the 5th inverter 1325, one hex inverter 1326 and one the 7th inverter 1327, this first inverter 1321 be electrically connected this first and lock 1311, this second inverter 1322 be electrically connected this second and lock 1312, 3rd inverter 1323 is electrically connected the 3rd and lock 1313, 4th inverter 1324 is electrically connected the 7th and lock 1317, 5th inverter 1325 is electrically connected the 8th and lock 1318, this hex inverter 1326 is electrically connected the 9th and lock 1319, 7th inverter 1327 is electrically connected the tenth and lock 131a, referring again to Fig. 3, this transistor seconds group 133 of this current compensation circuit 13 has a first transistor 133a, one transistor seconds 133b, one third transistor 133c, one the 4th transistor 133d, one the 5th transistor 133e, one the 6th transistor 133f, one the 7th transistor 133g, one the 8th transistor 133h, one the 9th transistor 133i, the a tenth transistor 133j, the a 11 transistor 133k, the a tenth two-transistor 133l, the a 13 transistor 133m and 1 the 14 transistor 133n, this first inverter 1321 is electrically connected this first transistor 133a, this second inverter 1322 is electrically connected this transistor seconds 133b, 3rd inverter 1323 is electrically connected this third transistor 133c, 4th inverter 1324 is electrically connected the 4th transistor 133d, 5th inverter 1325 is electrically connected the 5th transistor 133e, this hex inverter 1326 is electrically connected the 6th transistor 133f, 7th inverter 1327 is electrically connected the 7th transistor 133g, 8th transistor 133h is electrically connected this first transistor 133a, 9th transistor 133i is electrically connected this transistor seconds 133b, tenth transistor 133j is electrically connected this third transistor 133c, 11 transistor 133k is electrically connected the 4th transistor 133d, tenth two-transistor 133l is electrically connected the 5th transistor 133e, 13 transistor 133m is electrically connected the 6th transistor 133f, 14 transistor 133n is electrically connected the 7th transistor 133g, after current compensation via this current compensation circuit 13, this current correction digital analog converter 10 exports integral non-linearity (the Integrated Non-linearity of bit, and differential nonlinearity (Differential Non-linearity INL), DNL) all can lower than 0.5LSB.
The present invention adopts this first control signal end 111, this the second control signal end 112, 3rd control signal end 113, 4th control signal end 114 and the 5th control signal end 115 are as the current compensation input of this current compensation circuit 13, by those control signal ends and this current compensation circuit 13 should and the electric connection of lock group 131 design, make integral non-linearity (the Integrated Non-linearity that this D/A conversion circuit 12 produces, and differential nonlinearity (Differential Non-linearity INL), DNL) all can lower than 0.5LSB, reach high accurancy and precision, the requirement of this current correction digital analog converter 10 of high linearity.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (3)
1. a current correction digital analog converter, is characterized in that it comprises:
One signal transmission group, it has one first control signal end, one second control signal end, one the 3rd control signal end, one the 4th control signal end and one the 5th control signal end;
One D/A conversion circuit, it has one first inverter group, a first transistor group and a resistance, this first inverter group is electrically connected this signal transmission group, and this first transistor group is electrically connected this first inverter group, and this resistance is electrically connected this first transistor group;
One current compensation circuit, it has one and lock group, one second inverter group and a transistor seconds group, should and lock group be electrically connected this first control signal end of this signal transmission group, this second control signal end, the 3rd control signal end, the 4th control signal end and the 5th control signal end, this second inverter group is electrically connected to be somebody's turn to do and lock group, and this transistor seconds group is electrically connected this second inverter group; And
One voltage output end, this first transistor group, this resistance and this transistor seconds group are electrically connected this voltage output end;
Wherein, this and lock group have one first and lock, one second and lock, one the 3rd and lock, one the 4th and lock, one the 5th and lock, one the 6th and lock, one the 7th and lock, one the 8th and lock, one the 9th and lock and the tenth and lock, wherein this first and lock be electrically connected this first control signal end and this second control signal end, this second and lock be electrically connected this first control signal end and the 3rd control signal end, 3rd and lock be electrically connected the 4th control signal end, 4th and lock be electrically connected the 4th control signal end and the 5th control signal end, 5th and lock be electrically connected the 3rd control signal end and the 5th control signal end, 6th and lock be electrically connected the 3rd control signal end and the 4th control signal end, this first and lock there is an output, this output is electrically connected the 3rd and lock, 7th and lock, 8th and lock, 9th and lock and the tenth and lock,
This second inverter group has one first inverter, one second inverter, one the 3rd inverter, one the 4th inverter, one the 5th inverter, a hex inverter and one the 7th inverter, this first inverter be electrically connected this first and lock, this second inverter be electrically connected this second and lock, 3rd inverter is electrically connected the 3rd and lock, 4th inverter is electrically connected the 7th and lock, 5th inverter is electrically connected the 8th and lock, this hex inverter is electrically connected the 9th and lock, and the 7th inverter is electrically connected the tenth and lock;
This transistor seconds group has a first transistor, one transistor seconds, one third transistor, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor, one the 8th transistor, one the 9th transistor, the tenth transistor, the 11 transistor, the tenth two-transistor, the 13 transistor and 1 the 14 transistor, this first inverter is electrically connected this first transistor, this second inverter is electrically connected this transistor seconds, 3rd inverter is electrically connected this third transistor, 4th inverter is electrically connected the 4th transistor, 5th inverter is electrically connected the 5th transistor, this hex inverter is electrically connected the 6th transistor, 7th inverter is electrically connected the 7th transistor, 8th electric transistor connects this first transistor, 9th electric transistor connects this transistor seconds, tenth electric transistor connects this third transistor, 11 electric transistor connects the 4th transistor, tenth two-transistor is electrically connected the 5th transistor, 13 electric transistor connects the 6th transistor, 14 electric transistor connects the 7th transistor,
This the first transistor group has a first transistor, one transistor seconds, one third transistor, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor, one the 8th transistor, one the 9th transistor and 1 the tenth transistor, this the first transistor is electrically connected the 9th transistor, this transistor seconds is electrically connected the tenth transistor, this third transistor, 4th transistor, 5th transistor, 6th transistor, 7th transistor, 8th transistor, 9th transistor and the tenth electric transistor connect this resistance and this voltage output end.
2. current correction digital analog converter according to claim 1, is characterized in that it separately has a bias input, and this bias input is electrically connected this first transistor group and this transistor seconds group.
3. current correction digital analog converter according to claim 1, it is characterized in that wherein said signal transmission group separately has one the 6th control signal end, one the 7th control signal end and one the 8th control signal end, this first inverter group is electrically connected the 6th control signal end, the 7th control signal end and the 8th control signal end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110094543.0A CN102739250B (en) | 2011-04-07 | 2011-04-07 | Current correcting digital-to-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110094543.0A CN102739250B (en) | 2011-04-07 | 2011-04-07 | Current correcting digital-to-analog converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102739250A CN102739250A (en) | 2012-10-17 |
| CN102739250B true CN102739250B (en) | 2015-04-22 |
Family
ID=46994129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110094543.0A Active CN102739250B (en) | 2011-04-07 | 2011-04-07 | Current correcting digital-to-analog converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102739250B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104298287B (en) * | 2013-07-17 | 2016-04-20 | 联发科技（新加坡）私人有限公司 | Current correction method and device and resistance bearing calibration and device |
| TWI501561B (en) * | 2014-01-06 | 2015-09-21 | Univ Southern Taiwan Sci & Tec | Digital-to-analog converting device and method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577454A (en) * | 2003-07-07 | 2005-02-09 | 精工爱普生株式会社 | Digital/analog conversion circuit, electrooptical apparatus and electronic equipment |
| CN1719732A (en) * | 2004-07-05 | 2006-01-11 | 友达光电股份有限公司 | Time pulse return apparatus of low voltage differential signal and method thereof |
| CN101282076A (en) * | 2007-03-29 | 2008-10-08 | 英特赛尔美国股份有限公司 | Multi-module current sharing scheme |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI357214B (en) * | 2008-07-01 | 2012-01-21 | Univ Nat Taiwan | Phase locked loop (pll) with leakage current calib |
-
2011
- 2011-04-07 CN CN201110094543.0A patent/CN102739250B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577454A (en) * | 2003-07-07 | 2005-02-09 | 精工爱普生株式会社 | Digital/analog conversion circuit, electrooptical apparatus and electronic equipment |
| CN1719732A (en) * | 2004-07-05 | 2006-01-11 | 友达光电股份有限公司 | Time pulse return apparatus of low voltage differential signal and method thereof |
| CN101282076A (en) * | 2007-03-29 | 2008-10-08 | 英特赛尔美国股份有限公司 | Multi-module current sharing scheme |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102739250A (en) | 2012-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103620964B (en) | Switch sequencing for code-range-specific linearity improvement in digital-to-analog converters | |
| Yu et al. | A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS | |
| US9559715B2 (en) | Successive approximation resister analog-to-digital converter having separable dual capacitor array | |
| US10566990B2 (en) | Segmented resistor string type digital to analog converter and control system thereof | |
| WO2010108292A3 (en) | Switching device having a cascode circuit | |
| US8710541B2 (en) | Bi-directional switch using series connected N-type MOS devices in parallel with series connected P-type MOS devices | |
| US8130133B2 (en) | A/D converter using isolation switches | |
| CN104716962A (en) | Digital-analog converter unit and current steering type digital-analog converter | |
| CN102739250B (en) | Current correcting digital-to-analog converter | |
| KR101680080B1 (en) | Time interleaved pipeline SAR ADC for minimizing channel offset mismatch | |
| CN101986570B (en) | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof | |
| Yi | An 8-bit current-steering digital to analog converter | |
| US8937568B2 (en) | D/A converter | |
| CN101588179B (en) | Current steering digital-to-analog converter | |
| CN101895195A (en) | Ultrahigh pressure signal interface circuit | |
| CN108540135A (en) | A kind of digital analog converter and conversion circuit | |
| US20120161997A1 (en) | Digital-to-analog conversion device | |
| TWI430583B (en) | Digital/analog converter with current compensation | |
| US20110241920A1 (en) | Resistance-type digital-to-analog converter | |
| CN116192149A (en) | High-voltage-resistant current rudder digital-to-analog converter and chip | |
| Wang et al. | A 1.2 V 1.0-GS/s 8-bit voltage-buffer-free folding and interpolating ADC | |
| CN101043208A (en) | Amplifier circuit and gain control method thereof | |
| KR20050103541A (en) | Analog-digital converter using clock boosting | |
| CN109787635A (en) | D/A converting circuit and its digital-analog convertion method, display device | |
| CN101197574B (en) | Switch current unit and its array used for current rudder type D/A converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |