CN101588179B - Current steering digital-to-analog converter - Google Patents
Current steering digital-to-analog converter Download PDFInfo
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- CN101588179B CN101588179B CN2008101121826A CN200810112182A CN101588179B CN 101588179 B CN101588179 B CN 101588179B CN 2008101121826 A CN2008101121826 A CN 2008101121826A CN 200810112182 A CN200810112182 A CN 200810112182A CN 101588179 B CN101588179 B CN 101588179B
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Abstract
The invention discloses a current steering digital-to-analog converter, which comprises a driving buffer and a current source, wherein the current source also comprises a first switching transistor and a second switching transistor, the driving buffer also comprises a first input end, a second input end, a first phase inverter consisting of a first PMOS transistor, a first NMOS transistor and a first transistor, and a second phase inverter consisting of a second PMOS transistor, a second NMOS transistor and a second transistor, a grid of the first switching transistor is connected with a grid of the second transistor and a drain of the first PMOS transistor or the first NMOS transistor, and a grid of the second switching transistor is connected with a grid of the first transistor and a drain of the second PMOS transistor or the second NMOS transistor. The current steering digital-to-analog converter can reduce the fluctuation of nodal voltage between two switching transistors of the current source and burrs of output signals.
Description
Technical field
The present invention relates to digital to analog converter, relate in particular to a kind of current steering digital-to-analog converter.
Background technology
Current steering digital-to-analog converter (Current Steering Digital-to-Analog Converter) is based on current source matrix, directly driving resistor load, realize high-speed digital-to-analogue conversion, can reach very high performance, therefore be widely used.
The parameter index of weighing current steering digital-to-analog converter is except static properties, as: resolution (Resolution), DNL degree (DNL, Differencial NonLiner) etc., its dynamic property is also very crucial, as: signal to noise ratio (SNR, Signal-to-Noise Ratio), intermodulation distortion (IMD, Intermodulation Distortion) etc.
The factor that influences the current steering digital-to-analog converter dynamic property mainly contains following two aspects: the sequential of added two switching transistors of (1) current source is improper; (2) grid control signal of two of current source switching transistors can not be well synchronous.Below either way may cause two switching transistors of current source to be in off state simultaneously, make that the node voltage between it produces fluctuation, thereby cause output signal to produce burr (Glitch).
Be illustrated in figure 1 as current steering digital-to-analog converter of the prior art, comprise and drive buffer 1 (Buffer) and current source 2 two parts, driving buffer 1 further comprises: two digital signal input ends 11,12, first inverter that constitutes by PMOS transistor 13 and NNOS transistor 14, second inverter that constitutes by PMOS transistor 15 and NNOS transistor 16; Current source 2 further comprises: 21,22, two current output terminals 23,24 of two PMOS switching transistors, and bias voltage input 25 and the 3rd switching transistor 26.
Among Fig. 1, SEL and SEL_N represent two digital input signals (being the grid control signal of two switching transistors of current source), Vhigh and Vlow are the voltage of keeping PMOS transistor and nmos pass transistor work in the inverter, Vg and Vgn are the grid level of two switching transistors, Vx represents two node voltages between the switching transistor, Iout and Iout_n represent output current, Vbias is a bias voltage, by the bias of Vbias, make the constant supply of current of generation between Vhigh and the Vx.Wherein, the rollback point of the grid level of two switching transistors (Vg and Vgn) intersects at the centre position, as shown in Figure 2.
May there be following problem in current steering digital-to-analog converter among Fig. 1 when working: digital input signals (SEL and SEL_N) is if can not be synchronous well, the situation that two switching transistors of current source may occur turn-offing simultaneously, two switching transistors are in case turn-off simultaneously, then can cause the node voltage (Vx) between it to rise, cause output signal to produce burr (Glitch), influence the dynamic property of digital to analog converter.
Can be in the prior art by increasing nmos pass transistor or the PMOS transistor size that drives buffer, the signal rollback point of two switching transistors of control is reduced, to reduce the situation that two switching transistors turn-off simultaneously, if but digital input signals (being grid control signal) can not be synchronous, the problems referred to above also can't be avoided.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of current steering digital-to-analog converter, the situation that can effectively avoid two switching transistors of current source to turn-off simultaneously, thereby reduce the burr energy of the fluctuating range and the output signal of current source node voltage, realized the optimization of digital to analog converter dynamic property.
For achieving the above object, the embodiment of the invention provides a kind of current steering digital-to-analog converter, comprises driving buffer and current source, and described current source further comprises: first switching transistor and second switch transistor, it is characterized in that described driving buffer further comprises:
First input end is used to import first digital signal;
By first inverter that a PMOS transistor, first nmos pass transistor and the first transistor constitute, be used for described first digital signal is carried out anti-phase processing first control signal of controlled described first switching transistor;
The transistorized grid of a described PMOS is connected with described first input end, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the source electrode of described the first transistor;
The grid of described first nmos pass transistor is connected with described first input end, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the drain electrode of described the first transistor and the grid of described first switching transistor;
Second input is used to import second digital signal;
By second inverter that the 2nd PMOS transistor, second nmos pass transistor and transistor seconds constitute, be used for described second digital signal is carried out anti-phase processing transistorized second control signal of controlled described second switch;
The transistorized grid of described the 2nd PMOS is connected with described second input, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the source electrode of described transistor seconds;
The grid of described second nmos pass transistor is connected with described second input, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the transistorized grid of described second switch with the drain electrode of described transistor seconds;
The grid of described the first transistor is connected with the transistorized grid of described second switch;
The grid of described transistor seconds is connected with the grid of described first switching transistor.
Described first switching transistor, described second switch transistor, described the first transistor and described transistor seconds are the PMOS transistor.
Conducting when described the first transistor is lower than first predetermined level at the level of described second control signal is turn-offed when the level of described second control signal is higher than described first predetermined level;
Conducting when described transistor seconds is lower than second predetermined level at the level of described first control signal is turn-offed when the level of described first control signal is higher than described second predetermined level.
Described first predetermined level is by the size decision of described the first transistor, described first nmos pass transistor;
Described second predetermined level is by the size decision of described transistor seconds and described second nmos pass transistor.
Described first predetermined level equates with described second predetermined level.
The embodiment of the invention also provides a kind of current steering digital-to-analog converter, comprises driving buffer and current source, and described current source further comprises: first switching transistor and second switch transistor, and described driving buffer further comprises:
First input end is used to import first digital signal;
By first inverter that a PMOS transistor, first nmos pass transistor and the first transistor constitute, be used for described first digital signal is carried out anti-phase processing first control signal of controlled described first switching transistor;
The transistorized grid of a described PMOS is connected with described first input end, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the drain electrode of described the first transistor and the grid of described first switching transistor;
The grid of described first nmos pass transistor is connected with described first input end, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the source electrode of described the first transistor;
Second input is used to import second digital signal;
By second inverter that the 2nd PMOS transistor, second nmos pass transistor and transistor seconds constitute, be used for described second digital signal is carried out anti-phase processing transistorized second control signal of controlled described second switch;
The transistorized grid of described the 2nd PMOS is connected with described second input, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the transistorized grid of described second switch with the drain electrode of described transistor seconds;
The grid of described second nmos pass transistor is connected with described second input, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the source electrode of described transistor seconds;
The grid of described the first transistor is connected with the transistorized grid of described second switch;
The grid of described transistor seconds is connected with the grid of described first switching transistor.
Described first switching transistor, described second switch transistor, described the first transistor and described transistor seconds are nmos pass transistor.
Described the first transistor turn-offs when the level of described second control signal is lower than first predetermined level, conducting when the level of described second control signal is higher than described first predetermined level;
Described transistor seconds turn-offs when the level of described first control signal is lower than second predetermined level, conducting when the level of described first control signal is higher than described second predetermined level.
Described first predetermined level is by described the first transistor, the transistorized size decision of a described PMOS;
Described second predetermined level is by described transistor seconds and the transistorized size decision of described the 2nd PMOS.
Described first predetermined level equates with described second predetermined level.
Embodiments of the invention have following beneficial effect:
By on the inverter of current steering digital-to-analog converter, increasing the transistor of two polyphones, make that the grid control signal of two switching transistors of current source is checked and balance, avoided two grid control signals to be the situation of high level simultaneously, thereby two situation generations that switching transistor turn-offs have simultaneously been avoided, reduce the fluctuating range of node voltage of current supply switch and the energy of output signal burr, realized the optimization of current steering digital-to-analog converter dynamic property.
Description of drawings
Fig. 1 is the digital-to-analog converter structures schematic diagram of prior art;
Fig. 2 is the transistorized grid level rollback point of a current supply switch schematic diagram in the digital to analog converter of prior art;
Fig. 3 is a current steering digital-to-analog converter structural representation of the embodiment of the invention;
Fig. 4 is another current steering digital-to-analog converter structural representation of the embodiment of the invention
Fig. 5 is the current steering digital-to-analog converter one concrete scene schematic diagram of the embodiment of the invention;
Fig. 6 is the transistorized grid level rollback point of a current supply switch SPICE simulation waveform comparison diagram in the current steering digital-to-analog converter of the current steering digital-to-analog converter of the embodiment of the invention and prior art;
Fig. 7 is a current source node voltage SPICE simulation waveform comparison diagram in the current steering digital-to-analog converter of the current steering digital-to-analog converter of the embodiment of the invention and prior art.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
The current steering digital-to-analog converter of the embodiment of the invention comprises driving buffer and current source.
Driving buffer further comprises:
First input end is used to import first digital signal.
Second input is used to import second digital signal.
First inverter by a PMOS transistor and first nmos pass transistor and the first transistor constitute is used for first digital signal is carried out anti-phase processing, obtains first control signal.
Second inverter by the 2nd PMOS transistor and second nmos pass transistor and transistor seconds constitute is used for second digital signal is carried out anti-phase processing, obtains second control signal.
The high voltage input is used for importing the high voltage of keeping the work of driving buffer transistor.
The low-voltage input is used for importing the low-voltage of keeping the work of driving buffer transistor.
Wherein, during digital to analog converter work, the level of the digital signal of first input end and the input of second input is opposite, for example: when first digital signal was 0 (low level), second digital signal was 1 (high level), when first digital signal is 1 (high level), second digital signal is 0 (low level), and the saltus step simultaneously of two digital input signals, promptly first digital signal is 1 o'clock by 0 saltus step, corresponding second digital signal is 0 by 1 saltus step.
After first inverter and second inverter carried out anti-phase processing with the digital signal of input, the level of the control signal that obtains was opposite with the level of input signal.
PMOS transistor conducting when its grid level is low level in the inverter, its grid level are turn-offed during for high level, and NMOS is then opposite, turn-off conducting when its grid level is high level at its grid level during for low level.
The first transistor and transistor seconds are the transistor of same kind, can be PMOS transistor or nmos pass transistor, its type is by transistorized type decided in the current source, when current source is made of the PMOS transistor, the first transistor and transistor seconds are the PMOS transistor, when current source was made of nmos pass transistor, the first transistor and transistor seconds were nmos pass transistor.
Above-mentioned current source further comprises:
First switching transistor, second switch transistor, first output, second output and bias voltage input and the 3rd switching transistor.
First switching transistor, second switch transistor and the 3rd switching transistor are the transistor of same kind, can be PMOS transistor or nmos pass transistor.
When first switching transistor, second switch transistor and the 3rd switching transistor are the PMOS transistor, accordingly, the first transistor in the inverter and transistor seconds also are the PMOS transistor, a current steering digital-to-analog converter of the embodiment of the invention as shown in Figure 3:
The annexation of element is in the above-mentioned driving buffer:
The transistorized grid of the one PMOS is connected with first input end, and source electrode is connected with the high voltage input, and drain electrode is connected with the source electrode of the first transistor;
The grid of first nmos pass transistor is connected with first input end, and source electrode is connected with the low-voltage input, and drain electrode is connected with the drain electrode of the first transistor and the grid of first switching transistor;
The transistorized grid of the 2nd PMOS is connected with second input, and source electrode is connected with the high voltage input, and drain electrode is connected with the source electrode of transistor seconds;
The grid of second nmos pass transistor is connected with second input, and source electrode is connected with the low-voltage input, and drain electrode is connected with the transistorized grid of second switch with the drain electrode of transistor seconds;
The grid of the first transistor is connected with the transistorized grid of second switch;
The grid of transistor seconds is connected with the grid of first switching transistor.
The annexation of element is in the above-mentioned current source:
The grid of first switching transistor is connected with the drain electrode of first nmos pass transistor, and is connected with the grid of transistor seconds, and source electrode is connected with the drain electrode of the 3rd switching transistor, and drain electrode is connected with first output.
The transistorized grid of second switch is connected with the drain electrode of second nmos pass transistor, and is connected with the grid of the first transistor, and source electrode is connected with the drain electrode of the 3rd switching transistor, and drain electrode is connected with second output.
Current source also comprises:
The high voltage input is used for importing the high voltage of keeping the work of current source transistor.
Above-mentioned bias voltage input is used for input offset voltage, by the bias of this bias voltage, makes the constant electric current of generation between the high voltage input and first switching transistor and the second switch transistor node voltage.During digital to analog converter work, the 3rd switching transistor that is connected with the bias voltage input is in conducting state always.
When the first switching transistor conducting, the electric current that produces between high voltage input and the node voltage is exported from first output, and when the second switch transistor turns, the electric current that produces between high voltage input and the node voltage is exported from second output.
When the current steering digital-to-analog converter among Fig. 3 is worked:
Conducting when first switching transistor is low level at the level of first control signal is turn-offed during for high level at the level of first control signal;
Conducting when the second switch transistor is low level at the level of second control signal is turn-offed during for high level at the level of second control signal;
Conducting when the first transistor is lower than first predetermined level at the level of second control signal is turn-offed when the level of second control signal is higher than first predetermined level;
Conducting when transistor seconds is lower than second predetermined level at the level of first control signal is turn-offed when the level of first control signal is higher than second predetermined level.
Above-mentioned first predetermined level is mainly determined by the size of the first transistor, first nmos pass transistor; Second predetermined level is mainly determined by the size of the transistor seconds and second nmos pass transistor.
When first inverter and second inverter were the inverter of same type, promptly during the counter element in first inverter and second inverter measure-alike, first predetermined level equated with second predetermined level.
When first switching transistor, second switch transistor and the 3rd switching transistor are nmos pass transistor, accordingly, the first transistor in the inverter and transistor seconds also are nmos pass transistor, another current steering digital-to-analog converter of the embodiment of the invention as shown in Figure 4:
The annexation of element is in the above-mentioned driving buffer:
The transistorized grid of the one PMOS is connected with first input end, and source electrode is connected with the high voltage input, and drain electrode is connected with the drain electrode of the first transistor and the grid of first switching transistor;
The grid of first nmos pass transistor is connected with first input end, and source electrode is connected with the low-voltage input, and drain electrode is connected with the source electrode of the first transistor;
The transistorized grid of the 2nd PMOS is connected with second input, and source electrode is connected with the high voltage input, and drain electrode is connected with the transistorized grid of second switch with the drain electrode of transistor seconds;
The grid of second nmos pass transistor is connected with second input, and source electrode is connected with the low-voltage input, and drain electrode is connected with the source electrode of transistor seconds;
The grid of the first transistor is connected with the transistorized grid of second switch;
The grid of transistor seconds is connected with the grid of first switching transistor.
The annexation of element is in the above-mentioned current source:
The grid of first switching transistor is connected with a PMOS transistor drain, and is connected with the grid of transistor seconds, and source electrode is connected with the drain electrode of the 3rd switching transistor, and drain electrode is connected with first output.
The transistorized grid of second switch is connected with the 2nd PMOS transistor drain, and is connected with the grid of the first transistor, and source electrode is connected with the drain electrode of the 3rd switching transistor, and drain electrode is connected with second output.
Current source also comprises:
The low-voltage input is used for importing the low-voltage of keeping the work of current source transistor.
Above-mentioned bias voltage input is used for input offset voltage, by the bias of this bias voltage, makes the constant electric current of generation between the low-voltage input and first switching transistor and the second switch transistor node voltage.During digital to analog converter work, the 3rd switching transistor that is connected with the bias voltage input is in conducting state always.
When the first switching transistor conducting, the electric current that produces between low-voltage input and the node voltage is exported from first output, and when the second switch transistor turns, the electric current that produces between height voltage input end and the node voltage is exported from second output.
When the current steering digital-to-analog converter among Fig. 4 is worked:
First switching transistor turn-offs conducting when the level of first control signal is high level at the level of first control signal during for low level;
The second switch transistor turn-offs conducting when the level of second control signal is high level at the level of second control signal during for low level;
The first transistor turn-offs when the level of second control signal is lower than first predetermined level, conducting when the level of second control signal is higher than first predetermined level;
Transistor seconds turn-offs when the level of first control signal is lower than second predetermined level, conducting when the level of first control signal is higher than second predetermined level.
Above-mentioned first predetermined level is mainly by the first transistor, the transistorized size decision of a PMOS; Second predetermined level is mainly by transistor seconds and the transistorized size decision of the 2nd PMOS.
When first inverter and second inverter were the inverter of same type, promptly during the counter element in first inverter and second inverter measure-alike, first predetermined level equated with second predetermined level.
The current steering digital-to-analog converter that provides by the foregoing description, make that the grid control signal of two switching transistors in Control current source is checked and balance, avoided two grid control signals to be the situation of high level simultaneously, thereby the situation that two switches having avoided current source turn-off simultaneously takes place, reduce the energy of the burr of the fluctuating range of node voltage of current supply switch and output signal, realized the optimization of current steering digital-to-analog converter dynamic property.
Be illustrated in figure 5 as a concrete scene schematic diagram of the current steering digital-to-analog converter of the embodiment of the invention, this current steering digital-to-analog converter comprises driving buffer 3 and current source 2, driving buffer 3 further comprises: first input end 11, second input 12, first inverter that is made of PMOS transistor 13, nmos pass transistor 14 and the first transistor 31, second inverter that is made of PMOS transistor 15, nmos pass transistor 16 and transistor seconds 32; Current source 2 further comprises: first switching transistor 21, second switch transistor 22, first output 23, second output 24, bias voltage input 25 and the 3rd switching transistor 26.
Wherein, the element in the current source 2 is the PMOS transistor, and the first transistor 31 and transistor seconds 32 also are the PMOS transistor.
The annexation of element is consistent in the current steering digital-to-analog converter of describing among the annexation of above element and above-mentioned Fig. 3, is not described in detail in this.
Among Fig. 5, SEL and SEL_N represent the digital signal of first input end 11 and 12 inputs of second input respectively, and Vg and Vgn are two transistorized grid levels of current supply switch, and Vhigh and Vlow are the voltage of keeping transistor operate as normal in the digital to analog converter.
The level of supposing the digital signal of current input is: SEL=0, and SEL_N=1 handles the opposite level of back output through inverter: Vg=1, Vgn=0;
When the digital input signals saltus step is SEL=1 and SEL_N=0, at this moment, the first nmos pass transistor conducting in first inverter, Vg changes to low level from high level;
Before Vg is lower than second predetermined level, transistor seconds 32 can conducting, though the 2nd PMOS in second inverter manages conducting, but not conducting of transistor seconds 32, therefore Vgn still is a low level, be that Vgn can not become high level prior to Vg, this has just been avoided Vg and Vgn to be high level simultaneously, thereby the situation that causes two current supply switchs to turn-off simultaneously takes place;
After in case Vg is lower than second predetermined level, transistor seconds 32 conductings; After transistor seconds 32 conductings, impel the Vgn level to raise, when Vgn is elevated to first predetermined level, further controls the first transistor 31 again and turn-off, impel Vg to become low level rapidly, be presented as a positive feedback effect.
Wherein, mainly by the size decision of the first transistor 31 and first nmos pass transistor 14, second predetermined level is mainly determined by the size of the transistor seconds 32 and second nmos pass transistor 16 first predetermined level.
Is SEL=0 for digital input signals from SEL=1 and SEL_N=0 saltus step, and the situation of SEL_N=1 is similar with the course of work of foregoing description, is not described in detail in this.
Current source in the foregoing description is made of the PMOS transistor, certainly also be applicable to the current source that nmos pass transistor constitutes, when current source is made of nmos pass transistor, the first transistor and the transistor seconds that drive the buffer introducing are the NMOS serial transistor, the annexation of element is consistent in the current steering digital-to-analog converter of describing among the annexation of element and above-mentioned Fig. 4 in the digital to analog converter, is not described in detail in this.
Fig. 6 is the transistorized grid level rollback point of a current supply switch SPICE simulation waveform comparison diagram in the current steering digital-to-analog converter of the current steering digital-to-analog converter of the embodiment of the invention and prior art, wherein, (a) is the transistorized grid level rollback point of the current steering digital-to-analog converter current supply switch SPICE simulation waveform figure of prior art among Fig. 6, (b) is the transistorized grid level rollback point of the current steering digital-to-analog converter current supply switch SPICE simulation waveform figure of the embodiment of the invention among Fig. 6, as can be seen from the figure, the rollback point of grid level and comparing of prior art of two switching transistors in Control current source of the embodiment of the invention, occur significantly descending, therefore, the current steering digital-to-analog converter of the provable embodiment of the invention can reduce the situation generation that two switching transistors turn-off simultaneously.
Fig. 7 is a current source node voltage SPICE simulation waveform comparison diagram in the current steering digital-to-analog converter of the current steering digital-to-analog converter of the embodiment of the invention and prior art, wherein, (a) is current source node voltage SPICE simulation waveform figure in the current steering digital-to-analog converter of prior art among Fig. 7, (b) is current source node voltage SPICE simulation waveform figure in the current steering digital-to-analog converter of the embodiment of the invention among Fig. 7, as can be seen from the figure, the fluctuating range of current source node voltage (Vx) surpasses 0.6V in the prior art, and only is about 0.2V in the embodiment of the invention.In addition, also there is the 0.1V fluctuation of negative sense in node voltage of the present invention, can offset burr (Glitch) energy of forward, has reached the purpose that reduces total burr (Glitch) energy on the general effect, has improved the current steering digital-to-analog converter dynamic property.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. a current steering digital-to-analog converter comprises driving buffer and current source, and described current source further comprises: first switching transistor and second switch transistor is characterized in that described driving buffer further comprises:
First input end is used to import first digital signal;
By first inverter that a PMOS transistor, first nmos pass transistor and the first transistor constitute, be used for described first digital signal is carried out anti-phase processing first control signal of controlled described first switching transistor;
The transistorized grid of a described PMOS is connected with described first input end, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the source electrode of described the first transistor;
The grid of described first nmos pass transistor is connected with described first input end, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the drain electrode of described the first transistor and the grid of described first switching transistor;
Second input is used to import second digital signal;
By second inverter that the 2nd PMOS transistor, second nmos pass transistor and transistor seconds constitute, be used for described second digital signal is carried out anti-phase processing transistorized second control signal of controlled described second switch;
The transistorized grid of described the 2nd PMOS is connected with described second input, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the source electrode of described transistor seconds;
The grid of described second nmos pass transistor is connected with described second input, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the transistorized grid of described second switch with the drain electrode of described transistor seconds;
The grid of described the first transistor is connected with the transistorized grid of described second switch;
The grid of described transistor seconds is connected with the grid of described first switching transistor;
Described first switching transistor, described second switch transistor, described the first transistor and described transistor seconds are the PMOS transistor.
2. current steering digital-to-analog converter according to claim 1 is characterized in that:
Conducting when described the first transistor is lower than first predetermined level at the level of described second control signal is turn-offed when the level of described second control signal is higher than described first predetermined level;
Conducting when described transistor seconds is lower than second predetermined level at the level of described first control signal is turn-offed when the level of described first control signal is higher than described second predetermined level.
3. current steering digital-to-analog converter according to claim 2 is characterized in that:
Described first predetermined level is by the size decision of described the first transistor, described first nmos pass transistor;
Described second predetermined level is by the size decision of described transistor seconds and described second nmos pass transistor.
4. current steering digital-to-analog converter according to claim 3 is characterized in that, described first predetermined level equates with described second predetermined level.
5. a current steering digital-to-analog converter comprises driving buffer and current source, and described current source further comprises: first switching transistor and second switch transistor is characterized in that described driving buffer further comprises:
First input end is used to import first digital signal;
By first inverter that a PMOS transistor, first nmos pass transistor and the first transistor constitute, be used for described first digital signal is carried out anti-phase processing first control signal of controlled described first switching transistor;
The transistorized grid of a described PMOS is connected with described first input end, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the drain electrode of described the first transistor and the grid of described first switching transistor;
The grid of described first nmos pass transistor is connected with described first input end, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the source electrode of described the first transistor;
Second input is used to import second digital signal;
By second inverter that the 2nd PMOS transistor, second nmos pass transistor and transistor seconds constitute, be used for described second digital signal is carried out anti-phase processing transistorized second control signal of controlled described second switch;
The transistorized grid of described the 2nd PMOS is connected with described second input, and source electrode is connected with the high voltage of keeping its work, and drain electrode is connected with the transistorized grid of described second switch with the drain electrode of described transistor seconds;
The grid of described second nmos pass transistor is connected with described second input, and source electrode is connected with the low-voltage of keeping its work, and drain electrode is connected with the source electrode of described transistor seconds;
The grid of described the first transistor is connected with the transistorized grid of described second switch;
The grid of described transistor seconds is connected with the grid of described first switching transistor;
Described first switching transistor, described second switch transistor, described the first transistor and described transistor seconds are nmos pass transistor.
6. current steering digital-to-analog converter according to claim 5 is characterized in that:
Described the first transistor turn-offs when the level of described second control signal is lower than first predetermined level, conducting when the level of described second control signal is higher than described first predetermined level;
Described transistor seconds turn-offs when the level of described first control signal is lower than second predetermined level, conducting when the level of described first control signal is higher than described second predetermined level.
7. current steering digital-to-analog converter according to claim 6 is characterized in that:
Described first predetermined level is by described the first transistor, the transistorized size decision of a described PMOS;
Described second predetermined level is by described transistor seconds and the transistorized size decision of described the 2nd PMOS.
8. current steering digital-to-analog converter according to claim 7 is characterized in that, described first predetermined level equates with described second predetermined level.
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| CN2008101121826A CN101588179B (en) | 2008-05-21 | 2008-05-21 | Current steering digital-to-analog converter |
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| CN2008101121826A CN101588179B (en) | 2008-05-21 | 2008-05-21 | Current steering digital-to-analog converter |
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| CN101588179B true CN101588179B (en) | 2011-08-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142841A (en) * | 2010-12-23 | 2011-08-03 | 上海贝岭股份有限公司 | Current source switching circuit for current rudder digital/analog converter |
| CN103023508B (en) * | 2012-12-25 | 2015-12-02 | 北方工业大学 | Current source unit circuit of current steering type digital-to-analog converter |
| US8723712B1 (en) * | 2013-01-16 | 2014-05-13 | Freescale Semiconductor, Inc. | Digital to analog converter with current steering source for reduced glitch energy error |
| CN105187062B (en) * | 2015-09-07 | 2018-05-25 | 浪潮(北京)电子信息产业有限公司 | A kind of digital analog converter |
| CN108933607B (en) * | 2017-05-24 | 2020-08-25 | 华为技术有限公司 | Radio frequency transmitter |
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| US5420529A (en) * | 1994-05-19 | 1995-05-30 | Northern Telecom Limited | Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals |
| WO1996021274A1 (en) * | 1995-01-05 | 1996-07-11 | Cirrus Logic, Inc. | Low power high speed cmos current switching circuit |
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| US5420529A (en) * | 1994-05-19 | 1995-05-30 | Northern Telecom Limited | Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals |
| WO1996021274A1 (en) * | 1995-01-05 | 1996-07-11 | Cirrus Logic, Inc. | Low power high speed cmos current switching circuit |
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| CN101588179A (en) | 2009-11-25 |
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