CN102082506B

CN102082506B - Clock frequency selection circuit suitable for switching power converter

Info

Publication number: CN102082506B
Application number: CN 201010600611
Authority: CN
Inventors: 王科军; 李文宏; 宫艳
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2010-12-22
Filing date: 2010-12-22
Publication date: 2012-12-12
Anticipated expiration: 2030-12-22
Also published as: CN102082506A

Abstract

The invention belongs to the technical field of integrated circuits, in particular relates to a clock frequency selection circuit suitable for a switching power converter. The clock frequency selection circuit comprises two comparators, a finite state machine (FSM) and two multiplexers. The clock frequency selection circuit is applied to a switching power direct-current (DC)/DC converter, and has the advantages that the comparators are not required to increase and the encoding of the FSM is modified only so that multiple alternative frequencies can be selected freely, thus reducing the statical power consumption of a system and improving the system efficiency of the switching power converter.

Description

The clock frequency that is applicable to switch power converter is selected circuit

Technical field

The invention belongs to technical field of integrated circuits, a kind of clock frequency that is specifically related to is selected circuit, is mainly used in the Switching Power Supply DC/DC transducer.

Background technology

Switching Power Supply DC/DC transducer is one type and uses inductance or electric capacity as the medium of power transfer, through periodic clock pulse control, realizes a kind of circuit that level transforms.It is widely used in all kinds of consumer products.It is for the linear rectifier LDO of no switch, and biggest advantage is exactly a high efficiency.Therefore the raising problem of efficient also is the problem of paying close attention to the most in the switch power converter R&D process.

Generally, determine the length of all kinds of consumption electronic product stand-by times, often the power supply conversion efficiency during standby.Efficient during for underloading, a solution are according to the suitable switching frequency of the interval selection of current loading, to reduce the loss that discharges and recharges of switching tube gate capacitance.This just needs a kind of clock frequency to select circuit to accomplish this function.Traditional frequency selective network is as shown in Figure 1, and (V1 ~ V6) makees the switch clock that the digital coding that relatively obtains is selected CF through sampled voltage VSENSE that current sample is fed back and some threshold voltages for it.This method is simple; But maximum shortcoming is that it needs several comparators to realize; If select N frequency just to need N comparator at least, we know that comparator has certain quiescent dissipation, if alternative frequency is more; Will produce bigger quiescent dissipation so, the efficient when influencing system's underloading greatly.Therefore the present invention proposes a new frequency selective network, the clock of what alternative frequencies no matter, it only needs two comparators and some digital circuits just can realize.Greatly reduce system loss.

Summary of the invention

The clock frequency that the objective of the invention is to propose a kind ofly can to reduce quiescent dissipation in the Switching Power Supply DC/DC transducer, improves the efficient of system is selected circuit.

The clock frequency that the present invention proposes is selected circuit; As shown in Figure 2, mainly comprise two comparator C omp1 and Comp2, a finite state machine FSM; Two multiplexers, these two multiplexers provide threshold voltage V1, V2 respectively ... VN and alternative frequency FS1, FS2 ... FSN.

The sampled voltage Vsense that current sampling circuit feeds back and two high low voltage threshold Vthp, Vthn do comparison will occur below several kinds of situation.If Vsense>Vthp, A1A0=11.Think so the switching frequency FS that chooses and two threshold voltage vt hp, Vthn is on the low side, finite state machine moves to higher state, switching frequency FS uprises, threshold voltage vt hp, Vthn become big.If Vsense is < Vthn, A1A0=00.Think that so the switching frequency FS that chooses and two threshold voltage vt hp, Vthn are higher, finite state machine moves to lower state, switching frequency FS step-down, and threshold voltage vt hp, Vthn diminish.Have only Vthn Vsense during Vthp, A1A0=01.Think this time and choose the clock frequency that is complementary with the Vsense sampled voltage.Frequency selective network is in stable state.It is constant that the FSM state machine is kept state.Thereby reach the purpose that clock frequency is selected.

Adopt traditional frequency selective network, comparator is more, and quiescent dissipation is bigger, the system effectiveness when greatly reducing underloading.Frequency selective network of the present invention only needs two comparators just can realize the selection of a clock frequency arbitrarily, greatly reduces static power consumption, has improved the conversion efficiency of power supply.

Description of drawings

The frequency selective network that Fig. 1 is traditional.

Fig. 2 frequency selective network structure of the present invention.

Fig. 3 finite state machine transition diagram.

Fig. 4 selects frequency transfer process figure from high to low.

Fig. 5 selects frequency transfer process figure from low to high.

Embodiment

6 alternative frequencies below in conjunction with in the state table of comparisons are done further explanation to the present invention.Here selected V1=62.5mV, V2=125mV, V3=250mV, V4=250mV, V5=500mV, V6=1V, V7=5V (VDD).

< during Vthn, the output encoder of two comparators is A1A0=00 as sampled voltage Vsense.This coding is as the input code of finite state machine FSM.When the rising edge of switch clock triggers finite state machine; Can see from the state transition graph of the finite state machine of Fig. 3; During A1A0=00; State can move one to lower state, and the state output encoder B2B1B0 of this moment also makes corresponding change, thereby selects switching frequency and threshold voltage under the new state.Sampled voltage Vsense saltus step the time, checks the selection situation of clock frequency in 1.2V ~ 50mV interval.Can be clear that from Fig. 4 when sampled voltage reduced gradually, the clock frequency of choosing was also reducing gradually.

As sampled voltage Vsense>during Vthp, the output code A1A0=11 of comparator.When the rising edge of switch clock triggers finite state machine; Can see from the state conversion figure of the finite state machine of Fig. 3; State can move one to higher state, the conditional code B2B1B0 of this moment, and switching frequency FS and threshold voltage vt hp Vthn make corresponding change.Can be clear that from Fig. 5 when sampled voltage Vsense raise gradually, the frequency of choosing was also increasing gradually.

Have only that < < during Vthp, promptly during A1A0=01, system is in stable state to Vsense as Vthn.The switching frequency of selected appointment.

It should be noted that < < so state of Vthn is A1A0 ≠ 10 for Vsense owing to Vthp can not occur.Therefore A1A0=10 can do any attitude and handle the simplification circuit design in finite state machine.This example has only adopted 6 effective statuses in addition, also has two state S6, and S7 is not used, so no matter what value A1A0 gets in circuit design, all should move to lower state.

The state table of comparisons

Vsense	fsw	State	b2b1b0	Vthp	Vthn
						[V1 V2]	FS1	S0	000	V2	V1
[V2 V3)	FS2	S1	001	V3	V2
						[V3 V4)	FS3	S2	010	V4	V3
[V4 V5)	FS4	S3	011	V5	V4
						[V5 V6)	FS5	S4	100	V6	V5
[V6 V7)	FS6	S5	101	V7	V6

Claims

1. a clock frequency that is applicable to switch power converter is selected circuit; It is characterized in that; Comprise: two comparator C omp1 and Comp2; A finite state machine FSM, two multiplexers, these two multiplexers provide voltage threshold V1, V2 respectively ... VN and alternative clock frequency FS1, FS2 ... FSN; Wherein, the negative input end of comparator C omp1 is connected with the port of first multiplexer, to comparator C omp1 input dynamic electric voltage threshold value Vthp; The negative input end of comparator C omp2 is connected with the port of second multiplexer, to comparator C omp2 input dynamic electric voltage threshold value Vthn; The positive input terminal input sample voltage Vsense of comparator C omp1 and Comp2; The output of comparator C omp1 links to each other with the input control end A1 of finite state machine FSM, and the output of comparator C omp2 links to each other with the input control end A0 of finite state machine FSM; The output BO of finite state machine FSM, B1, B2 link to each other with input b0, b1, the b2 of first multiplexer and second multiplexer respectively successively;

Said two comparators compare sampled voltage Vsense and dynamic electric voltage threshold value Vthp, Vthn; The A1A0 of output code as a result relatively is as the input control code of finite state machine FSM; The moving direction of control FSM: work as A1A0=00; State machine moves to lower state, thereby selects lower clock frequency and lower voltage threshold; A1A0=11, state machine moves to higher state, thereby selects higher clock frequency and higher voltage threshold value; Have only when A1A0=01, state machine is in stable state, and clock frequency and two dynamic electric voltage threshold value Vthp, Vthn are chosen no longer and change, only if new variation takes place sampled voltage; The two-way multiplexer is respectively applied for the selection of the alternative clock frequency of multichannel and the selection of many group voltage thresholds, new clock frequency and voltage threshold that the result of selection is corresponding with finite state machine FSM state.