CN1713362A - Semiconductor packing structure and production thereof - Google Patents
Semiconductor packing structure and production thereof Download PDFInfo
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- CN1713362A CN1713362A CN 200410048752 CN200410048752A CN1713362A CN 1713362 A CN1713362 A CN 1713362A CN 200410048752 CN200410048752 CN 200410048752 CN 200410048752 A CN200410048752 A CN 200410048752A CN 1713362 A CN1713362 A CN 1713362A
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- China
- Prior art keywords
- semiconductor
- packaging
- semiconductor element
- substrate
- syndeton
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The construction of semiconductor encapsulation mainly consists of a baseboard and a semiconductor component connected with base board by using Flip Chip Bonding. A link construction is set between the semiconductor and base board, and extends along with underside of the semiconductor component in order to press the semiconductor component on the base board. The link construction is formed by solidifying sticking agent, and has function of fixing connection and supporting. The method of semiconductor encapsulation is: a semiconductor component is set on base board and is connected with base board by using Flip Chip bonding; the sticking agent is coated along with underside of semiconductor encapsulation; at least one sticking construction is formed between the edge of underside of semiconductor component and base board, and is used to fix the semiconductor component on the base board.
Description
Technical field
The present invention relates to a kind of semiconductor packaging structure and manufacture method thereof.
Background technology
Seeing also shown in Figure 1ly, is the cutaway view of existing known semiconductor packaging structure.Should have known semiconductor packaging structure 100 now, it comprises semiconductor element 102 and is fixed on the substrate 104 to cover brilliant ways of connecting (for example by a plurality of tin balls 108).Has a primer filling (underfill) 106 between this semiconductor element 102 and this substrate 104, increase the mechanical strength of the joint of this semiconductor element 102 and this substrate 104 by this, fixing relative position between the two, therefore follow on for example surface when being subjected to high temperature in the processing procedure when this semiconductor packaging structure 100, be unlikely to disintegration or distortion.
Yet, when this semiconductor packaging structure 100 is subjected to high temperature, the pollutant on the aqueous vapor that contains in this primer filling 106 or this semiconductor element 102 and substrate 104 surfaces can volatilize, expand and produce the cavity in this primer filling 106, even this primer filling 106 is peeled off.In addition, aforesaid aqueous vapor and pollutant still are covered by in this primer filling 106 after being subjected to high heat volatilization can't spill into the external world, very and after temperature decline, can condense in and cause tin ball 108 bridge joints and short circuit on the tin ball 108.Generally speaking, the space between this semiconductor element 102 and this substrate 104 is very limited, so the injection rate of primer filling is wayward, and the problem of excessive glue is often arranged.
This shows, on above-mentioned conventional semiconductor packages is configured in structure and uses, obviously still have inconvenience and defective, and demand urgently further being improved.In order to solve the problem that semiconductor packaging structure exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the conventional semiconductor packages structure exists, the inventor enriches practical experience and professional knowledge for many years based on being engaged in this type of product design manufacturing, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new semiconductor packaging structure and manufacture method thereof, make it have more practicality.After constantly research, design and improvement, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the conventional semiconductor packages structure exists, and provide a kind of new semiconductor packaging structure, technical problem to be solved is to make it can overcome or improve tin ball bridge joint and the problem of the glue that overflows, and then improve the reliability of semiconductor package, thereby be suitable for practicality more.
Another object of the present invention is to, a kind of new method for packaging semiconductor is provided, technical problem to be solved is to make it can save manufacturing process and man-hour, and then reduces manufacturing cost, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of method for packaging semiconductor that the present invention proposes, it may further comprise the steps: semiconductor element is placed on the substrate; This semiconductor element is connected this substrate to cover brilliant ways of connecting; With the edge coating of an adhesive along this semiconductor wafer package structure bottom surface, at least one adhesive structure of formation between the edge of this semiconductor element bottom surface and this substrate by this; And solidify this adhesive structure, further this semiconductor element is fixed on this substrate by this.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid method for packaging semiconductor, wherein said adhesive structure are to be dots structure.
Aforesaid method for packaging semiconductor, wherein said adhesive structure are to be list structure.
Aforesaid method for packaging semiconductor, wherein said adhesive structure are the whole edges of this semiconductor element bottom surface of sealing.
Aforesaid method for packaging semiconductor, wherein said adhesive structure are the part edges that only is distributed in this semiconductor element bottom surface.
Aforesaid method for packaging semiconductor, wherein said covering comprises a reflow step at brilliant the connection, and the step of this coating binder is to carry out before this covers brilliant Connection Step, and this curing schedule and this reflow step are to carry out simultaneously.
Aforesaid method for packaging semiconductor, wherein said semiconductor element are to be the semiconductor wafer packaging structure.
Aforesaid method for packaging semiconductor, wherein said semiconductor element are to be a wafer size packaging structure.
Aforesaid method for packaging semiconductor, wherein said semiconductor element are to be a wafer.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.According to a kind of semiconductor packaging structure that the present invention proposes, it comprises: a substrate; Semiconductor element is arranged on this substrate to cover brilliant ways of connecting; At least one syndeton is arranged between this semiconductor element and this substrate and only extends in order to this semiconductor element is fixed in this substrate along the edge of this semiconductor wafer package structure bottom surface, and wherein this syndeton is to be formed by an adhesive solidification.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor packaging structure, wherein said syndeton are to be dots structure.
Aforesaid semiconductor packaging structure, wherein said syndeton are to be list structure.
Aforesaid semiconductor packaging structure, wherein said syndeton are the whole edges of this semiconductor wafer package structure bottom surface of sealing.
Aforesaid semiconductor packaging structure, wherein said syndeton are the part edges that only is distributed in this semiconductor wafer package structure bottom surface.
Aforesaid semiconductor packaging structure is to make formed this syndeton have elasticity for a softwood matter glue in order to the adhesive that forms this syndeton wherein.
Aforesaid semiconductor packaging structure, wherein said semiconductor element are to be the semiconductor wafer packaging structure.
Aforesaid semiconductor packaging structure, wherein said semiconductor element are to be a wafer size packaging structure.
Aforesaid semiconductor packaging structure, wherein said semiconductor element are to be a wafer.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention proposes a kind of semiconductor packaging structure, it mainly comprises a substrate and semiconductor element is arranged on this substrate to cover brilliant ways of connecting, wherein this semiconductor element can be a wafer or semiconductor encapsulating structure, for example a wafer size packaging structure.The present invention is characterized in that this semiconductor packaging structure comprises a syndeton and is arranged between this semiconductor element and this substrate and only extends along the edge of this semiconductor element bottom surface, in order to this semiconductor element is fixed in this substrate, wherein this syndeton is to be formed by an adhesive solidification.
Because this syndeton is only to extend along the edge of this semiconductor element bottom surface, therefore the design of this syndeton not only can have function affixed and that support, can also reduce the stress between this semiconductor element and this substrate, make the structure of this packaging structure be unlikely to be subjected to heavily stressed influence and peel off.
This joint construction can comprise dots structure or list structure, and this syndeton can only be distributed in the part edge of this semiconductor element bottom surface, and the aqueous vapor of this semiconductor packaging structure inside and pollutant can be overflowed from the slit between the syndeton at the environment of high temperature.In addition, the whole edge of also salable this semiconductor element bottom surface of this syndeton, and can prevent that aqueous vapor or pollutant from entering this semiconductor packaging structure.
In addition, can make this syndeton also can have absorbing vibration by selecting suitable adhesive (for example softwood matter glue) to form the rubber-like syndeton to protect the function of this semiconductor element.
The present invention provides a kind of method for packaging semiconductor in addition.At first, semiconductor element is arranged on the substrate.Then, to cover brilliant ways of connecting this semiconductor element is connected this substrate.Again with edge coating formation one adhesive structure of an adhesive along the bottom surface of this semiconductor element.At last, solidify this adhesive structure to form this syndeton.
According to one embodiment of the invention, this adhesive application step also can be carried out before covering brilliant Connection Step.In particular, this covers and brilliant the connection comprises a reflow step, with a plurality of tin balls of high temperature reflow, utilizes these a plurality of tin balls that this semiconductor wafer package structure is connected this substrate again.The adhesive that can select the approximate tin ball reflow temperature of curing temperature in this embodiment is in order to form this syndeton, therefore after this adhesive of coating, can solidify this adhesive simultaneously by the high temperature of reflow step, can save manufacturing process and man-hour by this.
Because method provided by the present invention only needs the edge coating of adhesive along the bottom surface of this semiconductor element, and do not need as existing located by prior art, will form primer filling complete filling between this semiconductor element and this substrate, therefore can save the consumption of material, so not only can reduce the problem of the glue that overflows, more can form this syndeton fast, improve production capacity.
In sum, semiconductor packaging structure of the present invention can overcome or improve tin ball bridge joint and the problem of the glue that overflows, and then improves the reliability of semiconductor package.Method for packaging semiconductor of the present invention can be saved manufacturing process and man-hour, and then reduces manufacturing cost.It has above-mentioned plurality of advantages and practical value, and in like product and manufacture method, do not see have similar design to publish or use and really genus innovation, no matter it all has bigger improvement on product structure, manufacture method or function, have technically than much progress, and produced handy and practical effect, and has the multinomial effect of enhancement than the conventional semiconductor packages structure, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by going out a plurality of preferred embodiments, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the cutaway view that has known semiconductor packaging structure now.
Fig. 2 is the cutaway view of the semiconductor packaging structure of one embodiment of the invention.
Fig. 3 is the top view of the semiconductor packaging structure of one embodiment of the invention.
Fig. 4 is the top view of the semiconductor packaging structure of another embodiment of the present invention.
Fig. 5 is the cutaway view of the semiconductor packaging structure of another embodiment of the present invention.
Fig. 6 is the flow chart of the semiconductor packaging structure manufacture method of one embodiment of the invention.
100: semiconductor packaging structure 102: the semiconductor wafer package structure
104: substrate 106: the primer filling
108: tin ball 200: semiconductor packaging structure
204: the second semiconductor elements of 202: the first semiconductor elements
206: substrate 208: semiconductor wafer
210: connecting line 212: syndeton
212a: dots structure 212b: list structure
214: tin ball 500: the semiconductor wafer package structure
502: wafer 504: substrate
602: be provided with 604: cover brilliant the connection
606: coating binder 608: solidify
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to semiconductor packaging structure and its concrete structure of manufacture method, manufacture method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Seeing also shown in Figure 2ly, is the cutaway view of the semiconductor packaging structure of one embodiment of the invention.The semiconductor packaging structure 200 of one embodiment of the invention, it mainly comprises one first semiconductor element 202 and one second semiconductor element 204, and wherein this first semiconductor element 202 and second semiconductor element 204 are all a kind of semiconductor packaging structure.This first semiconductor element 202 comprises a substrate 206, semiconductor wafer 208 is arranged on this substrate 206, and is electrically connected at this substrate 206 by a plurality of connecting lines 210.This second semiconductor element 204 is to be arranged on this substrate 206 to cover brilliant ways of connecting (for example by a plurality of tin balls 214).In the present embodiment, this second semiconductor element 204 is to be a wafer size packaging structure.Has a syndeton 212 between this second semiconductor wafer package structure 204 and this substrate 206.
In the present embodiment, this wafer 208 is for having the wafer of major function, and the wafer 204a that is comprised in this second semiconductor element 204 then has miscellaneous function (for example memory body and fast flash memory bank etc.).Because this semiconductor packaging structure 200 comprises two semiconductor elements 202 and 204, follow in the processing procedure (this packaging structure 200 is connected to a printed circuit board (PCB)) on follow-up surface, these two semiconductor elements 202 and 204 are subjected to displacement because of the influence that is subjected to high temperature easily or separate.For addressing this problem, existing known techniques is to form one deck primer filling (seeing also shown in Figure 1) between this second semiconductor element 204 and this substrate 206, makes this second semiconductor element 204 also can be fixed on this substrate 206 under the environment of high temperature.Yet, the inside configuration of primer filling contains aqueous vapor and pollutant through regular meeting, and therefore when being heated, aqueous vapor in the structure of primer filling and pollutant form bubble easily, make this primer filling structure produce the cavity even peel off, and lose the effect of supporting and connecting; Very and when high temperature was fallen, aqueous vapor and pollutant can condense in and cause tin ball 214 bridge joints and short circuit on the tin ball 214.
Therefore, the invention provides a kind of syndeton 212 that forms by adhesive solidification and replace the existing employed primer filling of known techniques structure.This syndeton 212 is in order to this second semiconductor element 204 is fixed in this substrate 206, and under the environment of high temperature, make between this second semiconductor element 204 and this substrate 206 and be maintained fixed distance in order to support this second semiconductor element 204, be unlikely to Yin Gaowen and produce distortion.Should be noted that, this syndeton 212 is only to extend along the edge of these second semiconductor element, 204 bottom surfaces, but not complete filling is between this second semiconductor element 204 and this substrate 206, therefore the design of syndeton 212 can significantly reduce the combination interface between this syndeton 212 and packaging structure 204 and the substrate 206, can reduce the probability that this generation is peeled off by this.
See also Fig. 3, shown in Figure 4, this joint construction 212 can comprise dots structure 212a or list structure 212b.As shown in Figure 3, this syndeton 212 can only be distributed in the part edge of these second semiconductor element, 204 bottom surfaces, by this when being subjected to high temperature, can overflow from the slit between the syndeton 212 after aqueous vapor between this second semiconductor element 204 and this substrate 206 and the pollutant vaporization, therefore when temperature decline, just can not condense on the tin ball 214 and cause short circuit.As shown in Figure 4, the entire circumference edge of also salable these second semiconductor element, 204 bottom surfaces of this syndeton 212 enters between this second semiconductor element 204 and this substrate 206 to prevent water gas or pollutant.
In addition; this joint construction 212 is to be formed by a kind of adhesive solidification; therefore can make this syndeton 212 have absorbing vibration in addition by selecting suitable adhesive (for example softwood matter glue) to form rubber-like syndeton 212 to protect the function of this second semiconductor element 204.
In addition, seeing also shown in Figure 5ly, is the cutaway view of the semiconductor packaging structure of another embodiment of the present invention.Not single can being used in of joint construction 212 provided by the present invention further is fixed in a wafer packaging construction on the substrate of another packaging structure, also can be used in a wafer 502 with metal coupling further is fixed on the substrate 504.
The present invention also provides a kind of method of making the aforesaid semiconductor packaging structure in addition.Seeing also shown in Figure 6ly, is the flow chart of the semiconductor packaging structure manufacture method of one embodiment of the invention.The method of semiconductor packaging structure according to an embodiment of the invention, its main flow process may further comprise the steps: at first, in step 602, (seeing also Fig. 2, shown in Figure 5) is arranged on this semiconductor element 204 (or wafer 502) on this substrate 206 (or 504) earlier.Then, in step 604, this semiconductor element 204 (or wafer 502) mechanically and electrically is connected this substrate 206 (or 504) to cover brilliant ways of connecting.In step 606, with the edge coating of a suitable adhesive along this semiconductor element 204 (or wafer 502) bottom surface, at least one point-like of formation or the adhesive structure of strip between this semiconductor element 204 (or wafer 502) and substrate 206 (or 504).In step 608, utilize methods such as high temperature, ultraviolet light or electron beam irradiation to solidify this adhesive structure at last to form this syndeton 212.
According to another embodiment of the present invention, this step 604 comprises a reflow step, with a plurality of tin balls 214 of high temperature reflow, utilizes these a plurality of tin balls 214 that this semiconductor wafer package structure 204 is connected this substrate 206 again.This step 606 also can be carried out before step 604.In particular, in this embodiment, the adhesive that can select the approximate tin ball reflow temperature of curing temperature is in order to form this syndeton 212, therefore after earlier this adhesive being coated between this semiconductor element 204 (or wafer 502) and this substrate 206 (or 504), can solidify this adhesive simultaneously by the high temperature that covers in the brilliant reflow step that connects, can save manufacturing process and man-hour by this.
Because method provided by the present invention only needs the edge coating of adhesive along this semiconductor element 204 (or wafer 502) bottom surface, and do not need as existing known techniques, will form primer filling complete filling between this semiconductor element 204 (or wafer 502) and this substrate 206 (or 504), therefore can save the consumption of material, so not only can reduce the problem of the glue that overflows, more can form this syndeton fast to improve production capacity.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of method for packaging semiconductor is characterized in that it may further comprise the steps:
Semiconductor element is placed on the substrate;
This semiconductor element is connected this substrate to cover brilliant ways of connecting;
With the edge coating of an adhesive along this semiconductor wafer package structure bottom surface, at least one adhesive structure of formation between the edge of this semiconductor element bottom surface and this substrate by this; And
Solidify this adhesive structure, further this semiconductor element is fixed on this substrate by this.
2, method for packaging semiconductor according to claim 1 is characterized in that wherein said adhesive structure is to be dots structure.
3, method for packaging semiconductor according to claim 1 is characterized in that wherein said adhesive structure is to be list structure.
4, method for packaging semiconductor according to claim 1 is characterized in that wherein said adhesive structure is the whole edge of this semiconductor element bottom surface of sealing.
5, method for packaging semiconductor according to claim 1 is characterized in that wherein said adhesive structure is the part edge that only is distributed in this semiconductor element bottom surface.
6, method for packaging semiconductor according to claim 1, it is characterized in that wherein said covering comprises a reflow step at brilliant the connection, the step of this coating binder is to carry out before this covers brilliant Connection Step, and this curing schedule and this reflow step are to carry out simultaneously.
7, method for packaging semiconductor according to claim 1 is characterized in that wherein said semiconductor element is to be the semiconductor wafer packaging structure.
8, method for packaging semiconductor according to claim 1 is characterized in that wherein said semiconductor element is to be a wafer size packaging structure.
9, method for packaging semiconductor according to claim 1 is characterized in that wherein said semiconductor element is to be a wafer.
10, a kind of semiconductor packaging structure is characterized in that it comprises:
One substrate;
Semiconductor element is arranged on this substrate to cover brilliant ways of connecting;
At least one syndeton is arranged between this semiconductor element and this substrate and only extends in order to this semiconductor element is fixed in this substrate along the edge of this semiconductor wafer package structure bottom surface, and wherein this syndeton is to be formed by an adhesive solidification.
11, semiconductor packaging structure according to claim 10 is characterized in that wherein said syndeton is to be dots structure.
12, semiconductor packaging structure according to claim 10 is characterized in that wherein said syndeton is to be list structure.
13, semiconductor packaging structure according to claim 10 is characterized in that wherein said syndeton is the whole edge of this semiconductor wafer package structure bottom surface of sealing.
14, semiconductor packaging structure according to claim 10 is characterized in that wherein said syndeton is the part edge that only is distributed in this semiconductor wafer package structure bottom surface.
15, semiconductor packaging structure according to claim 10 is characterized in that being to make formed this syndeton have elasticity for a softwood matter glue in order to the adhesive that forms this syndeton wherein.
16, semiconductor packaging structure according to claim 10 is characterized in that wherein said semiconductor element is to be the semiconductor wafer packaging structure.
17, semiconductor packaging structure according to claim 10 is characterized in that wherein said semiconductor element is to be a wafer size packaging structure.
18, semiconductor packaging structure according to claim 10 is characterized in that wherein said semiconductor element is to be a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100487521A CN100356534C (en) | 2004-06-15 | 2004-06-15 | Semiconductor packing structure and production thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100487521A CN100356534C (en) | 2004-06-15 | 2004-06-15 | Semiconductor packing structure and production thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1713362A true CN1713362A (en) | 2005-12-28 |
| CN100356534C CN100356534C (en) | 2007-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100487521A Active CN100356534C (en) | 2004-06-15 | 2004-06-15 | Semiconductor packing structure and production thereof |
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| CN (1) | CN100356534C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289218A (en) * | 2019-06-18 | 2019-09-27 | 北京猎户星空科技有限公司 | A kind of integrated circuit plate producing process and integrated circuit board |
| CN110335825A (en) * | 2019-05-29 | 2019-10-15 | 宁波芯健半导体有限公司 | A kind of wafer stage chip encapsulation method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2748050C1 (en) * | 2020-08-05 | 2021-05-19 | Общество с ограниченной ответственностью "Маппер" | Method for compensating for inhomogeneity of the etching of silicon jumpers over chip (options) and silicon wafer with distribution of chips according to this method (options) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191952B1 (en) * | 1998-04-28 | 2001-02-20 | International Business Machines Corporation | Compliant surface layer for flip-chip electronic packages and method for forming same |
| US6724091B1 (en) * | 2002-10-24 | 2004-04-20 | Intel Corporation | Flip-chip system and method of making same |
| CN2603509Y (en) * | 2002-11-15 | 2004-02-11 | 威盛电子股份有限公司 | Chip package structure |
-
2004
- 2004-06-15 CN CNB2004100487521A patent/CN100356534C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110335825A (en) * | 2019-05-29 | 2019-10-15 | 宁波芯健半导体有限公司 | A kind of wafer stage chip encapsulation method |
| CN110289218A (en) * | 2019-06-18 | 2019-09-27 | 北京猎户星空科技有限公司 | A kind of integrated circuit plate producing process and integrated circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100356534C (en) | 2007-12-19 |
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