CN1707384A - Main machine board and control method thereof - Google Patents
Main machine board and control method thereof Download PDFInfo
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- CN1707384A CN1707384A CN 200410045288 CN200410045288A CN1707384A CN 1707384 A CN1707384 A CN 1707384A CN 200410045288 CN200410045288 CN 200410045288 CN 200410045288 A CN200410045288 A CN 200410045288A CN 1707384 A CN1707384 A CN 1707384A
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Abstract
The mainboard includes one CPU unit, one chipset and one time sequence and ratio control signal generator module. The chipset has at least one phase locking loop, one CPU unit bus loop and one memory module bus loop connected electrically. The time sequence and ratio control signal generator module generates time sequence and ratio control signal fed to the phase locking loop in relates to chipset, and the phase locking loop re-sets the transmission frequency ratio between the information transmission frequency of the CPU unit bus loop and the information transmission frequency of the memory module bus loop according to the time sequence and ratio control signal.
Description
Technical field
The present invention relates to a kind of motherboard and control method thereof, particularly a kind of constant transmissions frequency proportions relation that is not subject to chipset, and make memory modules can reach the motherboard and the control method thereof of more dynamical information transmission frequency.
Background technology
Along with improvement of computer science, the internal memory of higher clock pulse also is developed success in succession, and the internal memory that is widely used most on the market at present is so-called DDR.The abbreviation of the just double data transmission of DDR (double data rate) is the mainstream standard of PC memory over the years always, and the specification of DDR has reached 400MHz at present, but the internal memory DDR2 of another kind of specification is about to replace present DDR.The specification of DDR2 will be with the 533MHz take-off, and strides forward towards the technology of 667MHz, and higher clock pulse can reach higher data transmission efficiency, improves the usefulness of computing machine, simultaneously also more power saving of DDR2.According to the statistics of Samsung, the power consumption of the DDR2 of 533MHz clock pulse is less than 65% of 400MHz DDR.This also will save the power consumption of notebook computer.But, the present chipset that motherboard adopted on the market, some fixing specification ratio of setting is all arranged, and for example the specification of CPU (central processing unit) is that FSB-800 then complies with the fixedly specification ratio that is set by chipset, and the internal memory that it corresponded to is with a highest standard to be DDR2-533.
Please refer to shown in Figure 1ly, existing motherboard includes a CPU (central processing unit) 11, a chipset 12, a memory modules 13 and a sequential generation module 14.It produces a clock signal CK by sequence generation module 14
0, import CPU (central processing unit) 11 and chipset 12 respectively, CPU (central processing unit) 11 provides a percent information to chipset 12, percent information I
0Be the chipset 12 original specification ratios that set, illustrate, as the specification ratio is 2: 3, the specification of then corresponding with it CPU (central processing unit) 11 and memory modules 13 can be FSB-533 (CPU-bus 133MHz) and DDR2-400 (Memory-bus 200MHz) respectively, again, if specification ratio 5: 6, the specification of then corresponding with it CPU (central processing unit) 11 and memory modules 13 can be FSB-667 (CPU-bus 166MHz) and DDR2-400 (Memory-bus 200MHz) respectively.
From the above, set some fixing use specification ratio because of chipset all has, the usefulness of the memory modules of feasible higher clock pulse is limited, and can't reach the data transmission efficiency that memory modules itself sets.Therefore, how making memory modules can reach more dynamical information transmission frequency, and be not subject to the motherboard of the fixedly specification ratio that chipset sets, is one of important topic of current motherboard in fact.
Summary of the invention
Because above-mentioned problem the objective of the invention is to overcome the deficiencies in the prior art and defective, a kind of fixedly specification ratio that is not subject to chipset is provided, and makes memory modules can reach the motherboard of more dynamical information transmission frequency.
For reaching above-mentioned purpose, the invention provides a kind of motherboard, comprise a CPU (central processing unit), a chipset and a sequential ratio control signal generation module.Chipset, it is provided with a phase-locked loop, a CPU (central processing unit) bus loop at least, reaches a memory modules bus loop, wherein the phase-locked loop is electrically connected with CPU (central processing unit) bus loop and memory modules bus loop respectively, and the CPU (central processing unit) bus loop is electrically connected with CPU (central processing unit); Sequential ratio control signal generation module, be electrically connected on CPU (central processing unit) and chipset respectively, it produces a sequential ratio control signal, the sequential ratio control signal inputs in the phase-locked loop of chipset, and the phase-locked loop resets the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop of CPU (central processing unit) bus loop according to the sequential ratio control signal.
The present invention also provides a kind of motherboard control method in addition, it has a CPU (central processing unit), a chipset to be provided with a phase-locked loop, a CPU (central processing unit) bus loop and a memory modules bus loop at least, comprises one first controlled step, a sequential percent information detects step and one second controlled step.First controlled step, transmit original scale information to one a sequential ratio control signal generation module by CPU (central processing unit), sequential ratio control signal generation module produces a sequential ratio control signal to the phase-locked loop, and the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop of CPU (central processing unit) bus loop is set in the phase-locked loop according to the sequential ratio control signal; The sequential percent information detects step, detects the specification of a memory modules, inputs to sequential ratio control signal generation module to produce a sequential percent information; Second controlled step, produce another sequential ratio control signal to the phase-locked loop by sequential ratio control signal generation module according to the sequential percent information, the phase-locked loop resets the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop of CPU (central processing unit) bus loop according to another sequential ratio control signal.
From the above, because of complying with motherboard of the present invention, change the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop of CPU (central processing unit) bus loop by sequential ratio control signal generation module, therefore can not be subject to the fixedly specification ratio of chipset, and make memory modules can reach more dynamical information transmission frequency.
Description of drawings
Fig. 1 is for showing the partial circuit block schematic diagram of existing motherboard;
Fig. 2 is for showing the partial circuit block schematic diagram according to the motherboard of preferred embodiment of the present invention;
Fig. 3 is for showing the process flow diagram according to the motherboard control method of preferred embodiment of the present invention.
Symbol description among the figure:
11 CPU (central processing unit)
12 chipsets
13 memory modules
14 sequence generation module
I
0Percent information
21 CPU (central processing unit)
22 sequential ratio control signal generation modules
23 chipsets
231 phase-locked loops
232 CPU (central processing unit) bus loops
233 memory modules bus loops
24 sequence generation module
25 memory modules
26 output/input system modules substantially
I
0Original scale information
I
1The sequential percent information
S
1The sequential ratio control signal
CK
0Clock signal
The flow process of 41～44 motherboard control methods
Embodiment
Hereinafter with reference to relevant drawings, the motherboard according to preferred embodiment of the present invention is described, wherein identical assembly will be illustrated with identical reference marks.
Please refer to shown in Figure 2, the motherboard of preferred embodiment of the present invention comprises a CPU (central processing unit) 21, a sequential ratio control signal generation module 22, a chipset 23, a sequential generation module 24, at least one memory modules 25 and an output/input system module 26 substantially.In the present embodiment, chipset 23 is a north bridge chipset, it is provided with a phase-locked loop 231, a CPU (central processing unit) bus loop 232 at least, reaches a memory modules bus loop 233, wherein phase-locked loop 231 is electrically connected with CPU (central processing unit) bus loop 232 and memory modules bus loop 233 respectively, and CPU (central processing unit) bus loop 232 is electrically connected with CPU (central processing unit) 21.
Sequential ratio control signal generation module 22 is electrically connected on CPU (central processing unit) 21 and chipset 23 respectively, and it produces a sequential ratio control signal CK
0, sequential ratio control signal CK
0Input in the phase-locked loop 231 of chipset 23, phase-locked loop 231 is according to sequential ratio control signal CK
0Reset the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop 233 of CPU (central processing unit) bus loop 232.
Sequence generation module 24, it is electrically connected with CPU (central processing unit) 21 and chipset 23 respectively, and produces a clock signal CK
0And input to respectively in CPU (central processing unit) 21 and the chipset 23, in the present embodiment, clock signal CK
0Frequency equal the information transmission frequency of CPU (central processing unit) bus loop 232, in addition, in the present embodiment, the information transmission frequency of memory modules bus loop 233 ratio that equals the information transmission frequency of the information transmission frequency of CPU (central processing unit) bus loop 232 and memory modules bus loop 233 multiply by clock signal CK
0Frequency.
Memory modules 25, it is electrically connected with the memory modules bus loop 233 of chipset 23.
Basic output/input system module 26 is electrically connected with sequential ratio control signal generation module 22, basic output/input system module 26 outputs one sequential percent information I
1To sequential ratio control signal generation module 22, sequential ratio control signal generation module 22 is according to sequential percent information I
1Produce sequential ratio control signal S
1In the present embodiment, more include a ratio table of comparisons and at least one buffer in the sequential ratio control signal generation module 22, at basic output/input system module 26 outputs one sequential percent information I
1During to sequential ratio control signal generation module 22, with sequential percent information I
1Choose pairing sequential ratio control signal S by the ratio table of comparisons
1Be stored in buffer.
For content of the present invention is more readily understood, below will lift an example, with the flow process of explanation according to the motherboard control method of preferred embodiment of the present invention.
Please refer to Fig. 4 and in conjunction with shown in Figure 2, motherboard control method according to preferred embodiment of the present invention, wherein motherboard includes a CPU (central processing unit), 21 1 sequential ratio control signal generation modules 22, reaches a chipset 23, chipset 23 is provided with a phase-locked loop 231, a CPU (central processing unit) bus loop 232 and a memory modules bus loop 233 at least, in the present embodiment, the control method of motherboard comprises following steps:
Produce a clock signal CK by sequence generation module 24
0, import CPU (central processing unit) 21 and chipset 23 respectively, in the present embodiment, clock signal CK
0Be the signal of 166MHz, transmit an original scale information I by CPU (central processing unit) 21 again
0To a sequential ratio control signal generation module 22, so that sequential ratio control signal generation module 22 produces a sequential ratio control signal S
1, in the present embodiment, original scale information I
0It is one 5: 6 signal; With sequential ratio control signal S
1Input in the phase-locked loop 231, so that phase-locked loop 231 is according to sequential ratio control signal S
1Set the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop 233 of CPU (central processing unit) bus loop 232, in the present embodiment, the information transmission frequency of CPU (central processing unit) bus loop 232 was 5: 6 with the ratio of the transmission frequency ratio of the information transmission frequency of memory modules bus loop 233, this moment, CPU (central processing unit) 21 received the signal of 166MHz, therefore be the signal of 200MHz according to its corresponding memory modules 25 of ratio, in the present embodiment, memory modules 25 is the memory modules of DDR2 specification, therefore memory modules 25 is the specification of DDR2-400, then, produce a sequential percent information I
1, in the present embodiment, sequential percent information I
1Be 2: 3 information, it inputs to sequential ratio control signal generation module 22 by basic output/input system module 26, so that sequential ratio control signal generation module 22 is according to sequential percent information I
1Produce another sequential ratio control signal S
1, then, with another sequential ratio control signal S
1Input in the phase-locked loop 231, so that phase-locked loop 231 is according to this another sequential ratio control signal S, reset the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop 233 of CPU (central processing unit) bus loop 232, in the present embodiment, the information transmission frequency of the CPU (central processing unit) bus loop 232 of this moment was 2: 3 with the ratio of the transmission frequency ratio of the information transmission frequency of memory modules bus loop 233, but this moment, CPU (central processing unit) 21 still received 166MHz, therefore be the signal of 250MHz according to its corresponding memory modules 24 of ratio, because of memory modules 25 is the memory modules of DDR2 specification, therefore memory modules 25 can be the specification of DDR2-500, can be operated under the standard frequency situation in CPU (central processing unit) 21, make internal memory surpass the job specifications of DDR2-400.
In sum, change the transmission frequency ratio of information transmission frequency with the information transmission frequency of memory modules bus loop of CPU (central processing unit) bus loop by sequential ratio control signal generation module because of motherboard of the present invention, therefore can not be subject to the fixedly specification ratio of chipset, and make memory modules can reach more dynamical information transmission frequency.
The above only is an illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the scope of claims its equivalent modifications of carrying out or change.
Claims (10)
1, a kind of motherboard is characterized in that, comprises:
One CPU (central processing unit);
One chipset, it is provided with a phase-locked loop, a CPU (central processing unit) bus loop at least, reaches a memory modules bus loop, wherein this phase-locked loop is electrically connected with this CPU (central processing unit) bus loop and this memory modules bus loop respectively, and this CPU (central processing unit) bus loop is electrically connected with this CPU (central processing unit); And
One sequential ratio control signal generation module, be electrically connected on this CPU (central processing unit) and this chipset respectively, it produces a sequential ratio control signal, this sequential ratio control signal inputs in the phase-locked loop of this chipset, and this phase-locked loop resets the transmission frequency ratio of information transmission frequency with the information transmission frequency of this memory modules bus loop of this CPU (central processing unit) bus loop according to this sequential ratio control signal.
2, motherboard as claimed in claim 1, wherein, this motherboard more comprises:
One sequential generation module, it is electrically connected with this CPU (central processing unit) and this chipset respectively, and produces a clock signal and input to respectively in this CPU (central processing unit) and this chipset.
3, motherboard as claimed in claim 2, wherein, the frequency of this clock signal equals the information transmission frequency of this CPU (central processing unit) bus loop.
4, motherboard as claimed in claim 2, wherein, the information transmission frequency of this memory modules bus loop ratio that equals the information transmission frequency of the information transmission frequency of this CPU (central processing unit) bus loop and this memory modules bus loop multiply by the frequency of this clock signal.
5, motherboard as claimed in claim 1, wherein, this motherboard more comprises:
At least one memory modules, it is electrically connected with this memory modules bus loop of this chipset.
6, motherboard as claimed in claim 5, wherein, this memory modules is the memory modules of DDR2 specification.
7, motherboard as claimed in claim 1, wherein, more comprise an output/input system module substantially, should basic output/input system module be electrically connected with this sequential ratio control signal generation module, should basic output/input system module export a sequential percent information to this sequential ratio control signal generation module, this sequential ratio control signal generation module produces this sequential ratio control signal according to this sequential percent information.
8, motherboard as claimed in claim 1, wherein, this chipset is a north bridge chipset.
9, a kind of control method of motherboard, wherein this motherboard includes a CPU (central processing unit), a sequential ratio control signal generation module, reaches a chipset, this chipset is provided with a phase-locked loop, a CPU (central processing unit) bus loop and a memory modules bus loop at least, it is characterized in that the control method of this motherboard comprises following steps:
Transmit original scale information to one a sequential ratio control signal generation module by this CPU (central processing unit), so that this sequential ratio control signal generation module produces a sequential ratio control signal;
This sequential ratio control signal is inputed in this phase-locked loop, so that the transmission frequency ratio of information transmission frequency with the information transmission frequency of this memory modules bus loop of this CPU (central processing unit) bus loop is set in this phase-locked loop according to this sequential ratio control signal;
Produce a sequential percent information, and it is inputed in this sequential ratio control signal generation module, so that this sequential ratio control signal generation module produces another sequential ratio control signal according to this sequential percent information; And
This another sequential ratio control signal is inputed in this phase-locked loop, so that this phase-locked loop resets the transmission frequency ratio of information transmission frequency with the information transmission frequency of this memory modules bus loop of this CPU (central processing unit) bus loop according to this another sequential ratio control signal.
10, motherboard control method as claimed in claim 9, wherein, this motherboard more includes an output/input system module substantially, this sequential percent information by this export substantially/the input system module inputs to this sequential ratio control signal generation module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100452880A CN1329785C (en) | 2004-06-04 | 2004-06-04 | Main machine board and control method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100452880A CN1329785C (en) | 2004-06-04 | 2004-06-04 | Main machine board and control method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1707384A true CN1707384A (en) | 2005-12-14 |
| CN1329785C CN1329785C (en) | 2007-08-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100452880A Expired - Lifetime CN1329785C (en) | 2004-06-04 | 2004-06-04 | Main machine board and control method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576864B (en) * | 2008-05-09 | 2011-10-26 | 华硕电脑股份有限公司 | Computer system and data signal processing method of memory interface thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0119795B1 (en) * | 1994-04-20 | 1997-10-27 | 김광호 | Computer easy for up-grade |
| KR0172001B1 (en) * | 1995-12-05 | 1999-03-30 | 윤종용 | Re-programming apparatus of bios memory |
| CN1164991C (en) * | 2001-02-26 | 2004-09-01 | 微星科技股份有限公司 | Method for instant raising CPU frequency |
| CN1260661C (en) * | 2003-04-09 | 2006-06-21 | 威盛电子股份有限公司 | Computer system with several specification compatibility transmission channels |
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2004
- 2004-06-04 CN CNB2004100452880A patent/CN1329785C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101576864B (en) * | 2008-05-09 | 2011-10-26 | 华硕电脑股份有限公司 | Computer system and data signal processing method of memory interface thereof |
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| CN1329785C (en) | 2007-08-01 |
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