CN100339785C - Multi-section type super frequency mainframe board and control method thereof - Google Patents
Multi-section type super frequency mainframe board and control method thereof Download PDFInfo
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- CN100339785C CN100339785C CNB200410049358XA CN200410049358A CN100339785C CN 100339785 C CN100339785 C CN 100339785C CN B200410049358X A CNB200410049358X A CN B200410049358XA CN 200410049358 A CN200410049358 A CN 200410049358A CN 100339785 C CN100339785 C CN 100339785C
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Abstract
The present invention relates to multi-segment type over-frequency host board which comprises a central processing unit, a chip group and a module for generating time sequence ratio control signals, wherein the central processing unit outputs a time sequence control signal; the chip group is at least provided with a bus loop at the front end and a bus loop of a fast peripheral connecting interface which are electrically connected, and the bus loop at the front end and the central processing unit are electrically connected; the module for generating the time sequence ratio control signals is electrically connected with the chip group which generates a time sequence ratio control signal input into the chip group, and the chip group newly sets the transmission frequency ratio of the information transmission frequency of the bus loop at the front end and the information transmission frequency of the bus loop of a fast peripheral connecting interface by the time sequence ratio control signal.
Description
Technical field
The present invention relates to a kind of multisection type super frequency mainframe board and control method thereof, particularly a kind of avoiding do not caused unsettled multisection type super frequency mainframe board of system and control method thereof because of work schedule matches.
Background technology
Along with improvement of computer science, computing machine comprises CPU, motherboard, internal memory or the like, and is also more and more faster in processing and arithmetic speed, but the fast more product of relative processing speed is reflected at raising also relative on the price.Yet a product is when using, under the considering of many factors, it can't be used the limit at product, in other words, promptly be that product should have better application space, therefore, beginning the someone utilizes the technology of overclocking to make and can and make computer product can bring into play bigger usefulness with lower price.
Please refer to shown in Figure 1, with the motherboard is example, it consists predominantly of a CPU (central processing unit) 11, a sequential generation module 12, a north bridge chipset 13, and north bridge chipset 13 is provided with a Front Side Bus loop 131 at least and a fast peripheral links an interface bus loop 132 and a South Bridge chip group 14.Its action transmits sequence control signal S at least for the moment by CPU (central processing unit) 11
0To sequence generation module 12, and make sequence generation module 12 export the first clock signal CK respectively
0And the second clock signal CK
1The first clock signal CK
0Input to the Front Side Bus loop 131 of CPU (central processing unit) 11 and north bridge chipset 13, and the second clock signal CK
1The fast peripheral of input north bridge chipset 13 links interface bus loop 132 and South Bridge chip group 14.
Existing overlockin can be with the first clock signal CK in the permissible range of CPU (central processing unit) 11
0Frequency improve but need not improve the second clock signal CK
1Frequency, the first clock signal CK for example
0Can be FSB 200, FSB 201, FSB 202 even can being promoted to FSB1200 is that frequency of operation is 300MHz, but the second clock signal CK of this moment
1Still remain under the frequency of operation of PCIE 100, need be along with improving its frequency of operation.
In addition, product before Intel (Intel) 915 (Grantsdale) north bridge chipset and 925 (Alderswood) north bridge chipset, as long as the scope of overclocking is worked under the frequency that CPU (central processing unit) can bear, then as long as with the information transmission frequency overclocking between CPU (central processing unit) and the north bridge chipset, and do not need the information transmission frequency overclocking between the fast peripheral binding interface (S-PCIE-1～SPCIE-n as shown in Figure 1 and N-PCIE) of north bridge chipset and South Bridge chip group and periphery thereof, unsettled situation can not take place in system.Yet, after Intel 915 and 925 north bridge chipset, after overclocking at the first clock signal CK
0And the second clock signal CK
1The ratio of frequency of operation when surpassing certain ratio, then can produce the instability of system.
Recently, the dealer is developed the technology that another kind of overclocking again, please refer to shown in Figure 1ly, and it is with the first clock signal CK in the permissible range of CPU (central processing unit) 11
0Frequency improve simultaneously and improve the second clock signal CK according to a ratio
1Frequency, the first clock signal CK for example
0Can be FSB 133MHz, FSB 137MHz, FSB 140MHz and FSB 150MHz, the second clock signal CK of this moment
1Pairing frequency of operation is PCIE 100MHz or the above frequency of operation of PCIE100MHz.
So, though can solve at the first clock signal CK
0And the second clock signal CK
1The ratio of frequency of operation when surpassing certain ratio, cause work schedule not match, the unsettled situation of meeting generation system, but, this kind mode exists another problem, promptly be that north bridge chipset and South Bridge chip group and peripheral fast peripheral thereof link the information transmission frequency between the interface (S-PCIE-1～SPCIE-n as shown in Figure 1 and N-PCIE), one maximum value is arranged, illustrate, when the value of second clock signal is that PCIE 116MHz is when above, if first clock signal overclocking again is FSB 160MHz, and the value of second clock signal is when continue to promote surpassing PCIE 116MHz, link interface that interface be connected with fast peripheral this moment, and can't mate mutually, and then cause the instability of system at the information transmission frequency in Front Side Bus loop 131 and the transmission frequency ratio that fast peripheral links the information transmission frequency in interface bus loop 132.
From the above, because of after Intel 915 and 925 chipsets, when the ratio of the frequency of operation of first clock signal and second clock signal surpasses certain ratio, cause work schedule not match, the instability of meeting generation system, and computer product can't be brought into play its maximum efficiency.Therefore, how making computer product bring into play its maximum efficiency, is one of important topic of current motherboard overlockin in fact.
Summary of the invention
Because above-mentioned problem the objective of the invention is to overcome the deficiencies in the prior art and defective, provide a kind of avoiding not cause unsettled multisection type super frequency mainframe board of system and control method thereof because of work schedule matches.
For reaching above-mentioned purpose, the invention provides a kind of multisection type super frequency mainframe board, it comprises: a CPU (central processing unit), export a timing control signal; One chipset, it is provided with a Front Side Bus loop at least, reaches fast peripheral binding interface bus loop, and wherein this Front Side Bus loop is electrically connected with this fast peripheral binding interface bus loop, and this Front Side Bus loop is electrically connected with this CPU (central processing unit); One sequential generation module, it is electrically connected on this CPU (central processing unit) and this Front Side Bus loop and this fast peripheral respectively and links the interface bus loop, this sequence generation module is exported one first clock signal and one second clock signal respectively, wherein this first clock signal inputs to this CPU (central processing unit) and this Front Side Bus loop, and this second clock signal inputs to this fast peripheral and links the interface bus loop; One sequential ratio control signal generation module, be electrically connected with this chipset, it produces a sequential ratio control signal, this sequential ratio control signal inputs in this chipset, and this chipset resets the transmission frequency ratio of information transmission frequency with the information transmission frequency in this fast peripheral binding interface bus loop in this Front Side Bus loop according to this sequential ratio control signal; An and output/input system module substantially, be electrically connected with this CPU (central processing unit) and this sequential ratio control signal generation module respectively, should basic output/input system module be to export a sequential information and a sequential percent information respectively, wherein this time sequence information inputs to this CPU (central processing unit), and this sequential percent information inputs to this sequential proportional control signal generation module.
The present invention also discloses a kind of multisection type super frequency mainframe board control method in addition, wherein this multisection type super frequency mainframe board includes a CPU (central processing unit), one sequential generation module, one sequential ratio control signal generation module, an and chipset, this chipset is provided with a Front Side Bus loop at least, one fast peripheral links interface bus loop and an output/input system module substantially, wherein, the control method of this multisection type super frequency mainframe board comprises following steps: by this export substantially/the input system module produces a sequential information and it inputed to this CPU (central processing unit), so that this CPU (central processing unit) transmits a timing control signal to this sequence generation module according to this time sequence information; This sequence generation module produces one first clock signal and one second clock signal according to this timing control signal, and respectively this first clock signal is inputed to this Front Side Bus loop of this CPU (central processing unit) and this chipset, and this fast peripheral that this second clock signal inputs to this chipset is linked interface bus loop; By this export substantially/the input system module produces a sequential percent information, and it is inputed in this sequential ratio control signal generation module, so that this sequential ratio control signal generation module produces a sequential ratio control signal according to this sequential percent information; And this sequential ratio control signal inputed in this chipset, so that this chipset resets this Front Side Bus loop according to this sequential ratio control signal information transmission frequency and this fast peripheral link the transmission frequency ratio of the information transmission frequency in interface bus loop.
From the above, because of complying with multisection type super frequency mainframe board of the present invention, produce a sequential ratio control signal to chipset by sequential ratio control signal generation module, make chipset change the configuration that it is assert according to the sequential ratio control signal, therefore can avoid not matching because of work schedule, and the instability of the system of generation makes computer product bring into play its maximum efficiency.
Description of drawings
Fig. 1 is for showing the synoptic diagram of existing super frequency mainframe board;
Fig. 2 is for showing the synoptic diagram according to the multisection type super frequency mainframe board of preferred embodiment of the present invention;
Fig. 3 is for showing another synoptic diagram according to the multisection type super frequency mainframe board of preferred embodiment of the present invention;
Fig. 4 is for showing the process flow diagram according to the multisection type super frequency mainframe board control method of preferred embodiment of the present invention.
Symbol description among the figure
11 CPU (central processing unit)
12 sequence generation module
13 north bridge chipset
131 Front Side Bus loops
132 fast peripherals link the interface bus loop
14 South Bridge chip groups
S
0Timing control signal
CK
0First clock signal
CK
1Second clock signal
21 CPU (central processing unit)
22 chipsets
221 Front Side Bus loops
222 fast peripherals link the interface bus loop
23 sequential ratio control signal generation modules
24 sequence generation module
25 output/input system modules substantially
26 South Bridge chip groups
S
1Timing control signal
S
2The sequential ratio control signal
CK
2First clock signal
CK
3Second clock signal
I
1Time sequence information
I
2The sequential percent information
Embodiment
Hereinafter with reference to relevant drawings, the multisection type super frequency mainframe board according to preferred embodiment of the present invention is described, wherein components identical will be illustrated with identical reference marks.
Please refer to shown in Figure 2ly, the multisection type super frequency mainframe board of preferred embodiment of the present invention comprises a CPU (central processing unit) 21, a chipset 22, a sequential ratio control signal generation module 23, a sequential generation module 24, an output/input system module 25 substantially.In the present embodiment, CPU (central processing unit) 21 is exported a timing control signal S
1To sequence generation module 24.
Sequential ratio control signal generation module 23 is electrically connected with chipset 22, and it produces a sequential ratio control signal S
2, sequential ratio control signal S
2Input in the chipset 22, chipset 22 is according to sequential ratio control signal S
2Reset the transmission frequency ratio of information transmission frequency with the information transmission frequency in fast peripheral binding interface bus loop 222 in Front Side Bus loop 221.
Basic output/input system module 25 is electrically connected with CPU (central processing unit) 21 and sequential ratio control signal generation module 23 respectively, and basic output/input system module 25 is exported a sequential information I respectively
1An and sequential percent information I
2, in the present embodiment, time sequence information I
1Input to CPU (central processing unit) 21, CPU (central processing unit) 21 is according to time sequence information I
1Produce timing control signal S
1, in addition, sequential percent information I
2Input to sequential ratio control signal generation module 23, sequential ratio control signal generation module 23 is according to sequential percent information I
2Produce sequential ratio control signal S
2In the present embodiment, more include a ratio table of comparisons and at least one buffer in the sequential ratio control signal generation module 23, at basic output/input system module 25 outputs one sequential percent information I
2During to sequential ratio control signal generation module 23, with sequential percent information I
2Choose pairing sequential ratio control signal S by the ratio table of comparisons
2Be stored in the buffer.
In present embodiment, the multisection type super frequency mainframe board of preferred embodiment of the present invention more comprises a South Bridge chip group 26, please refer to shown in Figure 3ly, it links interface bus loop 222 with sequence generation module 24 and fast peripheral respectively and is electrically connected, and by the sequence generation module 24 generations second clock signal CK
3Input to South Bridge chip group 26, and the second clock signal CK
3Frequency equal fast peripheral and link information transmission frequency between interface bus loop 222 and South Bridge chip group 26 and the peripheral fast peripheral binding interface (S-PCIE-1～SPCIE-n as shown in Figure 3 and N-PCIE) thereof.
For content of the present invention is more readily understood, below will lift an example, with the flow process of explanation according to the multisection type super frequency mainframe board control method of preferred embodiment of the present invention.
Please refer to Fig. 4 and arrange in pairs or groups shown in Figure 3, multisection type super frequency mainframe board control method according to preferred embodiment of the present invention, wherein the multisection type super frequency mainframe board includes a CPU (central processing unit) 21, a chipset 22, chipset 22 be provided with at least a Front Side Bus loop 221, and a fast peripheral link interface bus loop 222, a sequential ratio control signal generation module 23, a sequential generation module 24, substantially output/input system module 25, reach a South Bridge chip group 26, the control method of multisection type super frequency mainframe board comprises following steps:
Produce a sequential information I
1And it is inputed to CPU (central processing unit) 21, so that CPU (central processing unit) 21 is according to time sequence information I
1Transmit a timing control signal S
1To sequence generation module 24, time sequence information I
1Export CPU (central processing unit) 21 to by basic output/input system module 25, in the present embodiment, time sequence information I
1Information for FSB 140 specifications.
Produce a sequential percent information I
2, and it is inputed in the sequential ratio control signal generation module 23, so that sequential ratio control signal generation module 23 is according to sequential percent information I
2Produce a sequential ratio control signal S
2, sequential percent information I
2Export sequential ratio control signal generation module 23 to by basic output/input system module 25, in the present embodiment, the sequential ratio control signal is 4: 3 a signal.
With sequential ratio control signal S
2Input in the chipset 22, so that chipset 22 is according to sequential ratio control signal S
2Reset the transmission frequency ratio of information transmission frequency with the information transmission frequency in fast peripheral binding interface bus loop 22 in Front Side Bus loop 221, in the present embodiment, the information transmission frequency in Front Side Bus loop 221 is 4: 3 with the ratio of the transmission frequency ratio of the information transmission frequency in fast peripheral binding interface bus loop 22, and this ratio is the ratio that Intel 915 and Intel 925 chipsets are assert.
In the present embodiment, the first clock signal CK
2For the frequency of FSB 140 specifications equals the information transmission frequency in Front Side Bus loop 221, and the second clock signal CK
3For equaling fast peripheral, the frequency of PCIE 108 specifications links information transmission frequency between interface bus loop 222 and South Bridge chip group 26 and the peripheral fast peripheral binding interface (S-PCIE-1～SPCIE-n as shown in Figure 2 and N-PCIE) thereof.
In addition, in the present embodiment, time sequence information I
1If the information of FSB 170 specifications, then sequential ratio control signal generation module 23 receives another sequential percent information I
2, at this moment, because the specification of PCIE can exceed standard during according to original 4: 3 ratio, therefore, sequential ratio control signal generation module 23 promptly produces another sequential ratio control signal S
2It is 2: 1 signal, and export it to chipset 22,22 information transmission frequencies with Front Side Bus loop 221 of chipset are set at 2: 1 with the transmission frequency ratio that this fast peripheral links the information transmission frequency in interface bus loop 222, then, sequence generation module 24 is exported another first clock signal CK respectively
2Frequency signal and another second clock signal CK for FSB 170 specifications
3For the frequency signal of PCIE 85 specifications, in this, the work schedule of motherboard can mate, and then can not cause the unsettled situation of system that does not match and produced because of work schedule.
From the above, in multisection type super frequency mainframe board control method of the present invention, the first clock signal CK
2Can be FSB 133, FSB 137, FSB 140, FSB 150, FSB 160, FSB170, FSB 180, FSB 190, and the specification of FSB 200 or the like, and second clock signal CK corresponding with it
3Can be PCIE 100, PCIE 100, PCIE 108, PCIE 116, PCIE82.5, PCIE 85, PCIE 90, PCIE 95, and the specification of PCIE 100 or the like.Can observe out by above-mentioned proportionate relationship, before the specification of FSB 150 and PCIE 116, the first clock signal CK
2With the second clock signal CK
3Ratio be about 4: 3, when the specification of FSB arrives FSB 160, its first clock signal CK
2With the second clock signal CK
3Ratio then be converted to 2: 1, make the specification of PCIE still in standard.Certainly, the first clock signal CK
2With the second clock signal CK
3Proportionate relationship also can do suitable adjustment with actual conditions.
In sum, because of multisection type super frequency mainframe board of the present invention and control method thereof according to time sequence information given specification export needed clock signal, increase by a sequential ratio control signal generation module in addition, the ratio configuration that the setting chip group is assert, therefore can avoid not matching because of work schedule, and the instability of the system of generation makes computer product bring into play its maximum efficiency.
The above only is an illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the scope of claims its equivalent modifications of carrying out or change.
Claims (7)
1. a multisection type super frequency mainframe board is characterized in that, comprises:
One CPU (central processing unit) is exported a timing control signal;
One chipset, it is provided with a Front Side Bus loop at least, reaches fast peripheral binding interface bus loop, and wherein this Front Side Bus loop is electrically connected with this fast peripheral binding interface bus loop, and this Front Side Bus loop is electrically connected with this CPU (central processing unit);
One sequential generation module, it is electrically connected on this CPU (central processing unit) and this Front Side Bus loop and this fast peripheral respectively and links the interface bus loop, this sequence generation module is exported one first clock signal and one second clock signal respectively, wherein this first clock signal inputs to this CPU (central processing unit) and this Front Side Bus loop, and this second clock signal inputs to this fast peripheral and links the interface bus loop;
One sequential ratio control signal generation module, be electrically connected with this chipset, it produces a sequential ratio control signal, this sequential ratio control signal inputs in this chipset, and this chipset resets the transmission frequency ratio of information transmission frequency with the information transmission frequency in this fast peripheral binding interface bus loop in this Front Side Bus loop according to this sequential ratio control signal; And
One output/input system module substantially, be electrically connected with this CPU (central processing unit) and this sequential ratio control signal generation module respectively, should basic output/input system module be to export a sequential information and a sequential percent information respectively, wherein this time sequence information inputs to this CPU (central processing unit), and this sequential percent information inputs to this sequential ratio control signal generation module.
2. multisection type super frequency mainframe board as claimed in claim 1, wherein, the frequency of this first clock signal equals the information transmission frequency in this Front Side Bus loop.
3. multisection type super frequency mainframe board as claimed in claim 1, wherein, the frequency of this second clock signal equals the information transmission frequency that this fast peripheral links the interface bus loop.
4. multisection type super frequency mainframe board as claimed in claim 1, wherein, this CPU (central processing unit) produces this timing control signal according to this time sequence information.
5. multisection type super frequency mainframe board as claimed in claim 1, wherein, this sequential ratio control signal generation module produces this sequential ratio control signal according to this sequential percent information.
6. multisection type super frequency mainframe board as claimed in claim 1, wherein, this chipset is a north bridge chipset.
7. multisection type super frequency mainframe board control method, wherein this multisection type super frequency mainframe board includes a CPU (central processing unit), a sequential generation module, a sequential ratio control signal generation module, reaches a chipset, this chipset is provided with a Front Side Bus loop at least, a fast peripheral links interface bus loop and an output/input system module substantially, it is characterized in that the control method of this multisection type super frequency mainframe board comprises following steps:
By this export substantially/the input system module produces a sequential information and it inputed to this CPU (central processing unit), so that this CPU (central processing unit) transmits a timing control signal to this sequence generation module according to this time sequence information;
This sequence generation module produces one first clock signal and one second clock signal according to this timing control signal, and respectively this first clock signal is inputed to this Front Side Bus loop of this CPU (central processing unit) and this chipset, and this fast peripheral that this second clock signal inputs to this chipset is linked interface bus loop;
By this export substantially/the input system module produces a sequential percent information, and it is inputed in this sequential ratio control signal generation module, so that this sequential ratio control signal generation module produces a sequential ratio control signal according to this sequential percent information; And
This sequential ratio control signal is inputed in this chipset, so that this chipset resets the transmission frequency ratio of information transmission frequency with the information transmission frequency in this fast peripheral binding interface bus loop in this Front Side Bus loop according to this sequential ratio control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB200410049358XA CN100339785C (en) | 2004-06-11 | 2004-06-11 | Multi-section type super frequency mainframe board and control method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410049358XA CN100339785C (en) | 2004-06-11 | 2004-06-11 | Multi-section type super frequency mainframe board and control method thereof |
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| CN1707388A CN1707388A (en) | 2005-12-14 |
| CN100339785C true CN100339785C (en) | 2007-09-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6058487A (en) * | 1997-06-06 | 2000-05-02 | Nec Corporation | Period measuring circuit with maximum frequency cutoff |
| CN1294326A (en) * | 1999-10-25 | 2001-05-09 | 威盛电子股份有限公司 | Crystal chip set of computer masterboard referring to different-frequency clocks and its signal processing method |
| US6397343B1 (en) * | 1999-03-19 | 2002-05-28 | Microsoft Corporation | Method and system for dynamic clock frequency adjustment for a graphics subsystem in a computer |
| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
-
2004
- 2004-06-11 CN CNB200410049358XA patent/CN100339785C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6058487A (en) * | 1997-06-06 | 2000-05-02 | Nec Corporation | Period measuring circuit with maximum frequency cutoff |
| US6397343B1 (en) * | 1999-03-19 | 2002-05-28 | Microsoft Corporation | Method and system for dynamic clock frequency adjustment for a graphics subsystem in a computer |
| CN1294326A (en) * | 1999-10-25 | 2001-05-09 | 威盛电子股份有限公司 | Crystal chip set of computer masterboard referring to different-frequency clocks and its signal processing method |
| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
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