CN1684240A - Semiconductor device, method for producing the same, circuit board, and electronic apparatus - Google Patents

Semiconductor device, method for producing the same, circuit board, and electronic apparatus Download PDF

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Publication number
CN1684240A
CN1684240A CNA2005100673214A CN200510067321A CN1684240A CN 1684240 A CN1684240 A CN 1684240A CN A2005100673214 A CNA2005100673214 A CN A2005100673214A CN 200510067321 A CN200510067321 A CN 200510067321A CN 1684240 A CN1684240 A CN 1684240A
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Prior art keywords
substrate
insulating barrier
electrode
forms
semiconductor device
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CN100378939C (en
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宫泽郁也
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Seiko Epson Corp
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Seiko Epson Corp
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract

The invention provides a semiconductor device wherein the warping of a substrate which comes from a difference in stress between the substrate and a functional layer formed on the substrate can be suppressed or removed, and also to provide its manufacturing method, a circuit board, and an electronic apparatus. The method of manufacturing the semiconductor device having an electrode extended through the substrate comprises processes of forming a concave portion in the active surface of the substrate, forming an insulation layer on the active surface of the substrate including the inner surface of the concave portion, removing at least part of the insulation layer formed outside the concave portion, forming the electrode by filling the inside of the concave portion formed with the insulation film by a conductor, and removing the rear face side of the active surface to expose the electrode from the rear face of the active surface.

Description

Semiconductor device and manufacture method thereof, circuit substrate and electronic instrument
Technical field
The present invention relates to manufacture method, circuit substrate and the electronic instrument of semiconductor device and semiconductor device.
Background technology
Personaldata assistance) etc. in mobile phone, notebook personal computer and PDA (personal data appliances: in the portable electronic instrument, be accompanied by miniaturization and light-weighted requirement, attempt to make the inner various electronics miniaturization such as semiconductor chip that are provided with.For example for semiconductor chip, on its packing method, work hard, a kind of so-called CSP can be provided (chip-scale packing: microminiature packing Chip Scale Package) now.The semiconductor chip that adopts the CSP technology to make is because erection space is identical substantially with the area of semiconductor chip, so realized high-density installation.
Therefore, in above-mentioned electronic instrument, the requirement trend of miniaturization and multifunction will day by day be arranged from now on, so need further to improve the packing density of semiconductor chip.Under this background, a kind of three-dimensional mounting technique is proposed in recent years.This three-dimensional mounting technique, to have the semiconductor chip of said function or have a semiconductor chip of difference in functionality stacked mutually, between each semiconductor chip, connect, realize the technology (for example referring to patent documentation 1) of the high-density installation of semiconductor chip with distribution.
Patent documentation: the spy opens the 2001-53218 communique
Yet, on above-mentioned semiconductor chip, form through hole, on this through hole, be formed with electrode, will be electrically connected between the semiconductor chip based on kind electrode, realized above-mentioned three-dimensional mounting technique.And, on the inside face of the active face of this semiconductor chip and through hole, form insulating barrier, and work as the insulation that makes through hole inside with to the diaphragm of the electrode terminal that forms in the semiconductor chip backside side.
But constitute the substrate of above-mentioned semiconductor chip and the insulating barrier that on substrate, forms, its physical constant, promptly thermal coefficient of expansion and internal stress are all inequality.In addition, above-mentioned insulating barrier only forms on the active face of the substrate that forms integrated circuit.Therefore, under the situation of chipization, can produce difference such as internal stress at substrate and between the insulating barrier that forms on the substrate, on substrate, produce stress, make the base plate deformation bending by this stress.The generation of this curved substrate makes the semiconductor chip difficulty that becomes is installed on wiring substrate etc.In addition as mentioned above, under the situation of stacked semiconductor chip on the semiconductor chip (the three-dimensional installation), because active face side or rear side flexural deformation at the substrate of the integrated circuit that forms semiconductor chip, so often be difficult to stacked with semiconductor chip, the electrode of two semiconductor chips be electrically connected or mechanical connection.
Summary of the invention
The present invention In view of the foregoing proposes just, its purpose is, provide a kind of can suppress or eliminate because of substrate and between the functional layer that forms on the substrate stress difference produce the semiconductor device of curved substrate and manufacture method, circuit substrate and the electronic instrument of semiconductor device.
For solving above-mentioned problem, the manufacture method of semiconductor device of the present invention is the manufacture method that possesses the semiconductor device of the electrode that connects substrate, it is characterized in that wherein having successively: the operation that forms recess on the active face of described substrate; On the active face of the described substrate that comprises described recess inside, form the operation of insulating barrier; Remove operation at least a portion of the outside described insulating barrier that forms of described recess; Having formed the described recess inner filling electric conductor of described insulating barrier, to form the operation of described electrode; With the rear side of removing described active face, the operation that described electrode is exposed from the rear side of described active face.
According to this formation, owing to remove the insulating barrier that on the active face of substrate, forms, so can eliminate or reduce the internal stress or the thermal coefficient of expansion of insulating barrier.Can eliminate the internal stress or the thermal coefficient of expansion that act on the insulating barrier on the substrate like this, perhaps reduce the poor of the internal stress of substrate and insulating barrier or thermal coefficient of expansion, thereby can prevent curved substrate.And, mutual when stacked between with semiconductor chip, by between semiconductor chip, importing the bonding agent that contains electrically conductive microparticle, stiffener etc., can guarantee the insulation property between the semiconductor chip.Therefore, even as mentioned above under the situation of removing the insulating barrier that forms on the active face of substrate,, the bonding agent that is imported into etc. can not have problems because playing insulating effect.
And remove in the operation at described insulating barrier, it is characterized in that covering the described insulating barrier of described recess after etching with mask material.
According to this formation, because the masked material of recess covers, prevent by the etching solution etching so can protect at the inner insulating barrier that forms of recess, can avoid removing the inner insulating barrier that forms of recess like this.
Perhaps remove in the operation, preferably under the fast condition of the etching speed of the insulating barrier that the etching speed that makes the insulating barrier that forms on the described substrate forms than the described recess inside at described substrate, carry out comprehensive etching at described insulating barrier.
According to this formation, because the etching speed of the insulating barrier that forms on the substrate is faster than the etching speed of the insulating barrier that the recess inside at substrate forms, so can under the situation that the insulating barrier that recess inside is formed does not exert an influence, remove the insulating barrier that on substrate, forms.And, owing to need not to form the operation of mask material; So can realize the simplification of manufacturing process and shorten manufacturing time.
And the manufacture method of semiconductor device of the present invention, be manufacture method with semiconductor device of the electrode that connects substrate, it is characterized in that wherein having successively: the operation that on the active face of substrate, forms recess; On the active face of the described substrate that comprises described recess inside, form the operation of insulating barrier; Having formed the described recess inner filling electric conductor of described insulating barrier, to form the operation of described electrode; Remove operation at least a portion of the outside described insulating barrier that forms of described recess; With the rear side of removing described active face, the operation that described electrode is exposed from the rear side of described active face.
According to this formation, owing to the insulating barrier that will form on the active face of substrate is removed, so can eliminate or reduce the internal stress or the thermal coefficient of expansion of insulating barrier.Like this, can go out to remove the internal stress or the thermal coefficient of expansion that act on the insulating barrier on the substrate, the internal stress of substrate and insulating barrier or the difference of thermal coefficient of expansion are reduced, it is crooked to prevent that substrate from producing.
And remove in the operation at described insulating barrier, it is characterized in that, cover the described insulating barrier of described recess after etching with mask material.
According to this formation,,, can avoid removing electrode like this by etching so can protect the electrode surface that exposes formation to avoid by the etching solution etching because the masked material of recess covers.
Perhaps remove in the operation, preferably cover described recess, the described insulating barrier of etching with grafting material at described insulating barrier.
Wherein as grafting material, (ACP: anisotropic conductive is stuck with paste: Anisotropic Conductive Paste can to use lead-free solder, anisotropic conductive thickener; Anisotropic conductive film Anisotropic Conductive Film), NCF (non-conductive film: Non Conductive Film) etc. ACF:.These grafting materials are made under the multilayer wired situation at further stacked semiconductor chip on the semiconductor chip, are the materials of two semiconductor chips being realized being electrically connected usefulness.So, owing to adopt grafting material, form operation so can omit the pattern that adopts photolithographic resist as the mask etching insulating barrier.
In addition, semiconductor device of the present invention is the semiconductor device that has formed integrated circuit on the active face of substrate, it is characterized in that wherein possessing: the described substrate that has formed through hole from active face to the rear side of substrate; The insulating barrier that on the internal face of described substrate and described through hole, forms; With the electrode that forms in the inboard of described insulating barrier, exposes from the rear side of described active face, and the thickness of the described insulating barrier that forms on the active face of described substrate, the thickness of the described insulating barrier that forms than the periphery at described electrode is little.
According to this formation, because the insulating barrier that forms on the active face of substrate is littler than the thickness of the insulating barrier that the peripheral part at electrode forms, so not only can prevent the short circuit that causes because of the insulating barrier that forms at the peripheral part of electrode, and can reduce the internal stress or the thermal coefficient of expansion of the insulating barrier that on the active face of substrate, forms.The internal stress of substrate and insulating barrier or the difference of thermal coefficient of expansion are reduced, suppress the bending of substrate.
And the present invention is the semiconductor device that has formed integrated circuit on the active face of substrate, it is characterized in that wherein possessing: the described substrate that has formed through hole from active face to the rear side of described substrate; The insulating barrier that on the internal face of described through hole, forms; With the electrode that forms in the inboard of described insulating barrier, exposes from the rear side of described active face.
According to this formation, because a naked layer or a formation part at least on the active face of substrate, so not only can prevent the short circuit that causes because of insulating barrier that the peripheral part of electrode forms, and can eliminate or alleviate the internal stress or the thermal coefficient of expansion of the insulating barrier that on substrate, forms.It is crooked to prevent that like this substrate from producing.
And circuit substrate of the present invention, it is characterized in that wherein possessing above-mentioned semiconductor device.A kind of circuit substrate with above-mentioned effect can be provided like this.In addition, electronic instrument of the present invention is characterized in that, wherein possesses above-mentioned circuit substrate.Like this, can provide a kind of electronic instrument with above-mentioned effect.
Description of drawings
Fig. 1 is the side cross-sectional view of electrode part in the semiconductor chip that relates to of first kind of execution mode.
Fig. 2 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 3 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 4 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 5 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 6 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 7 is the key diagram of the manufacturing method for semiconductor chips that relates to of first kind of execution mode.
Fig. 8 is the key diagram of the stacked state of semiconductor device that relates to of first kind of execution mode.
Fig. 9 is again the key diagram of distribution.
Figure 10 is again the key diagram of distribution.
Figure 11 is the key diagram of circuit substrate.
Figure 12 is the key diagram of the manufacturing method for semiconductor chips that relates to of second kind of execution mode.
Figure 13 is the key diagram of the manufacturing method for semiconductor chips that relates to of second kind of execution mode.
Figure 14 is the stereogram as the mobile phone of an example of electronic instrument.
Among the figure:
2 ... semiconductor chip, 10 ... substrate, 22 ... dielectric film (insulating barrier), 24 ... basilar memebrane, 26,32 ... resist (mask material), 34 ... electrode, 40 ... solder layer (grafting material)
Embodiment
The following execution mode of using with reference to description of drawings enforcement the present invention.Wherein in each figure of following explanation usefulness, each parts is plotted the engineer's scale that discernible size has suitably changed each parts for making.
[first kind of execution mode]
At first relate to the semiconductor chip as first kind of execution mode of semiconductor device of the present invention with Fig. 1 explanation.Fig. 1 is the side cross-sectional view of the electrode part of the semiconductor chip that relates to of present embodiment.The semiconductor chip 2 that present embodiment relates to possesses: the substrate 10 that has formed integrated circuit; Form the inside of through hole H4 at rear side 10b, by means of the electrode 34 that forms as the dielectric film 22 of first insulating barrier from the active face 10a of substrate 10 to substrate; Dielectric film 26 with conduct second insulating barrier that on the rear side 10b of substrate 10, forms.
(semiconductor device)
In the semiconductor chip 2 shown in Figure 1, go up at the surperficial 10a of the substrate of forming by silicon (elements Si) etc. 10 and to form the integrated circuit (diagram omission) that constitutes by transistor, memory element and other electronic components.On the active face 10a of this substrate 10, form by SiO 2The dielectric film 12 of compositions such as (silicon dioxide).And then forming the interlayer dielectric 14 that waits formation by boron phosphosilicate glass (below be called BPSG) on the surface of this dielectric film 12.The thickness of aforesaid substrate 10 for example is about 625 microns.
On institute's certain portions on these interlayer dielectric 14 surfaces, be formed with electrode pad 16.The ground floor 16a that kind electrode liner 16 will be made up of Ti (titanium) etc. successively, the second layer 16b that forms by TiN (titanium nitride) etc., the 3rd layer of 16c that forms by AlCu (aluminium/copper) etc. and be laminated by the 4th layer of (cover top layer cap) 16d that TiN etc. forms.Wherein the constituent material of electrode pad 16 can suitably change according to electrode pad 16 required electrology characteristic, physical characteristic and chemical characteristics.That is to say, both can use the general electrode pad 16 that adopt, that only form of electrode, also can only form electrode pad 16 with the low Cu of resistance with aluminium as integrated circuit.
Electrode pad 16 is overlooked down at semiconductor chip 2 peripheries and is formed in mode arranged side by side.Wherein electrode pad 16, under situation about forming in mode arranged side by side at semiconductor chip 2 peripheries, often form side by side at central portion simultaneously.Under the situation that periphery forms, (under many situations along both sides or four limits) forms side by side at least along one side of semiconductor chip 2.And each electrode pad 16 is electrically connected in not shown part with above-mentioned integrated circuit.Wherein should be noted that and below electrode pad 16, do not form the integrated circuit this point.
Being formed with passivating film 18 on the surface of interlayer dielectric 14 covers this electrode pad 16.Passivating film 18 is by SiO 2Formation such as (silicon dioxide), SiN (silicon nitride) polyimide resin for example forms 1 micron left and right sides thickness.
And be formed with the peristome H1 of passivating film 18 and the peristome H2 of electrode pad 16 at the central portion of electrode pad 16.Wherein the diameter of the diameter ratio open H1 of portion of peristome H2 is little, for example is set in about 60 microns.And be provided with the opening of same diameter on the 4th layer of 16d in electrode pad 16.On the other hand, on the inner face of the surface of passivating film 18 and peristome H1 and peristome H2, be formed with by SiO 2The dielectric film 20 that (silicon dioxide) is formed.
At the central portion of electrode pad 16, form the H3 of hole portion that dielectric film 20, interlayer dielectric 14, dielectric film 12 and substrate 10 are connected.The diameter of the H3 of hole portion forms to such an extent that the diameter of the H2 of ratio open portion is little, for example about 30 microns.The H3 of its mesopore portion is not limited to overlook rounded, also can form overlook rectangular.Form the through hole H4 that actively connects by peristome H1, peristome H2 and the H3 of hole portion towards rear side from substrate.The degree of depth of this through hole H4 for example is about 70 microns.
Dielectric film 22 forms along the surface, inside of above-mentioned through hole H4.And then the dielectric film 20 that forms at substrate 10 from the surface, inside of through hole H4 extends and is forming.The dielectric film 22 that on above-mentioned dielectric film 20, forms, bigger slightly than the diameter of the peristome H1 of through hole H4, form at the circumference of through hole H4.And other zones become the state that dielectric film 20 is exposed.The dielectric film 20 and the dielectric film 22 that form on the surface of the 3rd layer of 16c of electrode pad 16 are removed a part along the periphery of peristome H2, and electrode pad 16 and electrode 34 are electrically connected.And the rear side 10b of dielectric film 22 from the inner wall surface of above-mentioned through hole H4 towards substrate 10 is outstanding and form, and plays the diaphragm effect when the rear side of substrate 10 forms electrode terminal.In addition, above-mentioned dielectric film 22 is used to prevent what electric current generation leakage and generation etchings such as oxygen and moisture from using, for example forms 1 micron left and right thickness.
Be formed with basilar memebrane 24 on the surface of the 3rd layer of 16c of the electrode pad 16 that exposes and on the surface of residual dielectric film 22 like this.This basilar memebrane 24 is made of the barrier layer that forms on the surface of dielectric film 22 grades (shielded metal) and the inculating crystal layer (seed crystal electrode) that forms on the surface on barrier layer.The barrier layer is to be used to prevent that the constituent material of electrode 34 described later from spreading usefulness to substrate 10, is made up of TiW (tungsten titanium), TiN (titanium nitride), TaN (tantalum nitride) etc.On the other hand, inculating crystal layer is the layer that becomes electrode when forming electrode 34 described later by electroplating processes, is made of Cu, Au, Ag etc.
And be formed with electrode 34 in the inboard of this basilar memebrane 24.Kind electrode 34 is made by Cu and the low electric conducting material of W constant resistance.Wherein if use the electric conducting material of the impurity such as B, P that in polysilicon, mixed to form electrode 34, then owing to needn't prevent to substrate 10 diffusions, so do not need above-mentioned barrier layer.And, form the plug 36 of electrode 34 by on through hole H4, forming electrode 34.Wherein plug 36 and the electrode pad 16 P portion in Fig. 1 is electrically connected by basilar memebrane 24.And expose to the outside lower surface of plug 36.On the other hand, by above passivating film 18, electrode 34 being extended the circumference that is arranged on peristome H1, form the portion of terminal 35 of electrode 34.This portion of terminal 35 is not limited to overlook rounded, and can form rectangle.
In addition, in first kind of execution mode, the end face of the plug 36 of electrode 34 forms outstandingly from the rear side of substrate 10.The projecting height of plug portion 36 for example is set in about 10～20 microns.When stacked a plurality of semiconductor chips, can guarantee the space between the semiconductor chip like this, so easily basilar memebrane etc. is filled in the gap of each semiconductor chip.Wherein by adjusting the projecting height of intercalation part 36, can adjust stacked semiconductor chip interval each other.Even before stacked on the rear side 10b of semiconductor chip 2 coated heat thermosetting resin etc., replace stacked back to fill under the situation of basilar memebrane with this, because the plug portion 36 coated heat thermosetting resins that also can avoid giving prominence to etc. connect so positively carry out the distribution of semiconductor chip.
On the other hand, on the portion of terminal 35 of electrode 34, be formed with solder layer 40 (grafting material).Though this solder layer 40 also can be formed by general PbSn alloy, consider from aspects such as environment, preferably form with lead-free solders such as AgSn alloys.Wherein also can replace solder layer 40, the metal paste bed of material that adopts hard solder (motlten metal) layer made by SnAg alloy etc. or form by Ag thickener etc. as slicken solder.Consider that from environment this hard solder bed of material and the metal paste bed of material also preferably form with lead-free solder.The semiconductor chip 2 that relates in the present embodiment constitutes as above.
(manufacture method)
Below utilize Fig. 2～Fig. 6 that the manufacture method of the semiconductor chip that present embodiment relates to is described.Fig. 2～Fig. 6 is the key diagram of the manufacturing method for semiconductor chips that relates to of present embodiment.Though below be to be that example is illustrated a plurality of semiconductor chips in the semiconductor substrate are formed zone situation about handling simultaneously, also can carry out processing shown below to single semiconductor chip.
At first shown in Fig. 2 (a), on the surface of substrate 10, form dielectric film 12 and interlayer dielectric 14.And on the surface of stacked dielectric film 14, form electrode pad 16.Specifically, at first on all surfaces of stacked dielectric film 14, form successively from the film of four layers of the ground floors to the of electrode pad 16.And the formation of each film all adopts sputtering method to carry out.And then painting erosion resistant agent etc. in its surface.Then utilize photoetching technique the resist pattern to be formed the net shape of electrode pad 16.And carry out etching as mask with the resist that forms through pattern, make electrode pad form the shape that formalizes (for example rectangle), then formation passivating film 18 on electrode pad 16.
Then make passivating film 18 form peristome H1.Its concrete operations are in proper order: painting erosion resistant agent on all surfaces of passivating film at first.Resist both can be photoresists, electron ray resist or X ray resist, also can be eurymeric or negative resist.And the coating of resist can adopt spin-coating method, dip coating or spraying process etc. to carry out.Wherein carry out prebake behind the painting erosion resistant agent.And by with the mask that has formed peristome H1 resist being carried out exposure-processed, and then carry out development treatment, make the resist pattern form the shape of peristome H1.After wherein resist forms through pattern, carry out the back roasting.
And the resist that forms with pattern carries out etching as mask with passivating film 18.And in the present embodiment, also also carry out etching with the 4th layer of electrode pad 16 with passivating film 18.Though Wet-type etching can be also adopted in etching, the preferred dry-etching that adopts.Dry-etching also can be active-ion-etch (RIE:Reactive Ion Ething).Wherein, after forming peristome H1 on the passivating film 18, utilize stripper that the resist on the passivating film 18 is peeled off.By with upper type, shown in Fig. 2 (a), can on passivating film 18, form peristome H1, electrode pad 16 is exposed.
And then shown in Fig. 2 (b), form peristome H2 with respect to electrode pad 16.Its concrete order is: painting erosion resistant agent on all surfaces of electrode pad 16 that exposes and passivating film 18 at first, pattern forms the shape of peristome H2.Then the resist that forms with pattern carries out dry-etching as mask to electrode pad 16.Dry-etching can adopt active-ion-etch.If resist is peeled off, then shown in Fig. 2 (b), can on electrode pad 16, form peristome H2 then.
Shown in Fig. 2 (c), on all surfaces above the substrate 10, form dielectric film 20 then.When this dielectric film 20 adopts dry-etching that the H3 of 10 pairs of hole portions of substrate is bored a hole, has function as mask.Wherein the thickness of dielectric film 20 utilizes the degree of depth at the H3 of hole portion of perforation on the substrate 10 for example to be set in about 2 microns.In the present embodiment, though used SiO 2As dielectric film 20, but, then also can use resist as if the selection ratio of employing with Si.And (Plasma Enhabced Chemial Vapor Deposition: the chemical vapour deposition (CVD) that plasma strengthens) method has formed positive tetraethyl orthosilicate (Tetra Ethyl Ortho Silicate:Si (OC-to utilize PECVD on dielectric film 20 2H 5) 4, below be called TEOS) and be PE-TEOS, perhaps adopt the silica of CVD method formation etc.
Next pattern on dielectric film 20 forms the shape of the hole H3 of portion.Its concrete order is: painting erosion resistant agent on all surfaces of dielectric film 20 at first, pattern forms the shape of peristome H3.Then the resist that forms with pattern carries out dry-etching as mask to dielectric film 20, stacked dielectric film 14 and dielectric film 12.If resist is peeled off, then can on dielectric film 20 grades, form the hole H3 of portion then, substrate 10 is exposed.
And then be etched on the substrate 10 perforation by high speed and dry and form the hole H3 of portion.Wherein can adopt RIE and ICP (Inductively Coupled Plasma: inductive couple plasma) as the dry-etching method.Can adopt dielectric film 20 (SiO this moment as mentioned above 2) as mask, but also can replace dielectric film 20 as mask with resist.The degree of depth of the H3 of its mesopore portion can suitably be selected according to the thickness of the semiconductor chip of final formation.That is to say, semiconductor chip is etched into after the final thickness that the degree of depth of the polyvinyl fluoride hole H3 of portion is set to such an extent that make at the inner electrode tip that forms of the H3 of hole portion and expose on the rear side of substrate 10.Shown in Fig. 2 (c), can on substrate 10, form the H3 of hole portion by the way.And, can form recess H0 from active face to the inside of substrate 10 by means of peristome H1, peristome H2 and the H3 of hole portion.
Then shown in Fig. 3 (a), on the surface of the inner face of recess H0 and dielectric film 20, form dielectric film 22 as first insulating barrier.This dielectric film 22 is for example by PE-TEOS or O 3Compositions such as-TEOS for example are made up of plasma TEOS etc., and surperficial thickness is reached about 1 micron.Then painting erosion resistant agent covers recess H0 on all surfaces of substrate 10.Resist utilizes spin-coating method etc. to be coated with.And the pattern that makes the shape that mask pattern forms greatlyyer than the opening radius H0 of recess H0 to resist irradiation carry out exposure-processed.By development treatment,, the resist pattern of unexposed portion be left behind with the resist of dissolution with solvents exposure portion.That is to say, can form the resist of the shape bigger, the top covering of recess H0 than recess H0 opening radius.
Then dielectric film 22 and dielectric film 20 are carried out anisotropic etching, the part of electrode pad 16 is exposed.And in the present embodiment, a part that makes electrode pad 16 is exposed along the periphery of peristome H2.Its concrete order is, painting erosion resistant agent etc. on whole of dielectric film 22 at first, and the part pattern that will expose forms.Then with the resist that formed by pattern as mask, dielectric film 22 and dielectric film 20 are carried out anisotropic etching.This anisotropic etching should adopt dry-etching methods such as RIE.By forming the state shown in Fig. 3 (a) with upper type.
And then shown in Fig. 3 (b), painting erosion resistant agent 26 on all surfaces of the dielectric film 22 that forms on the substrate 10 covers recess H0.Resist 26 can adopt the whole bag of tricks such as spin-coating method, dip coating or spraying process to be coated with on substrate 10.
Then above-mentioned resist 26 is carried out exposure-processed and development treatment, pattern forms the shape that formalizes.Specifically when exposure-processed, by being set than forming round-shaped as the shape of recess H0, the peristome H0 diameter of recess H0 than 70 microns big masks to resist 26 irradiation light, with above-mentioned pattern transfer.Then in development treatment, the exposure portion with dissolution with solvents is exposed through above-mentioned exposure-processed left behind unexposed portion.Above-mentioned resist 26 heat-treated prebake thereafter.Shown in Fig. 3 (b), can make to form to such an extent that the big resist pattern of the H1 of ratio open portion diameter forms like this.
And then shown in Fig. 4 (a), with having of forming through above-mentioned exposure-processed and development treatment decided pattern resist 25 as mask, carry out dry-etching.Dry-etching adopts the RIE method that can make anisotropic etching to carry out.The RIE device that this dry-etching is used is set under 200W power and the 0.3 torr pressure, carries out etch processes with this understanding.At first, will be as the spike CF of reaction product 430sccm imports in the RIE device.And the RIE device applied voltage, make the CF of importing 4Plasma makes on the surface of plasma attached to the dielectric film 22 that forms on the substrate 10, makes its reaction.Generation has volatile reaction product like this, by making surface disengaging the carry out active etching of this reaction product from the dielectric film 22 of substrate 10 formation.After etching finishes, remove resist 26 with stripper etc.In the present embodiment, the dielectric film 22 that on substrate 10, forms, except that the circumference of recess H0, the state that is removed substantially by above-mentioned etching forms.
In addition, the reaction product as the surface reaction that makes itself and dielectric film 22 preferably adopts CHF 3, C 4F 8Deng.And, adjust the dielectric film 22 etched processes of carrying out preferably by the setting of change to the import volume of power, the pressure of above-mentioned RIE device and the reaction product that in the RIE device, imports.For example, the power of RIE device brought up to be higher than above-mentioned condition and reduce under the situation of pressure, above-mentioned reaction product is increased, the etched tempo of result is totally accelerated, and can get the surface etching of the dielectric film 22 that forms on substrate 10 more.
Then shown in Fig. 4 (b), on the surface that above-mentioned etching is removed, form the surface that makes surface that electrode pad 16 exposes and remaining dielectric film 22.As basilar memebrane 24, at first form the barrier layer, and form inculating crystal layer thereon.Barrier layer and inculating crystal layer are for example used PVD such as vacuum vapour deposition, sputtering method, ion plating method (Physical Vapor Deposition: method physical vapour deposition (PVD)), and CVD method, IMP (ionic metal plasma) method, non-electrolytic plating method form.
And then shown in Fig. 5 (a), form electrode 34.Its concrete order: at first above the substrate 10 comprehensively on painting erosion resistant agent 32.Can adopt and electroplate with liquid resist or dry film etc. as resist 32.Though resist of using in the time of also can adopting in the semiconductor device generally the Al etching electrode that is provided with in addition or the resin resist with insulating properties, prerequisite is to have elching resistant for electroplate liquid that uses in the aftermentioned operation and etching solution.
The coating of resist 32 adopts spin-coating method, dip coating or spraying process etc. to carry out.Wherein the thickness setting of resist 32 must be identical with the thickness sum of the height of the portion of terminal 35 of the electrode 34 that should form and solder layer 40.Wherein, carry out prebake behind the painting erosion resistant agent 32.
Then the resist pattern is formed the flat shape of the portion of terminal 35 that should form electrode 34.Specifically, adopt formed decide pattern mask by carrying out exposure-processed and development treatment, resist 32 patterns are formed.If the flat shape rectangle of portion of terminal 35 wherein then forms the peristome of rectangular shape to resist 32 patterns.The size of peristome according to the settings such as spacing of electrode in the semiconductor chip 34, for example forms the square of 120 or 80 microns size dimensions.Here after pattern forms, set the size of peristome to such an extent that make resist 32 can not produce destruction.
More than 32 modes that the portion of terminal 35 of electrode 34 is surrounded are formed resist method be illustrated.Yet, not necessarily must make resist 32 form to such an extent that will surround around the portion of terminal 35.For example when electrode 34 form only under the adjacent situation of the paper left and right directions of Fig. 4 (a), also can form resist entering on the direction of this paper.So at least, can on the part of the outer shape of portion of terminal 35, form resist.
More than illustrated and adopted photoetching technique to form the method for resist 32.Yet in case adopt this method to form resist 32, part resist can enter in the H3 of hole portion when comprehensive painting erosion resistant agent, remains in problem in the H3 of hole portion even development treatment also has with the residue form.And for example preferably adopt printing processes such as dry film or silk screen printing, under pattern formation state, form resist 32.In addition, can also adopt droplet ejection apparatus such as ink discharge device, only, form the resist 32 under the pattern formation state to the formation position of resist 32 ejection resist drop.Can under the situation in resist can not enter the H3 of hole portion, form resist 32 like this.
Then making mask with this resist 32 fills electrode material in recess H0, forms electrode 34.The filling of electrode material adopts galvanoplastic and CVD method etc. to carry out.Electroplating processes for example adopts electrochemical deposition (ECP) method.Wherein use the electrode of the inculating crystal layer of formation basilar memebrane 24 as electroplating processes.And electroplanting device uses cup type electroplanting device.Cup type electroplanting device is a kind of so that electroplate liquid and spray from cup-like containers and electroplate device into feature.Electrode material can be filled in the recess H0 like this, form intercalation part 36.And electrode material can be filled in the peristome that is to form on the resist 32, form portion of terminal 35.
Formation solder layer 40 on electrode 34 then.The formation of solder layer 40 adopts scolder galvanoplastic and silk screen print method etc. to carry out.And can use the electrode of the inculating crystal layer of formation basilar memebrane 24 as the scolder plating.And can use cup type electroplanting device as electroplanting device.On the other hand, also can form the hard solder bed of material of forming by SnAg etc. and replace solder layer.The hard solder bed of material also can adopt formation such as galvanoplastic and print process.Form the state shown in Fig. 4 (a) by the way.
Then shown in Fig. 5 (b), utilize stripper etc. that resist 32 is peeled off (removing).Wherein stripper can use Ozone Water etc.And then remove the basilar memebrane 24 that above substrate 10, exposes.Its concrete order: at first above the substrate 10 comprehensively on painting erosion resistant agent, pattern forms the shape of the portion of terminal 35 of electrode 34.Then with the resist that formed by pattern as mask, with basilar memebrane 24 etchings.And formed the hard solder bed of material with under the situation that replaces solder layer 40, can be with this hard solder bed of material as mask, with basilar memebrane 24 etchings.In this case owing to not needing photo-mask process, so can simplify manufacturing process.
And then shown in Fig. 6 (a), after substrate 10 reversed up and down, stiffener 50 is installed in the below of substrate 10.Though can adopt diaphragm etc. as stiffener 50, hard materials such as preferred employing glass.Rear side to substrate 10 adds man-hour like this, can prevent to crack on the substrate 10 etc.By means of bonding agent 52 stiffener 50 is installed on the substrate 10.As bonding agent 52, should use curable bonding agents such as heat-curable adhesive or Photocurable adhesive agent.Concavo-convex on like this can not only the active face 10a of absorptive substrate 10, and stiffener 50 can also be installed securely.In addition, use under the situations of Photocurable adhesive agent as bonding agent 52 such as ultra-violet solidified bonding agent, preferably adopt translucent materials such as glass as stiffener 50.In this case, by outside irradiation light, bonding agent 52 is solidified from stiffener 50.
Then shown in Fig. 6 (b), all surfaces of substrate 10 rear side 10B is carried out etching, the end of dielectric film 22 is exposed, the rear side 10b from substrate 10 disposes laterally with the end of electrode 34.Etching can be adopted wet etching or dry-etching method.Wherein,, the end of dielectric film 22 is exposed, then can shorten manufacturing time if carry out etching after the rear side 10b rough polishing to substrate 10.And can be with to the etching of substrate 10 simultaneously, dielectric film 22 and basilar memebrane 24 are removed in etching.
Below as shown in Figure 7, the end of electrode 34 is exposed.Specifically, remove dielectric film 22 and basilar memebrane 24, the end of electrode 34 is exposed.Removing of dielectric film 22 and basilar memebrane 24 can adopt modes such as CMP (Chemical and Mechanical Polishing: chemistry and mechanical polishing) polishing to carry out.CMP is by means of having polishing cloth concurrently to the mechanical polishing of substrate with to the chemical action of the polishing fluid of its supply and substrate is polished.When wherein dielectric film 22 and basilar memebrane 24 are removed in polishing, also can be with the end polishing of electrode 34.In this case, because basilar memebrane 24 removed fully, so the poor flow between the electrode can prevent the stacked semiconductor chip time.
Thereafter with solvent etc. with bonding agent 52 dissolvings, take off stiffener 50 from substrate 10.Secondly the adhesive tape (diagram slightly) of will cutting into slices sticks on the rear side 10b of substrate 10, by 10 sections are separated into single semiconductor chip to substrate.And can pass through CO 2Substrate 10 is cut off in laser or YAG laser radiation.
Form state shown in Figure 1 like this, finish the semiconductor chip 2 that present embodiment relates to.
(stepped construction)
Will be stacked with the semiconductor chip 2 that upper type forms, form the three-dimensional semiconductor device of installing.
Fig. 8 is the side cross-sectional view of the semiconductor chip state that relates to of the stacked present embodiment of expression.Each semiconductor chip 2a, 2b, be configured in electrode 34 among the semiconductor chip 2b of lower floor portion of terminal above, be on the position, lower surface of the intercalation part of electrode 34 among the semiconductor chip 2a of upper strata.And the electrode 34 among each semiconductor chip 2a, 2b is engaged one another by means of solder layer 40.Specifically, not only make solder layer 40 dissolvings, but also form solder alloy, the two machinery and electricity are engaged at the junction surface by reflowing.Utilization connects each semiconductor chip 2a, 2b with upper type with distribution.And in case of necessity, can also in the space between each stacked semiconductor chip, fill basilar memebrane.
(disposing distribution again)
For stacked in the above described manner semiconductor device is installed on the circuit substrate, should carry out distribution again.Simple declaration distribution at first.Fig. 9 (a) and (b) be the key diagram of distribution again of semiconductor chip.On the surface of the semiconductor chip 61 shown in Fig. 9 (a), owing to form a plurality of electrodes 62 along its opposite side, so adjacent interelectrode mutual spacing narrows down.In case this semiconductor chip 61 is installed on the circuit substrate, the anxiety of mutual short circuit is just arranged between adjacent electrode.And, will carry out the distribution again of drawing along a plurality of electrodes 62 that the opposite side of semiconductor chip 61 forms to central portion for the mutual spacing of expansion electrode.
Fig. 9 (b) is the vertical view that the semiconductor chip of distribution is carried out in expression again.In the surface of semiconductor chip 61 central authorities, a plurality of electrode pads 63 of circle are arranged formation on matrix.Each electrode pad 63 is connected on one or more electrodes 62 with distribution 64 again.The electrode 62 of narrow-pitch can be drawn big spacingization like this to central portion.
Figure 10 is the side cross-sectional view of A-A line in Fig. 9 (b), and the semiconductor device of the stacked formation of aforesaid way is reversed up and down, on the bottom central part that is in undermost semiconductor chip 61, is formed with scolder-resist 65.And the surface from the portion of terminal of electrode 62 to scolder-resist 65 is formed with distribution 64 again.End in scolder-resist 65 sides of distribution 64 again forms electrode pad 63, is formed with projection (bump) 78 on the surface of this electrode pad 63.Projection 78 for example is a solder projection, utilizes print process to form.Wherein, make strengthen with resin 66 grades in the bottom surface of semiconductor chip 61 all on moulding.
(circuit substrate)
Figure 11 is the stereogram of circuit substrate.Among Figure 11,, be installed on the circuit substrate 1000 through the semiconductor device that semiconductor chip is laminated.Specifically, the projection that forms on the undermost semiconductor chip in semiconductor device 1 by reflowing and FCB (Film Chip Bonding: the film chip is connected) etc., is installed facing to the electrode pad that forms on the surface of circuit substrate 1000.Wherein, also semiconductor device 1 can be installed under the situation of clamping anisotropic conductive film between the circuit substrate.
[second kind of execution mode]
In first kind of execution mode, before forming electrode 34 on the recess H0, carried out the etching work procedure of dielectric film 22.In contrast to this, on recess H0, just carry out dielectric film 22 etching work procedure this point differences after the formation electrode 34 in the present embodiment.Following with reference to accompanying drawing detailed description present embodiment.In addition, will omit in the present embodiment to the explanation of above-mentioned first kind of execution mode same processes.
At first, the operation in first kind of execution mode till Fig. 2 (a)～(c) and Fig. 3 (a) is also carried out same operation in the present embodiment, forms dielectric film 22 by these operations on substrate 10.Then as Figure 12 (a) shown in, on the surface of the electrode pad 16 that exposes and dielectric film 22 comprehensively on formation basalis 24.Therefore in present embodiment, different with first kind of execution mode of etching dielectric film 22 before forming basilar memebrane 24.And about the formation of this basilar memebrane 24, adopt with first kind of execution mode in the same quadrat method that illustrates form.
And then shown in Figure 12 (b), form electrode 34.Painting erosion resistant agent on all surfaces that forms basalis 24 forms the shapes that formalize such as circle or rectangle with resist 32 patterns.And adopt galvanoplastic to form electrode 34.Concrete way, utilize with first kind of execution mode in the same quadrat method that illustrates form.
Follow shown in Figure 13 (a) formation solder layer 40 on electrode 34.About the formation of solder layer 40, also adopt with first kind of execution mode in the same quadrat method that illustrates carry out.Shown in Figure 13 (b), make mask etching dielectric film 22 and basalis 24 simultaneously then with above-mentioned solder layer 40.About the etching of this dielectric film 22, also adopt with first kind of execution mode in the same quadrat method that illustrates carry out.About operation thereafter, also adopt with first kind of execution mode in Fig. 6 (a) and (b) and same operation shown in Figure 7 carry out.Form semiconductor chip 2 through these processes.
Therefore, under the dielectric film 22 etched situations, can make mask etching dielectric film 22 in the present embodiment with solder layer 40.Solder layer 40 as mentioned above, when on the semiconductor chip 2 again under the situation of stacked semiconductor chip 2, the electrode 34 that can adopt two semiconductor chips 2 is as electric connection mode.Therefore, utilize this process of the manufacture process of semiconductor device 1, just energy etching dielectric film 22 can omit and adopt photolithographic resist pattern to form operation.Its result can prevent electrode 34 etched removing.
(electronic instrument)
The electronic instrument example that below utilizes Figure 14 to illustrate to possess above-mentioned semiconductor device.Figure 14 is the stereogram of mobile phone.Above-mentioned semiconductor device is configured in the framework inside of mobile phone 300.
In addition, above-mentioned semiconductor device can also be used for various electronic instruments except that mobile phone.For example, can also be applied in tape video camera, electronic notebook, desk top computer, automobile navigation apparatus, the POS terminal of liquid crystal projection apparatus, the personal computer (PC) corresponding and engineering work station (EWS), beep-pager, word processor, television set, view-finder type or monitoring type and possessing among the electronic instruments such as device of touch-screen with multimedia.
Technical scope of the present invention is not limited to above-mentioned execution mode, wherein is also included within the various changes of in the scope that does not exceed main points of the present invention above-mentioned execution mode being done.
For example, in first kind of above-mentioned execution mode, under the situation of etching dielectric film 22, adopt photoetching process to form the resist 26 that constitutes by deciding pattern, carry out etching as mask with this resist 26.In contrast to this, can not carry out etching as mask yet, and directly dielectric film 22 is carried out etching with resist 26.That is to say, make on substrate 10 etching speed that forms dielectric film 22,, also can need not mask and dielectric film 22 is carried out etching by carrying out anisotropic etching with this understanding than fast at the etching speed of the inner dielectric film 22 that forms of recess H0.Wherein, described etching can adopt various engraving methods such as Wet-type etching, dry-etching to carry out.Can under the situation of the inner residual dielectric film 22 of recess H0, be etched in the dielectric film 22 that forms on the substrate 10 like this.And, owing to omit photo-mask process, shorten manufacturing time and simplify manufacturing process.
And in above-mentioned first kind and second kind of execution mode, though be that the dielectric film 22 that forms on the recess H0 of substrate 10 circumference is all removed, but also preferably not exclusively remove this dielectric film 22, but it is littler than the dielectric film 22 that the peripheral part at electrode 34 forms that dielectric film 22 attenuates are got thickness.The internal stress and the thermal coefficient of expansion of the dielectric film 22 of formation on the substrate 10 can be reduced the bending of substrate 10 in the time of can suppressing chip like this.

Claims (10)

1. the manufacture method of a semiconductor device is the manufacture method with semiconductor device of the electrode that connects substrate, it is characterized in that wherein having successively:
On the active face of described substrate, form the operation of recess;
On the active face of the described substrate that comprises described recess inside, form the operation of insulating barrier;
Remove operation at least a portion of the outside described insulating barrier that forms of described recess;
Having formed the described recess inner filling electric conductor of described insulating barrier, to form the operation of described electrode; With
Remove the rear side of described active face, the operation that described electrode is exposed from the rear side of described active face.
2. the manufacture method of semiconductor device according to claim 1 is characterized in that, wherein removes in the operation at described insulating barrier, covers the described insulating barrier of described recess after etching with mask material.
3. the manufacture method of semiconductor device according to claim 1, it is characterized in that, wherein remove in the operation at described insulating barrier, under the fast condition of the etching speed of the insulating barrier that the etching speed that makes the insulating barrier that forms on the described substrate forms than the described recess inside at described substrate, carry out comprehensive etching.
4. the manufacture method of a semiconductor device is the manufacture method with semiconductor device of the electrode that connects substrate, it is characterized in that wherein having successively:
On the active face of described substrate, form the operation of recess;
On the active face of the described substrate that comprises described recess inside, form the operation of insulating barrier;
Having formed the described recess inner filling electric conductor of described insulating barrier, to form the operation of described electrode;
Remove operation at least a portion of the outside described insulating barrier that forms of described recess; With
The rear side of described active face is removed the operation that described electrode is exposed from the rear side of described active face.
5. the manufacture method of semiconductor device according to claim 4 is characterized in that, wherein removes in the operation at described insulating barrier, covers the described insulating barrier of described recess after etching with mask material.
6. the manufacture method of semiconductor device according to claim 4 is characterized in that, wherein removes in the operation at described insulating barrier, covers the described insulating barrier of the inner after etching of described recess with jointing material.
7. a semiconductor device is the semiconductor device that has formed integrated circuit on the active face of substrate, it is characterized in that wherein possessing:
Formed the described substrate of through hole from active face to the rear side of substrate;
The insulating barrier that on the internal face of described substrate and described through hole, forms; With
The electrode that inboardly forms at described insulating barrier, exposes from the rear side of described active face;
The thickness of the described insulating barrier that forms on the active face of described substrate is littler than the thickness of the described insulating barrier that forms in the periphery of described electrode.
8. a semiconductor device is the semiconductor device that has formed integrated circuit on the active face of substrate, it is characterized in that wherein possessing:
Formed the described substrate of through hole from active face to the rear side of substrate;
The insulating barrier that on the internal face of described through hole, forms; With
The electrode that inboardly forms at described insulating barrier, exposes from the rear side of described active face.
9. a circuit substrate is characterized in that, wherein possesses the described semiconductor device of claim 8.
10. an electronic instrument is characterized in that, wherein possesses the described circuit substrate of claim 9.
CNB2005100673214A 2004-04-16 2005-04-15 Semiconductor device, method for producing the same, circuit board, and electronic apparatus Expired - Fee Related CN100378939C (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475637A (en) * 2016-01-21 2018-08-31 三菱电机株式会社 Semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863187B2 (en) * 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7892972B2 (en) 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
FR2978610A1 (en) * 2011-07-28 2013-02-01 St Microelectronics Crolles 2 Method for making electrically conductive connection in semiconductor substrate of three-dimensional integrated structure, involves thinning substrate from face of substrate up to pillar that is guided on another face of substrate
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US10332757B2 (en) * 2017-11-28 2019-06-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package having a multi-portion connection element

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2270845A3 (en) * 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
JP3920399B2 (en) * 1997-04-25 2007-05-30 株式会社東芝 Multi-chip semiconductor device chip alignment method, and multi-chip semiconductor device manufacturing method and manufacturing apparatus
JP3792954B2 (en) * 1999-08-10 2006-07-05 株式会社東芝 Manufacturing method of semiconductor device
JP3951091B2 (en) * 2000-08-04 2007-08-01 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US6498381B2 (en) * 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
JP4110390B2 (en) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP2004228392A (en) * 2003-01-24 2004-08-12 Seiko Epson Corp Manufacturing method of semiconductor device and manufacturing method of semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475637A (en) * 2016-01-21 2018-08-31 三菱电机株式会社 Semiconductor device
CN108475637B (en) * 2016-01-21 2022-08-16 三菱电机株式会社 Semiconductor device with a plurality of semiconductor chips

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TW200535982A (en) 2005-11-01

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