CN1681378A - Blocking wiring method of multi-layer circuit board - Google Patents
Blocking wiring method of multi-layer circuit board Download PDFInfo
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- CN1681378A CN1681378A CN 200410033544 CN200410033544A CN1681378A CN 1681378 A CN1681378 A CN 1681378A CN 200410033544 CN200410033544 CN 200410033544 CN 200410033544 A CN200410033544 A CN 200410033544A CN 1681378 A CN1681378 A CN 1681378A
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Abstract
The multi-layer circuit at least comprises a first layer and a second layer. The wiring method includes following steps: arranges multi cam solder according to multi triangle unit; multi signal windings corresponding to multi cam solder are set on the first layer; multi signal windings corresponding to multi cam solder are set on the second layer; the multi signal windings on the second layer is parallel with multi signal windings on first layer at vertical plane; Multi shield windings are set between multi signal windings on the first and second layers.
Description
Technical field
The invention provides and a kind ofly the method for (route) a plurality of signal wire windings (signal trace) is set, refer to a kind of block type wiring method that a plurality of signal wire windings and a plurality of shielding coiling (shielding trace) are set especially on multilayer circuit board via the convex pads on the multilayer circuit board (bumper pad).
Background technology
In the modern society of the computer technology with high development, the computer system that includes a plurality of integrated circuits is used in each different field widely.For instance, housed device, mobile communication device and the personal computer with automatic control system all is to utilize integrated circuit to realize some specific function.The main body of integrated circuit is to be made of the small pieces (die) that existing semiconductor fabrication process is produced, the manufacturing process of these small pieces starts from makes wafer (wafer), then, each wafer is divided into a plurality of blocks again, therefore, just can form a plurality of circuit in each block by existing semiconductor fabrication process, last, each finished block just is cut into a plurality of small pieces further on the wafer.After obtaining required small pieces, still need use particular form that these small pieces are electrically connected on a circuit, for example a printed circuit board (PCB) (printed circuit board, PCB) on.Therefore, these small pieces just can obtain required operating voltage to carry out a scheduled operation from printed circuit board (PCB).For instance, the function of supposing small pieces is corresponding to a coding circuit, so, after this coding circuit receives suitable operating voltage, these small pieces just can carry out encoding process to the data that printed circuit board (PCB) is imported, and the data that will finish behind the coding are back to printed circuit board (PCB).
The small pieces of some integrated circuit, for example existing wire-bonded small pieces (wire-bond IC die) are provided with metal connection gasket (metal bonding pad) around its small pieces, be used as end points to connect these small pieces and external signal, for example control signal, power end and earth terminal.Generally speaking, the wire-bonded small pieces are arranged at plastics or ceramic packaging body (package) lining, and a plurality of pins (pin) are arranged on the packaging body, so the metal connection gasket around the small pieces just needs wiring to finish required the connection with pin on the packaging body.
Yet, above-mentioned packaged type has its restriction: first, because around having only small pieces connection gasket is arranged, so for the small pieces of a specific size, its number of the connection gasket that can be provided with also be subjected to the restriction of area size, in addition, yet progress along with science and technology, the logic gate quantity of being held in the small pieces is also more and more, so also increase for the demand of connection gasket thereupon, particularly is used for connecting the connection gasket of power end and earth terminal; The second, when all connection gaskets all be arranged at small pieces around the time, this moment just need additionally to connect up signal (the particularly signal of power end and earth terminal) is passed to the logical circuit of small pieces inside; The 3rd, in the wire-bonded small pieces, the metal wire that is used for connecting pin on small pieces and the packaging body can produce extra resistance value (resistance) worsens small pieces with inductance value (inductance) usefulness.
In order to improve the problems referred to above, flip chip encapsulation (flip-chip packaging) has become preferred packaged type today.The flip chip encapsulation technology makes that the overall dimensions of packaging body can be tightr, and with respect to the wire-bonded small pieces, and these small pieces and external electric parts link, and to be connected the resistance value and the inductance value that are produced littler.In addition, because the online distance of these small pieces and power end and earth terminal shortens, so can obtain the power supply supply of higher quality.Yet even use the flip chip encapsulation technology, the actual size of small pieces is influenced by the size and the quantity of the convex pads that distributes on the small pieces need still unavoidablely.Because the market keen competition, it is littler, more effective therefore constantly to stimulate enterprise to research and develop with the production size, and dynamical product, and therefore how shorten product sizes is considered and become an important topic to meet production cost.
In order to reach the advantage of saving the space, also use the technology of multilager base plate (a for example circuit board) in the electronic system.Multilager base plate can be used different manufactures and produces now, for example multilager base plate can be thin slice storehouse substrate (laminated substrate) or deposition substrate (build-up substrate), and in the above-mentioned different multilager base plate that manufacture generated, because the live width of the signal line on the deposition substrate can be carefully to 30 μ m, so the most suitable current densities that is applied to the device of many pin counts demand with expansion available circuit plate of deposition substrate.See also Fig. 1 and Fig. 2, Fig. 1 is the schematic diagram that has on six layers of additional layers substrate 12 configuration one small pieces 10 now, and Fig. 2 is the schematic diagram of six layers of additional layers substrate 12 shown in Figure 1.Six layers of additional layers substrate 12 comprise four internal layer 12A, 12B, 12E, 12F, are used to dispose a plurality of signal wire windings, and wherein live width/line-spacing can be provided is the wiring of 25 μ m/25 μ m and the via 12G of path length 110 μ m to each internal layer.It is the wiring of 100 μ m/100 μ m and the via 12H of 440 μ m that two layers of 12C, 12D in addition provide live width/line-spacing separately.Structure based on above-mentioned six layers of additional layers substrate 12, when using six layers of additional layers substrate 12, have only four internal layer 12A, 12B, 12E, and 1 2F can be used to arrange signal wire winding, because remaining two-layer 12C, can provide bigger via (440 μ m) 12H that power supply and ground connection are provided between the 12D, so above-mentioned two- layer 12C, 12D then should not allow signal wire winding pass through.
See also Fig. 3, Fig. 3 shows the enlarged diagram in zone 14 for frame shown in Figure 1.Embodiment shown in Figure 3 shows that a plurality of signal wire windings 18 are electrically connected to six layers of additional layers substrate 12 shown in Figure 2 from small pieces 10.The embodiment of Fig. 3 shows that all signal wire windings all are designed to be electrically connected to internal layer 12A, and 12B is so a plurality of signal wire windings 18 can be according to being positioned at the signal wire winding 18 (2) that internal layer 12A or 12B are divided into the signal wire winding 18 (1) that is positioned at ground floor and the second layer.See also Fig. 4, Fig. 4 is the schematic diagram that is arranged at the convex pads 20 on Fig. 1, the 3 described small pieces 10.A plurality of convex pads 20 are used as the end points of the I/O of small pieces 10.Fig. 1 or signal wire winding 18 shown in Figure 3 can be connected to corresponding convex pads 20, and wherein convex pads 20 may be positioned at die edge zone (dieperiphery) 22 or small pieces central area 24.
Please later consult Fig. 1 and Fig. 2, when signal wire winding 18 when convex pads 20 places of small pieces 10 begin to be provided with, dashed region 16 shown in Figure 1 is not sufficient to hold wide-aperture via 12H like this.Therefore only there is the signal wire winding 18 of minority can directly be arranged to internal layer 12E, 12F downwards.This has explained also why signal wire winding 18 nearly all is distributed in last two-layer internal layer 12A, 12B shown in Figure 3.As shown in Figure 4, when using flip chip encapsulation technology (flip-chip packaging), the small pieces 10 of a standard comprise hundreds of convex pads 20, and the appropriate location that how bars coilings 18 up to a hundred is routed on the small pieces 10 is a quite complicated job.In addition, a large amount of convex pads 20 must closely be arranged and be put so that the winding space on the substrate 12 can be effectively utilized, simultaneously, this represents that also the heavy substrate 12 of six laminations must provide wiring more closely and better elasticity in desired signal wire winding 18 is set in a zone.Unavoidable ground, highdensity signal wire winding distributes and less chip size makes that all the interval between the signal wire winding 18 is minimum, just worsen the crosstalk effect (cross-talk effect) that has between the signal wire winding 18, wherein major part is capacitive crosstalk effect (capacitivecross-talk), so above-mentioned crosstalk effect just can reduce signal quality further.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of block type wiring method that utilizes so that a plurality of signal wire windings and shielding coiling to be set on multilayer circuit board, to address the above problem.
The present invention proposes a kind of method that a plurality of signal wire windings (signal trace) of corresponding a plurality of convex pads (bumper pad) are set on multilager base plate (circuit board).The inventive method is formed a plurality of convex pads blocks according to a specific arrangement method with a plurality of convex pads, and in addition, a plurality of signal wire windings only are routed to the ground floor and the second layer of multilager base plate, and the 3rd layer then is used for being electrically connected of power end and earth terminal.In addition, between a plurality of signal wire windings, be used to provide shield effectiveness on the interspersed ground floor of a plurality of shielding coilings and the second layer.In addition, the inventive method can be applicable to the flip chip encapsulation technology, the wire-bonded technology, and coil type engages (tape automatic bonding) technology automatically, and other encapsulation technology.
Among the present invention, convex pads is a corresponding particular arrangement in the convex pads block.A plurality of ground floor coiling designs trend in line, the second layer winds the line then conversion direction to avoid with to be positioned at detouring of ground floor parallel to each other on vertical plane, therefore, this simple and handy arrangement mode is dispensed to corresponding signal wire winding from each convex pads easily.
The present invention discloses a kind of wiring method that a plurality of signal wire windings (signal trace) of corresponding a plurality of convex pads (bumper pad) are set on a multilayer circuit board (multi-layer circuit board), this multilayer circuit board includes has a ground floor and a second layer at least.This wiring method includes: arrange this a plurality of convex pads according to a plurality of triangular units (triangle unit); A plurality of signal wire windings of corresponding a plurality of convex pads are set on this ground floor; A plurality of signal wire windings of corresponding a plurality of convex pads are set on this second layer, and a plurality of signal wire windings of this of this second layer are not parallel with a plurality of signal wire windings of this ground floor in vertical plane; And a plurality of shieldings coilings (shielding trace) are set between a plurality of signal wire windings of this first and second layer.
Moreover, the present invention discloses a kind of block type wiring method in addition, be used for being provided with on a multilayer circuit board (multi-layer circuit board) wiring method of a plurality of signal wire windings (signal trace) of corresponding a plurality of convex pads (bumper pad), this multilayer circuit board includes has a ground floor and a second layer at least.This block type wire laying mode includes: should a plurality of convex pads be formulated for a convex pads block according to a specific arrangement mode; Appointment is a plurality of ground floors coilings that are arranged on this ground floor to a plurality of signal wire windings of a plurality of convex pads in should the convex pads block; Appointment is a plurality of second layers coilings that are arranged on this second layer to a plurality of signal wire windings of a plurality of convex pads in should the convex pads block; In a straight line mode this a plurality of ground floor coilings are set; These a plurality of second layer coilings are set so that these a plurality of second layer coilings are vertically not parallel in these a plurality of ground floor coilings in a turnover mode; And these a plurality of ground floor coilings of shielding and these a plurality of second layer coilings.
In addition, the present invention discloses a kind of method that a plurality of signal wire windings of corresponding a plurality of convex pads are set again, and it is applied to the small pieces (die) on the multilayer circuit board (multi-layer circuit board).This method includes: a plurality of convex pads of using the die edge zone (periphery area) that is arranged at these small pieces; Use is arranged at a plurality of power ends/earth terminal convex pads of the small pieces central area (center area) of these small pieces; A plurality of signal wire windings of specifying corresponding a plurality of convex pads are a plurality of ground floor coilings that are arranged on this ground floor; A plurality of signal wire windings of specifying corresponding a plurality of convex pads are a plurality of second layer coilings that are arranged on this second layer, and wherein this second layer vertically is positioned at the below of this ground floor; In a straight line mode this a plurality of ground floor coilings are set; These a plurality of second layer coilings are set so that these a plurality of second layer coilings vertically are not positioned at the below of these a plurality of ground floor coilings in a turnover mode; And via this a plurality of power ends/earth terminal convex pads certainly a plurality of shieldings are set and wind the line and shield these a plurality of ground floors coilings and should wind the line by a plurality of second layers.
Description of drawings
Fig. 1 is the schematic diagram that has configuration one small pieces on six layers of additional layers substrate now.
Fig. 2 is the schematic diagram of six layers of additional layers substrate shown in Figure 1.
Fig. 3 is the enlarged diagram in zone shown in Figure 1.
Fig. 4 is the schematic diagram that is arranged at the convex pads on Fig. 1, the 3 described small pieces.
Fig. 5 is a plurality of convex pads and first kind of configuration schematic diagram of a plurality of corresponding signal wire windings.
Fig. 6 is the schematic perspective view of a part in the multilager base plate shown in Figure 5.
Fig. 7 is the schematic diagram of first kind of configuration of second kind of configuration of a plurality of convex pads and convex pads shown in Figure 5.
Fig. 8 is applied to the flow chart of the wiring method of convex pads block shown in Figure 7 for the present invention.
Fig. 9 is the convex pads block signal wire winding corresponding with it shown in Figure 7 and the schematic diagram of shielding coiling.
Figure 10 is the schematic diagram from embodiment improvement shown in Figure 5 to embodiment shown in Figure 9.
Figure 11 is applied to the flow chart of embodiment E shown in Figure 10 for the inventive method.
Figure 12 is the profile of embodiment E shown in Figure 10.
Figure 13 is provided with the schematic diagram that a plurality of convex pads and corresponding ground floor wind the line for the present invention in small pieces.
The simple symbol explanation
12 6 layers of additional layers substrate of 10 small pieces
22,24,94 small pieces central areas, 92 die edge zones
12A, 12B, 12C, internal layer 12H, 12G via
12D、12E、12F、
82A?82B、82C
18 (1), 18 (2), signal line 20,31～38,51～convex pads
39～46、59～66、 58、90
88、89
67～74 shielded lines, 82 multilager base plates
84,86 convex pads blocks
Embodiment
See also Fig. 5, Fig. 5 is first kind of ornaments schematic diagram of part convex pads 31～38 and a plurality of signal wire windings 39～46.The chip size of the ornaments of this convex pads and many pin counts small pieces has height correlation, for the flip chip encapsulation, chip size (Fig. 1 and small pieces 10 shown in Figure 4) is subjected to two elements affect, and just the quantity of convex pads and corresponding holding wire are around the required area that takies.As shown in Figure 5, convex pads 31～38 is disposed on the multilager base plate 82, and this multilager base plate 82 comprises at least one ground floor 82A and a second layer 82B (second layer 82B be positioned at ground floor 82A under).Multilager base plate 82 can be six layers of additional layers substrate 12 shown in Figure 2 (ground floor 82A can correspond to internal layer 12A, and second layer 82B can correspond to internal layer 12B) or any multilayer circuit board (multi-layercircuit board).According to existing manufacturing process technology, the pairing minimum value of the distance between two convex pads (being called the convex pads spacing) is 227 μ m, and the path length of arbitrary convex pads (width) then is 110 μ m.On the ground floor 82A on the multilager base plate 82, a plurality of signal wire windings 39～42 outwards are provided with from a plurality of convex pads 31,32,35,36 respectively, and the minimum feature of signal wire winding is that the minimum line of 25 μ m and adjacent two coilings are apart from also being 25 μ m.After simple calculating, still leave the distance of 112 μ m (227-115=112) between convex pads 31 and the convex pads 35, just above-mentioned gap only can allow that single signal wire winding passes through, and the signal wire winding 43～46 (circuit that dotted line indicates among the figure) that therefore corresponds to convex pads 33,34,37,39 just can only be arranged on the second layer 82B.
Convex pads 31 or convex pads 35 please be paid special attention to and power supply connection gasket or ground connection connection gasket can not be planned to, if this two convex pads is planned to the function of ground connection connection gasket or power supply connection gasket, then will lose two corresponding signal wire windings, therefore just need to plan more convex pads and wider die edge zone (zone of die edge shown in Fig. 4 22) meeting the needs of convex pads number, so said method is not a cost-effective method.Based on above-mentioned considering, therefore a kind of arrangement of more effective convex pads just is used for reaching the purpose that reduces chip size, sees also Fig. 4, and Fig. 4 is the schematic diagram that is arranged in a plurality of convex pads 20 on the small pieces shown in Figure 1 10.Die edge zone 22 is provided with the convex pads of all input/output signal coilings of corresponding small pieces 10, that is to say, the signal wire winding of all corresponding input/output signals contained whole small pieces 10 around, just the die edge zone 22, and the central area 24 of small pieces 10 then comprises the convex pads of corresponding power end/earth terminal.
According to the mode of putting of a plurality of convex pads 31～38 shown in Figure 5, all signal wire windings 39～46 all can closely be put to avoid the waste of any free space in die edge zone 22.Under highdensity wiring situation, and before the coiling distribution is come, the spacing of two adjacent coilings very little (as discussed previously, the minimum line distance is 25 μ m), therefore mutual electromagnetic interference just becomes the key factor that influences the transmission signals quality between the coiling.See also Fig. 5, the wiring of signal wire winding 39～46 is not that to be positioned at abreast with one deck be exactly to be positioned at different layers abreast, and thus, the interference between signal wire winding also can be from the signal wire winding on the different layers not only from the adjacent signal coiling with one deck.With ground floor 82A is example, and signal wire winding 39～42 must be because of the too near interference that seriously is subjected to contiguous coiling with lacking shielding protection of distance.Two-layer (ground floor 82A and second layer 82B) included in consideration, because insufficient space, so can place shielded line with the maintenance signal quality without any the space.
See also Fig. 6, Fig. 6 is the schematic perspective view of a part in the multilager base plate 82 shown in Figure 5.Signal wire winding 39～41 is positioned at the ground floor 82A of multilager base plate 82, and three barss coiling 43～45 then is positioned at the second layer 82B of multilager base plate 82 in addition, in addition, one deck 47 is arranged in addition as an insulating barrier between ground floor 82A and the second layer 82B.When signal wire winding 39,41,44 operates simultaneously, apparently, signal wire winding 40 can be subjected to the serious interference of three adjacent signals coilings 39,41,44 of level and vertical direction, because in the additional layers substrate 12 shown in Figure 2, ground floor 82A and second layer 82B are only at a distance of 30 μ m, so the interference that above-mentioned signal wire winding causes will be more remarkable in additional layers substrate 12 shown in Figure 2, therefore, reducing or increasing at least not significantly under the prerequisite of chip size, just need a kind of brand-new convex pads and the configuration mode of wiring to promote signal quality.
Limit based on the above-mentioned live width and the line-spacing that have about existing manufacturing process technology mentioned, how suitable the present invention set forth the convex pads of putting, the convex pads of power end/earth terminal, and the wiring of the set signal wire winding of multilager base plate 82 upper protruding block weld pads.Please look back Fig. 5, as before described, between the two adjacent convex pads in permissible range (227 μ m) have only bars coiling be able to by.For different between the convex pads configuration clearly are described among the configuration of new convex pads and above-mentioned Fig. 5, therefore use and define a kind of convex pads block (bumper-tile block).See also Fig. 7, Fig. 7 is the schematic diagram of first kind of configuration of second kind of configuration of convex pads 51～58 and convex pads 31～38 shown in Figure 5.Eight convex pads 31～38 are regarded as the first convex pads block 84 of corresponding first kind of arrangement mode, other eight convex pads 51～58 then are the second convex pads blocks 86 of corresponding second kind of arrangement mode, each convex pads block, no matter be that the first convex pads block 84 or the second convex pads block 86 all comprise eight convex pads, be used for connecting eight signal wire winding additional layers that are distributed in middle ground floor 82A of multilager base plate 82 (six layers of additional layers substrate 12 for example shown in Figure 2) and second layer 82B.Please note, second kind of new configuration mode of corresponding eight convex pads 51～58 is a kind of embodiment of the present invention about the setting of convex pads 51～58, and the small change of the second convex pads block 86 is also belonged to category of the present invention, following narration will describe in detail from the first convex pads block, 84 progressive processes to the second convex pads block 86.
At first, each convex pads block can be regarded as being made up of a plurality of difform unit.See also Fig. 7, the first convex pads block 84 originally can be considered by a plurality of rectangular cells 84a to be formed, and the characteristic of first kind of configuration mode illustrates in embodiment shown in Figure 5.According to technology of the present invention, new convex pads block changes by a plurality of triangular unit 86a (as shown in Figure 7) to be formed, and the corresponding identical length in each limit of these triangular units 86a, in addition, all convex pads spacings are all identical with convex pads spacing in original convex pads block 84 in the convex pads block 86, yet, because the alteration of form of each component units, so the occupied area of convex pads block (it has determined chip size) also changes to some extent.The width of the first convex pads block is 342 μ m (minimum convex pads spacing+convex pads width, just 227+115=342 (μ m)), and length is 796 μ m (minimum convex pads spacing+convex pads is wide, just 681+115=796 (μ m)); In new configuration, the width of convex pads block 86 is 455.5 μ m (the minimum convex pads spacing+convex pads of 1.5* is wide, just 340.5+115=455.5 (μ m)), and length is 700 μ m (1.5*
* minimum convex pads is wide+and convex pads is wide, 590+115=700 (μ m) just).Configuration via the visible second convex pads block 86 of above-mentioned Simple Calculation causes width to increase, but length but shortens, so this new configuration mode can't additionally increase the size of small pieces significantly, but can make full use of characteristics of the present invention.
According to the configuration of the above-mentioned second convex pads block 86, a kind of wiring method discloses and connects corresponding a plurality of (8) signal wire winding with a plurality of on multilager base plate 82 (8) convex pads.As previously mentioned, signal wire winding is distributed in the ground floor 82A and the second layer 82B of multilager base plate 82, sees also Fig. 8, and Fig. 8 is applied to the flow chart of the wiring method of convex pads block 86 shown in Figure 7 for the present invention, and its operating procedure is as follows:
Step 100: a plurality of convex pads of configuration on a plurality of triangular units;
Step lOl: on ground floor, dispose corresponding a plurality of signal wire winding from a plurality of convex pads:
Step 102: on the second layer, dispose corresponding a plurality of signal wire winding from a plurality of convex pads, still
These a plurality of signal wire windings can not be arranged in the existing signal wire winding of this ground floor under; With
And
Step 103: a plurality of shielding coilings of configuration between a plurality of signal wire windings of this first and second layer respectively.
Please note that the shape according to each unit is not defined as equilateral triangle, and difform triangle also can be used to design each unit among the present invention, in addition, the convex pads quantity of convex pads block 86 is not limited to eight, and can be adjusted according to actual demand.See also Fig. 9, Fig. 9 is convex pads block 86 signal wire windings corresponding with it shown in Figure 7 and the schematic diagram of shielding coiling.As shown in Figure 9, convex pads 51～58 on the multilager base plate 82 and a plurality of signal wire windings 59～62 that are derived from convex pads 51～58 all are positioned at the ground floor 82A of multilager base plate 82, other four barss coiling, 63～66 53,54,57,58 of convex pads corresponding with it are assigned to second layer 82B, and the circuit on the second layer then is covered with oblique line and represents.Shielding coiling 67～70 (fine rules) that please note ground floor 82A are interspersed between the signal wire winding 59～62 so that the interference shielding function of last adjacent two signal wire windings of ground floor 82A to be provided.In like manner, last four the shielding coilings 71～74 of second layer 82B (fine rule and fill up oblique line) are interspersed between the four barss coiling 63～66 so that the interference shielding function of last adjacent two holding wires of second layer 82B to be provided.
Wire laying mode shown in Figure 9 can be improved length by length from embodiment shown in Figure 5 and form.See also Figure 10, Figure 10 is the schematic diagram from embodiment improvement shown in Figure 5 to embodiment shown in Figure 9.
Figure 10 comprises five embodiment A～E, wherein contains Fig. 5 and embodiment shown in Figure 9, and figure E is and the identical embodiment of Fig. 9.Embodiment A is revised by the embodiment of Fig. 5, and the signal wire winding 43～46 that is derived from convex pads 33,34,37,38 just turns to after leaving convex pads 33,34,37,38 immediately with under the signal wire winding 39～42 of avoiding being positioned at ground floor.Then, in Embodiment B, the convex pads block is corresponding diagram 7 and the second convex pads block 86 shown in Figure 9 via adjustment, set up a wiring rule simultaneously all signal wire windings 18 are set: all signal wire windings 18 among the ground floor 82A all change and take the air line, and the signal wire winding of second layer 82B just turns to when leaving corresponding convex pads.Therefore, all signal wire windings stagger mutually and are positioned on the same vertical plane with the coiling of avoiding different layers, so far only solve the problem of vertical interference.Yet the level interference between the same layer signal coiling further method solves, and just adds the shielding coiling.See also Embodiment C, its demonstration ground floor (upper strata) is gone up signal wire winding 59～62 and is interted the setting of shielding coiling 67～70 therebetween.In like manner, see also embodiment D, its demonstration second layer 82B (lower floor) goes up signal wire winding 63～66 and interts the setting of shielding coiling 71～74 therebetween.Behind the equipment energy characteristic of combination Embodiment C and embodiment D, promptly produce final required embodiment E.
Based on embodiment E shown in Figure 10 and above-mentioned wiring rule, the specific embodiment that the present invention discloses another kind of wiring method is provided with a plurality of (8) convex pads and a plurality of (8) signal wire winding with the second convex pads block 86 on multilager base plate 82.See also Figure 11, Figure 11 is applied to the flow chart of embodiment E shown in Figure 10 for the inventive method, and its operating procedure is as follows: step 200: according to a particular form a plurality of convex pads are planned to a convex pads block, and should be many
Individual convex pads constitutes a plurality of triangular units;
Step 201: configuration is used a plurality of signal wire windings of a plurality of convex pads in should the convex pads block
Be used as being routed at the ground floor coiling on the ground floor, and according to embodiment shown in Figure 10
E, it is 59～62 that the ground floor coiling is signal wire winding;
Step 202: configuration is used a plurality of signal wire windings of a plurality of convex pads in should the convex pads block
Be used as being routed at the second layer coiling on the second layer, and according to embodiment shown in Figure 10
E, it is 63～66 that second layer coiling is signal wire winding;
Step 203: move towards to be provided with a plurality of ground floor coilings with a straight line;
Step 204: a plurality of second layer coilings have a turnover so that it is not just winding the line at ground floor the position in being provided with
The below;
Step 205: on ground floor, per two adjacent ground floor winding departments add ground floor shielding coiling,
Embodiment E as shown in figure 10, ground floor shielding coiling is shielding coiling 67～70; With
And
Step 206: on the second layer, per two adjacent second layer winding departments add second layer shielding coiling,
Embodiment E as shown in figure 10, second layer shielding coiling is shielding coiling 71～74.
This simple and easy and effective wiring rule, just the signal wire winding on the ground floor 82A takes the air line, and the signal wire winding on the second layer 82B turns in leaving corresponding convex pads, provides a method to solve wind the line problem on the small pieces 80 with a large amount of convex pads (small pieces 80 corresponding shown in Figure 1 small pieces 10) of signalization how.For emphasizing this structure of the present invention, other has a Figure 12 to be illustrated.Figure 12 is the profile of embodiment E shown in Figure 10, also is the profile of embodiment shown in Figure 9.Apparently, multilager base plate 82 also comprises one the 3rd layer of 82C, and it is positioned under the second layer 82B, is used as a ground plane.Signal wire winding 59,60 winds the line (Figure 11 defines) for the ground floor that is arranged in multilager base plate 82 ground floor 82A, and signal wire winding 63,64 is for being arranged in the second layer coiling of multilager base plate 82 second layer 82B.Signal wire winding 60 is positioned at the ground floor shielding coiling 67,68 on its both sides and is positioned at 72 shieldings of second layer shielding coiling under it, therefore, except the signal wire winding (for example signal wire winding 59) at several edges, each bars coiling is all surrounded by three shielding coilings among the ground floor 82A, wherein two parallel in the horizontal direction with this signal wire winding, and another is parallel with it in vertical direction.In like manner, second layer signal wire winding also has same characteristic, is example with signal wire winding 63, and its both sides is subjected to 71,72 protections of two shielding coilings respectively, and in addition, ground floor also has shielding coiling 67 to be positioned at directly over it, then is the 3rd layer of 82C under it.Therefore, the arbitrary bars coiling on the second layer 82B not only is subjected to three shielding coilings and protects, and is positioned at the ground plane (the 3rd layer of 82C) under it in addition.According to wiring method of the present invention, all signal wire windings all can be subjected to complete protection, and capacitive interference (capacitive interference) also can be reduced effectively.
At last, all convex pads that link to each other with signal wire winding are formed a die edge zone 92.See also Figure 13, Figure 13 is provided with wind the line 88 schematic diagram of a plurality of convex pads 90 and corresponding ground floor for the present invention in small pieces 80.Small pieces 80 comprise a central area 94 and a die edge zone 92.Embodiment shown in Figure 13 is similar to embodiment shown in Figure 4, the characteristics of the embodiment of its suitable the invention described above.All signal wire windings (comprising that ground floor detours 88) all distribute equably, and staggered with shielding coiling (earth terminal), and only represent ground floor shielding coiling 89 with dotted line among Figure 13.For each edge of small pieces 80, it is 88 all parallel with shielding coiling 89 and directly walk forward that each ground floor detours, and up to arriving its corresponding via, so ground floor detours and 88 just can be connected to corresponding solder ball (soldering ball); Moreover, all outwards settings of corresponding convex pads 90 beginnings on small pieces fringe region 92 of all signal wire windings (comprising ground floor coiling 88), the convex pads of all the other corresponding power ends or earth terminal then is placed on the central area 24 of small pieces 80.
The present invention proposes a kind of new wiring method, can be used for the flip chip encapsulation technology and make that a plurality of convex pads can be connected to a plurality of signal wire windings in the multilager base plate, these a plurality of convex pads are assembled a plurality of convex pads blocks of formation, and arrange according to the mode of a plurality of triangular units.When the inventive method is implemented, a plurality of signal wire windings are distributed in first and second layer of multilager base plate, the 3rd layer of multilager base plate then is used to connect power end or earth terminal, in addition, in the ground floor and the second layer, a plurality of shielding coilings then are disposed under the situation that need not use exceptional space between a plurality of signal wire windings so that the interference shielding function to be provided.
The above only is the preferred embodiments of the present invention, and the equalization that all the present patent application claims are done changes and modifies, and all should belong to the covering scope of patent of the present invention.
Claims (21)
1, a kind of wiring method that a plurality of signal wire windings (signal trace) of corresponding a plurality of convex pads (bumper pad) are set on a multilayer circuit board (multi-layer circuit board), this multilayer circuit board includes has a ground floor and a second layer at least, and this wiring method includes:
Arrange this a plurality of convex pads according to a plurality of triangular units (triangle unit);
A plurality of signal wire windings of corresponding a plurality of convex pads are set on this ground floor;
A plurality of signal wire windings of corresponding a plurality of convex pads are set on this second layer, and a plurality of signal wire windings of this of this second layer are not parallel with a plurality of signal wire windings of this ground floor in vertical plane; And
A plurality of shielding coilings (shieldingtrace) are set between a plurality of signal wire windings of this first and second layer.
2, wiring method as claimed in claim 1, wherein this multilayer circuit board also includes one the 3rd layer, is used as a ground plane (ground plane), and these a plurality of shielding coilings are connected in the 3rd layer.
3, wiring method as claimed in claim 2, wherein this second layer vertically is positioned at the below of this ground floor, and the 3rd layer of below that vertically is positioned at this second layer.
4, wiring method as claimed in claim 1 is applied to flip chip encapsulation (flip-chippackaging) technology, a wire-bonded technology, the automatic joining technique of a coil type, and other encapsulation technology.
5, a kind of block type wiring method, be used on a multilayer circuit board (multi-layer circuit board), being provided with a plurality of signal wire windings (signal trace) of corresponding a plurality of convex pads (bumper pad), this multilayer circuit board includes has a ground floor and a second layer at least, and this block type wiring method includes:
Should a plurality of convex pads be formulated for a convex pads block according to a specific arrangement mode;
Appointment is a plurality of ground floors coilings that are arranged on this ground floor to a plurality of signal wire windings of a plurality of convex pads in should the convex pads block;
Appointment is a plurality of second layers coilings that are arranged on this second layer to a plurality of signal wire windings of a plurality of convex pads in should the convex pads block;
In a straight line mode this a plurality of ground floor coilings are set;
These a plurality of second layer coilings are set so that these a plurality of second layer coilings are vertically not parallel in these a plurality of ground floor coilings in a turnover mode; And
Shield these a plurality of ground floor coilings and these a plurality of second layer coilings.
6, block type wiring method as claimed in claim 5, it also includes:
Between per two adjacent ground floor coilings on the ground floor of this multilayer circuit board, ground floor shielding coiling is set; And
Between per two adjacent second layer coilings on the second layer of this multilayer circuit board, second layer shielding coiling is set.
7, block type wiring method as claimed in claim 6, wherein this multilayer circuit board also includes one the 3rd layer, is used as a ground plane, and this block type wiring method also includes:
Utilization is connected to each ground floor shielding coiling of the 3rd layer and carries out ground connection; And
Utilization is connected to each second layer shielding coiling of the 3rd layer and carries out ground connection.
8, block type wiring method as claimed in claim 7, wherein this second layer vertically is positioned at the below of this ground floor, and the 3rd layer of below that vertically is positioned at this second layer.
9, block type wiring method as claimed in claim 5, wherein each convex pads block includes eight convex pads, and it arranges corresponding a plurality of positive triangular units, and corresponding eight signal wire windings that can transmit input/output signal of these eight convex pads.
10, block type wiring method as claimed in claim 9, wherein this convex pads block is arranged at the zone, an edge (periphery area) of small pieces (die).
11, block type wiring method as claimed in claim 5 is applied to flip chip encapsulation (flip-chip packaging) technology and other encapsulation technology.
12, block type wiring method as claimed in claim 5, wherein this multilayer circuit board is any multi-layer sheet that one or six layers of additional layers substrate (6-layer build-up substrate) or are applied to the high pin number.
13, a kind of method that a plurality of signal wire windings of corresponding a plurality of convex pads are set, it is applied to the small pieces (die) on the multilayer circuit board (multi-layer circuit board), and this method includes:
Use is arranged at a plurality of convex pads in the die edge zone (periphery area) of these small pieces;
Use is arranged at a plurality of power ends/earth terminal convex pads of the small pieces central area (center area) of these small pieces;
Specify a plurality of convex pads to arrange with particular form;
A plurality of signal wire windings of specifying corresponding a plurality of convex pads are a plurality of ground floor coilings that are arranged on this ground floor;
A plurality of signal wire windings of specifying corresponding a plurality of convex pads are a plurality of second layer coilings that are arranged on this second layer, and wherein this second layer vertically is positioned at the below of this ground floor;
In a straight line mode this a plurality of ground floor coilings are set;
These a plurality of second layer coilings are set so that these a plurality of second layer coilings vertically are not positioned at the below of these a plurality of ground floor coilings in a turnover mode; And
Via this a plurality of power ends/earth terminal convex pads certainly a plurality of shieldings being set winds the line and shields these a plurality of ground floors coilings and should wind the line by a plurality of second layers.
14, method as claimed in claim 13, wherein these a plurality of signal wire windings can transmit a plurality of input/output signals, are used for connecting these small pieces and a plurality of external modules that are arranged on this multilayer circuit board.
15, method as claimed in claim 13, wherein these a plurality of convex pads can be formed a plurality of convex pads blocks.
16, method as claimed in claim 15, wherein each convex pads block includes eight convex pads, and it arranges corresponding a plurality of positive triangular units.
17, method as claimed in claim 13, wherein these a plurality of shielding coilings include a plurality of second layers shielding coilings that a plurality of ground floor shieldings that are disposed at this ground floor wind the line and are disposed at this second layer.
18, method as claimed in claim 17, it also includes:
Between per two adjacent ground floor coilings on the ground floor of this multilayer circuit board, each ground floor shielding coiling is set; And
Between per two adjacent second layer coilings on the second layer of this multilayer circuit board, each second layer shielding coiling is set.
19, method as claimed in claim 18, wherein this multilayer circuit board also includes one the 3rd layer, is used as one power supply/ground plane, and this method also includes:
Utilization is connected to each ground floor shielding coiling of the 3rd layer and carries out ground connection; And
Utilization is connected to each second layer shielding coiling of the 3rd layer and carries out ground connection.
20, method as claimed in claim 13, wherein this multilayer circuit board is one or six layers of additional layers substrate (6-layer build-up substrate) or any multi-layer sheet that is applied to the high pin number.
21, method as claimed in claim 13 is applied to flip chip encapsulation (flip-chippackaging) technology or other encapsulation technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410033544 CN1681378A (en) | 2004-04-06 | 2004-04-06 | Blocking wiring method of multi-layer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410033544 CN1681378A (en) | 2004-04-06 | 2004-04-06 | Blocking wiring method of multi-layer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1681378A true CN1681378A (en) | 2005-10-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410033544 Pending CN1681378A (en) | 2004-04-06 | 2004-04-06 | Blocking wiring method of multi-layer circuit board |
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| Country | Link |
|---|---|
| CN (1) | CN1681378A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110741472A (en) * | 2017-08-03 | 2020-01-31 | 华为技术有限公司 | grid array package module and terminal |
| TWI726427B (en) * | 2019-09-27 | 2021-05-01 | 友達光電股份有限公司 | Device substrate |
-
2004
- 2004-04-06 CN CN 200410033544 patent/CN1681378A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110741472A (en) * | 2017-08-03 | 2020-01-31 | 华为技术有限公司 | grid array package module and terminal |
| TWI726427B (en) * | 2019-09-27 | 2021-05-01 | 友達光電股份有限公司 | Device substrate |
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