CN1677649A - 具保护晶粒功用的半导体元件 - Google Patents

具保护晶粒功用的半导体元件 Download PDF

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CN1677649A
CN1677649A CNA2004100296933A CN200410029693A CN1677649A CN 1677649 A CN1677649 A CN 1677649A CN A2004100296933 A CNA2004100296933 A CN A2004100296933A CN 200410029693 A CN200410029693 A CN 200410029693A CN 1677649 A CN1677649 A CN 1677649A
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张荣骞
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XIANGHU CO Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Led Device Packages (AREA)

Abstract

本发明公开了一种具保护晶粒功用的半导体元件,其主要具有一可为金属或绝缘材质制成的骨架,于该骨架预设的晶粒植入孔中植入晶粒,并填入绝缘材固定晶粒,于骨架一侧面绝缘设有图案化的铜线路,该晶粒预设的接点朝向铜线路,且自以接点设导体电性连接铜线路,藉以构成一具有保护晶粒功能的半导体元件。

Description

具保护晶粒功用的半导体元件
技术领域
本发明涉及一种具保护晶粒功用的半导体元件,尤指一种利用晶粒埋入式结构应用于如:感测元件、发光二极管(LED)或其它半导体元件产品,并使其具备保护晶粒功用的半导体元件。
背景技术
目前如光感测元件、发光二极管、…等半导体元件的构装,大都是将晶粒固着一可为基板(substrate)或导线架(lead frame)的载体(carrier)一侧,次以打线接合手段使晶粒上预设的接点电性连接载体上预设的线路的对应处,续于载体上固设包围晶粒的胶体,于晶粒上方固设透明材以及切割成形等步骤,完成该具有预定功能的半导体元件产品。
前揭半导体元件的构装结构,虽可提供晶粒保护及线路重布功能,但因该半导体元件的结构设计,使其搭配应用的制程技术均是沿袭传统式构装技术,无法作出较具技术性的突破。
发明内容
本发明要解决的技术问题是提供一种具保护晶粒功用的半导体元件,藉此元件的构装结构,使其可结合电路板的制程技术来完成制造,跳脱既有传统构装技术的范畴,并为其元件中的晶粒提供更好的防护效果。
为此,本发明提出了一种具保护晶粒功用的半导体元件,其主要具有一预设晶粒植入孔的骨架,该晶粒植入孔中植入晶粒并填入绝缘材固定该晶粒,该骨架一侧面绝缘设有图案化的铜线路,该晶粒预设的接点朝向铜线路,并自接点设导体电性连接铜线路的对应点,藉以构成一半导体元件。
如上所述的具保护晶粒功用的半导体元件,该晶粒相对于接点的另侧具有功能面,于骨架相对于铜线路的另侧面封设透明材,覆盖于该晶粒的功能面外侧。
如上所述的具保护晶粒功用的半导体元件,该骨架为导电金属材质制成的板体,该骨架与其上图案化铜线路之间设有绝缘层,设于该晶粒顶面各接点上的导体通过绝缘层连接铜线路。
如上所述的具保护晶粒功用的半导体元件,该骨架为非金属绝缘硬质板体。
如上所述的具保护晶粒功用的半导体元件,各电极接点上焊设可导电的焊点凸块。
如上所述的具保护晶粒功用的半导体元件,设于骨架底面覆盖晶粒功能面外侧的透明材为玻璃。
如上所述的具保护晶粒功用的半导体元件,设于骨架底面覆盖晶粒功能面外侧的透明材为透明胶。
如上所述的具保护晶粒功用的半导体元件,该骨架厚度等于晶粒厚度。
如上所述的具保护晶粒功用的半导体元件,该骨架厚度大于晶粒厚度。
依上述构造可知,本发明提出的具保护晶粒功用的半导体元件,该具保护晶粒功用的半导体元件主要具有一可为金属或绝缘材质制成的骨架,于该骨架预设的晶粒植入孔中植入晶粒,并填入绝缘材固定晶粒,于骨架一侧面绝缘设有图案化的铜线路,该晶粒预设的接点朝向铜线路,并自该接点设导体电性连接铜线路,藉以构成一具有保护晶粒功能的半导体元件,另利用该半导体元件的构装结构,使其可利用现有电路板制造技术来完成,让该半导体元件制造不需受限于传统构装技术的限制。
附图说明
图1是本发明半导体元件的构装结构平面示意图。
图2A-J是本发明可应用的制程方法流程图。
附图标号说明:
10、骨架     11、晶粒植入孔  12、晶粒
121、功能面  13、绝缘材      14、铜线路
141、薄铜板  142、导通孔     15、导体
16、绝缘漆   17、透明材      18、凸块
19、胶带
具体实施方式
有关本发明的具保护晶粒功用的半导体元件具体实施例,请配合参阅图1所示,其主要具有一预设有晶粒植入孔11的骨架10,该晶粒植入孔11中植入晶粒12,该骨架10厚度可等于或略大于晶粒12厚度,该晶粒12并与骨架10底面平齐,该晶粒植入孔11内另填入绝缘材13固定晶粒12,其中,当骨架10厚度等于晶粒12厚度时,该绝缘材13包覆晶粒12周边,当骨架10厚度略大于晶粒12厚度时,则该绝缘材13包覆晶粒12周边及其顶面,该骨架10顶面绝缘设有图案化的铜线路14,该铜线路14上设有图案化绝缘漆16,使该铜线路14形成图案化的电极接点,各电极接点上可进一步焊设可导电的焊点凸块18,作为外部连接之用,另自该晶粒12顶面预设的各接点上分别设导体15连接图案化铜线路14对应点,使晶粒12上的接点透过铜线路14作线路重布,而构成一具有预定功能的半导体元件。
前述中,该晶粒12可为具有光感测功能的感测晶粒或为发光二极管晶粒,该晶粒12的光感测面或发光面等功能面121朝下与骨架10底面平齐,又,该骨架10底面尚可封设一可为玻璃或透明胶之类的透明材17,覆盖于晶粒12的功能面121外侧保护该晶粒12。
前述中,该晶粒12为不具功能面的晶粒时,该晶粒12底面与骨架10底面平齐,外露出于骨架10,可外接散热装置,以利晶粒作用时产生的高温散发之用。
前述中,该骨架10可使用铜材质或其它可导电金属材质制成的板体,或可为非金属绝缘硬质板体,如图1所示,其使用铜质骨架10,并于该铜骨架10与其上图案化铜线路14之间设有绝缘层15,设于该晶粒12顶面各接点上的导体15是贯穿通过绝缘材13连接铜线路14。
本发明以前揭半导体元件构装结构,即可结合现行电路板制造技术来进行量产制造,其具体可行的制造方法是采用图1所示的元件上下相反方向进行,请配合参阅图2A-J所示,其制造步骤可为:
取用裸铜板作为骨架10,并以钻孔或蚀刻等加工手段作出复数预定形状的晶粒植入孔11及工具孔,该工具孔可作为对位之用,如图2A所示;
取复数晶粒12分别定位于铜骨架10的晶粒植入孔11中,其中可先将胶带19贴合于骨架10底面作为晶粒12的载体,提供晶粒植入孔11内的晶粒12固定其上,其中晶粒12的功能面12黏着于胶带19上,如图2B所示;
以薄铜板141结合绝缘材13热压合于铜骨架10顶面,并使绝缘材13填入晶粒植入孔11中包覆固定晶粒12,如图2C所示,前述压合时,可配合抽真空手段,用以确保晶粒植入孔11中以免残留空气,另藉由骨架10对晶粒12的支撑及保护,于此压合过程中,确保晶粒12免于被破坏;
以雷射钻孔手段自薄铜板141钻设延伸至晶粒12接点处的导通孔142,再以化学铜或铜电镀手段令导通孔142形成连接薄铜板141与晶粒12接点间的铜导体15,如图2D所示;
以影像移转手段使薄铜板141形成图案化的铜线路14,如图2E所示;
于铜线路14上设图案化绝缘漆16,使铜线路形成显露于绝缘漆16的图案化电极接点,如图2F所示;
去除铜骨架10侧面胶带19,显露出晶粒12功能面121,如图2G所示;
于铜骨架10侧面固设玻璃或透明胶等透明材17,覆盖于晶粒12功能面121外侧,如图2H所示;
于铜线路14各电极接点焊设焊点凸块18,如图2I所示;以及以切割手段将其分割成数个各具晶粒12的元件成品,如图2J所示。
前揭半导体元件制程步骤中,除先对裸铜板加工出晶粒植入孔及工具孔,再贴胶带,用以提供晶粒植入于裸铜板预设的晶粒植入孔等步骤外,尚可以先于裸铜板侧面压合胶带,再以蚀刻手段成形出图案化的晶粒植入孔及对位工具孔后,提供晶粒植入于裸铜板预设的晶粒植入孔的步骤来取代。
由以上说明中可以了解,本发明以其创新的半导体元件构装结构,可利用晶粒埋入骨架中,藉由骨架提供一良好的防护,同时,可让该半导体元件可运用既有的电路板制造来量产制造,跳脱传统构装技术的范畴,而提供一项具产业利用价值的发明。

Claims (9)

1.一种具保护晶粒功用的半导体元件,其主要具有一预设晶粒植入孔的骨架,该晶粒植入孔中植入晶粒并填入绝缘材固定该晶粒,该骨架一侧面绝缘设有图案化的铜线路,该晶粒预设的接点朝向铜线路,并自接点设导体电性连接铜线路的对应点,藉以构成一半导体元件。
2.如权利要求1所述的具保护晶粒功用的半导体元件,其特征在于:该晶粒相对于接点的另侧具有功能面,于骨架相对于铜线路的另侧面封设透明材,覆盖于该晶粒的功能面外侧。
3.如权利要求2所述的具保护晶粒功用的半导体元件,其特征在于:该骨架为导电金属材质制成的板体,该骨架与其上图案化铜线路之间设有绝缘层,设于该晶粒顶面各接点上的导体通过绝缘层连接铜线路。
4.如权利要求2所述的具保护晶粒功用的半导体元件,其特征在于:该骨架为非金属绝缘硬质板体。
5.如权利要求1、2、3或4所述的具保护晶粒功用的半导体元件,其特征在于:各电极接点上焊设可导电的焊点凸块。
6.如权利要求2、3或4所述的具保护晶粒功用的半导体元件,其特征在于:设于骨架底面覆盖晶粒功能面外侧的透明材为玻璃。
7.如权利要求2、3或4所述的具保护晶粒功用的半导体元件,其特征在于:设于骨架底面覆盖晶粒功能面外侧的透明材为透明胶。
8.如权利要求1、2或3所述的具保护晶粒功用的半导体元件,其特征在于:该骨架厚度等于晶粒厚度。
9.如权利要求1、2、3或4所述的具保护晶粒功用的半导体元件,其特征在于:该骨架厚度大于晶粒厚度。
CNA2004100296933A 2004-03-30 2004-03-30 具保护晶粒功用的半导体元件 Pending CN1677649A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206479A (zh) * 2015-03-31 2016-12-07 南茂科技股份有限公司 四方扁平无引脚封装结构与导线架结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206479A (zh) * 2015-03-31 2016-12-07 南茂科技股份有限公司 四方扁平无引脚封装结构与导线架结构

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