CN1667950A - High-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger - Google Patents

Abstract

A high and low clock signal amplitude pre-fill CMOS trigger characterizes in connecting substrates of all PMOS tubes in the first stage latch of SAFF-CD conditional pre-fill structure driven by the low voltage amplitude clock signals to the power supply directly, the same time when omitting the only grating connected with NMOS tubes of the same supply end, two coupled NMOS tubes at the drain are removed, so that the drain of NMOS tubes with the substrate and the source all connected with the earth is connected with the drain of two remained NMOS tubes, finally, two compensated output ends of the first state latch are connected with two mutual independent single clock phase latches with the same circuit parameters.

Description

High-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger

Technical field

" high-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger " direct applied technical field is the low-power consumption flip-flop circuit design of adopting low-clock signal excursion to drive.The circuit that proposes is the Low-Power CMOS flip-flop circuit unit that a class is applicable to low amplitude of oscillation clock signal networks technology.

Background technology

Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.Based on present integrated circuit (IC) design style, in the large scale digital Circuits System, the ratio that the energy of clock network consumption accounts for the total power consumption of entire circuit remains high always; Wherein, under the circuit working state, (trigger: energy Flip-Flop) becomes the important source of clock network energy consumption again in clock interconnection gauze and sequence circuit unit in consumption, and the power consumption ratio of the two has ever-increasing trend (to see document David E.Duarte, N.Vijaykrishnan, and Mary Jane Irwin, " A Clock Power Model to Evaluate Impact of Architecturaland Technology Optimizations ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, no.6, pp.844-855, December 2002.).

CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.Wherein dynamic power consumption accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit node _DynamicIt is this node load capacitor C _L, supply voltage V _DDVoltage swing V with this node _SwingFunction, that is:

P _Dynamic＝C _LV _DDV _Swingfα?????????????????????(1)

Wherein, f is the operating frequency of circuit, and α is the signal activity.From formula (1), as seen, reduce α, C _L, V _DDAnd V _SwingAll can reduce the dynamic power consumption of circuit.Be different from the data-signal gauze, the clock cable netting gear has the characteristics of big interconnection line parasitic capacitance and high signal activity, by reducing the voltage signal amplitude of oscillation V of clock signal gauze _SwingCan be at the energy that guarantees to reduce under the condition of circuit performance to consume on the clock interconnection line.The flip-flop circuit unit is widely used in integrated circuit (IC) design.Be the flip-flop circuit cell schematics as shown in Figure 1.Be illustrated in figure 2 as the traditional flip-flop circuit unit basic circuit structure that is widely used in the design of digital circuit standard cell lib, here with complementary output in the Grace 0.15 μ m technology digital standard cell library, the flip-flop circuit unit F FDHD1X that rising edge triggers is example explanation (seeing document Manual of " VeriSilicon GSMC 0.15 μ m High-DensityStandard Cell Library Databook ").The main feature of sort circuit structure is that circuit structure is fairly simple, but is not suitable for the design of low-clock signal excursion clock network system, because clock signal upset each time all can cause the upset of circuit internal node, circuit power consumption is bigger simultaneously.H.Kawaguchi propose a kind of flip-flop circuit RCSFF that can adopt low-voltage amplitude of oscillation clock signal to drive (see document H.Kawaguchi and T.Sakurai: " A Reduced Clock-Swing Flip-Flop (RCSFF) for 63%Power Reduction " ', IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.33, NO.5, MAY1998, PP.807-811.), but the problem of sort circuit is when clock signal low level each time, extra energy consumption can be caused to the precharge of circuit internal node in the capital.On the basis of RCSFF circuit, the flip-flop circuit SAFF_CP that Y.Zhang proposes a kind of low-voltage amplitude of oscillation clock signal driving of condition presetting construction (sees document Y.Zhang, H.Yang, and H.Wang, " Low clock-swing conditional-precharge flip-flop for more than 30%power reduction; " Electron.Lett., vol.36, no.9, pp.785-786, Apr.2000.), as shown in Figure 3.The maximum characteristics of this flip-flop circuit are can be operated under the low-voltage oscillation amplitude driving conditional except keeping; Simultaneously, if the flip-flop circuit input remains unchanged when the clock signal low level, circuit can be to its internal node precharge between the clock signal low period.The employing of this technology greatly reduces the power consumption of flip-flop circuit itself.But, the problem that the SAFF_CP circuit exists is, because the output latch circuit has adopted cross-couplings NAND2 (NAND2: two input NAND gate) structure, can cause time-delay of flip-flop circuit output rising edge and trailing edge time-delay extremely asymmetric, bring potential problem for the use of circuit unit.Be illustrated in figure 4 as cross-couplings NAND2 latch circuit.With V _OutaOutput is an example, works as V _InaBe low level ' 0 ', simultaneously V _InbDuring for high level ' 1 ', signal is through NAND gate NAND2_a, makes V _OutaThe upset of generation rising edge; Work as V _InaBe high level ' 1 ', simultaneously V _InbDuring for low level ' 0 ', V _OutaUpset can be do not produced at once, but V will be waited until _OutbAt first be turned to high level ' 1 ', afterwards just can be at V _OutaThe upset of generation trailing edge.This shows, for the SAFF_CP circuit that adopts cross-couplings NAND2 latch circuit as output, output end signal produces the trailing edge upset and always has more the time-delay of a door than producing the rising edge upset, has therefore caused the circuit rising edge to delay time and the trailing edge asymmetric problem of delaying time.Simultaneously, because behind the SAFF_CP circuit employing condition presetting construction, NMOS pipe MN2 in the circuit, MN3 and MN4 become redundant transistor, have not only increased circuit power consumption, have also increased circuit internal node electric capacity simultaneously, have limited the operating rate of circuit.

Summary of the invention

When the objective of the invention is on the flip-flop circuit that the low-voltage amplitude of oscillation clock signal of existing condition presetting construction drives is the basis of SAFF_CP circuit, to propose a kind of output end signal trailing edge upset and rising edge upset its delay time symmetry and settling time characteristic fine, the CMOS trigger of the low clock signal oscillation amplitude driving conditional precharging that the total time-delay of circuit is very little, as shown in Figure 5.The invention is characterized in: it contains:

First order latch, it comprises:

First or logical circuit, it is made up of as the NMOS pipe of the output of described logical circuit two its drain electrode backs in parallel, and wherein, the source electrode of a NMOS pipe connects clock signal clk, and grid meets data-signal D _bThe source electrode of another NMOS pipe and grid meet another data-signal D simultaneously; The substrate of these two NMOS pipes is ground connection all;

Second or logical circuit, it is made up of as the NMOS pipe of the output of described logical circuit two its drain electrode backs in parallel, and wherein, the source electrode of a NMOS pipe connects above-mentioned same clock signal clk, and grid meets above-mentioned same data-signal D; And the source electrode of another NMOS pipe and grid all meet above-mentioned same data-signal D simultaneously _b, the grid of described NMOS pipe oppositely links to each other with first or the D signal end of logical circuit through an inverter; The substrate of these two NMOS pipes is ground connection all;

First PMOS pipe parallel circuits, the PMOS pipe that it connects power end after by two its source electrode parallel connections is formed in parallel, and wherein, the grid of first PMOS pipe connects above-mentioned first or the output of logical circuit; The substrate of these two PMOS pipes all connects above-mentioned same power end;

First NMOS pipe, its substrate ground connection, and the grid of second PMOS pipe in grid and above-mentioned first PMOS pipe parallel circuits links to each other afterwards as second output of described first order latch, represent with Y, the source electrode of described first NMOS pipe then links to each other with another sys node of above-mentioned first PMOS pipe parallel circuits afterwards as first output of described first order latch, represents with X;

Second PMOS pipe parallel circuits, the PMOS pipe that it connects above-mentioned same power end after by two other its source electrode parallel connection is formed in parallel, wherein, the grid of first PMOS pipe connects above-mentioned second or the output of logical circuit, and the substrate of two PMOS pipes all connects above-mentioned same power end;

Second NMOS pipe, its substrate ground connection, and the grid of second PMOS pipe in grid and above-mentioned second PMOS pipe parallel circuits links to each other with first output of the above-mentioned first order latch of representing with X after linking to each other again; The source electrode of described second NMOS pipe with link to each other with second output of the above-mentioned first order latch of representing with Y again after another parallel connected end of above-mentioned second PMOS parallel circuits links to each other;

Another source electrode and substrate be the NMOS pipe of ground connection all, and its grid connects above-mentioned same clock signal clk, and its drain electrode links to each other with the drain electrode of above-mentioned first, second two NMOS pipes simultaneously;

Second level latch, it is separate and have after the single clock phase latch parallel connection of same circuits parameter the more above-mentioned same power end of a termination and constitute behind the other end common ground by first, second two, wherein, each single clock phase latch is in series by a PMOS pipe, a NMOS pipe and another NMOS pipe successively and constitutes, the substrate of all two PMOS pipes directly connects above-mentioned same power end, and the substrate of all 4 NMOS pipes is ground connection all; Connect first output of above-mentioned first order latch after wherein the grid of the grid of a PMOS pipe in second single clock phase latch and another NMOS pipe described in this single clock phase latch links to each other, the source electrode that is positioned at a middle NMOS pipe of series circuit in this single clock phase latch connects an inverter, the output of this inverter is the output of above-mentioned trigger, uses Q _bExpression; Wherein, after linking to each other, the grid of described another NMOS pipe in the grid of a PMOS pipe in the first single clock phase latch and this single clock phase latch meets second output Y of above-mentioned first order latch, the source electrode that is positioned at a middle NMOS pipe of series circuit in this first single clock phase latch connects another inverter, the output of this inverter is the output of above-mentioned trigger, is expressed as Q; The grid that in above-mentioned first, second two single clock phase latch two are positioned at the NMOS pipe in the middle of the series circuit separately all connects above-mentioned same clock signal clk.

2. high-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger according to claim 1 is characterized in that:

In the latch of the described second level, output signal is that inverter input and the output signal of Q is Q _bThe inverter input between be connected with a holding circuit, it is formed by two inverter reverse parallel connections.

The invention has the beneficial effects as follows: with traditional digital standard unit triggers device circuit FFDHD1X, RCSFF flip-flop circuit and SAFF_CP flip-flop circuit are relatively, the SAFF_CP_SFL trigger that patent of the present invention proposes can be saved and is higher than 25% power consumption under identical test condition.And the structure of circuit obtains very big simplification, and circuit area is less, the circuit delay characteristic, and settling time and metastable state time response also have advantage clearly.The circuit engineering that is proposed is suitable as the digital circuit standard cell and is applied in the low power consumption integrated circuit design very much.

Description of drawings

Fig. 1. the flip-flop circuit cell schematics, D is the data-signal input, CLK is a clock signal input terminal, Q and Q _bBe the complementary signal output;

The flip-flop circuit unit F FDHD1X circuit structure diagram that complementary output and rising edge trigger in Fig. 2 .Grace 0.15 μ m technology digital standard cell library;

Fig. 3 .SAFF_CP flip-flop circuit structure chart;

Fig. 4. cross-couplings NAND2 flip-latch circuit structure figure;

Fig. 5. SAFF_CP_SFL flip-flop circuit structure chart of the present invention.

Embodiment

The technical scheme that the present invention solves its technical problem is: the high-speed low clock signal oscillation amplitude driving conditional precharging trigger SAFF_CP_SFL that the present invention proposes, as shown in Figure 5.The SAFF_CP_SFL trigger has the characteristics that can adopt low amplitude of oscillation clock signal driving and employing condition presetting technology to reduce the power consumption of flip-flop circuit own simultaneously, and, can guarantee the complementary output end Q and the Q of SAFF_CP_SFL trigger because the complementary output end of first order latch is connected respectively to two independently and have on the single clock phase latch of same circuits parameter _bCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.With respect to the SAFF_CP flip-flop circuit, SAFF_CP_SFL flip-flop circuit structure is simpler, has reduced by an extra high-voltage power supply line V _Well(to PMOS pipe MP1, MP2 provides substrate biasing, V _Well＞V _DD), help using and designing of circuit more; Simultaneously, owing to adopt the condition presetting control structure, can remove NMOS pipe MN2 redundant in the original SAFF_CP circuit, MN3 and MN4 have reduced circuit internal node electric capacity, thereby have reduced power consumption, have improved the operating rate of circuit.

The SAFF_CP_SFL trigger adopts low amplitude of oscillation clock signal to drive, and can effectively reduce the online power consumption of clock line that interconnects.Simultaneously, the condition presetting control circuit that the flip-flop circuit employing is controlled by input data signal D is finished the condition presetting process to the circuit internal node, has reduced the power consumption of trigger itself.Be different from the RCSFF trigger (see document H.Kawaguchi and T.Sakurai: " A Reduced Clock-Swing Flip-Flop (RCSFF) for 63%Power Reduction " ', IEEEJOURNAL OF SOLID-STATE CIRCUITS, VOL.33, NO.5, MAY 1998, PP.807-811.), clock signal clk and input data signal D composition or logic also are connected to the grid that PMOS manages MP1, simultaneously clock signal clk and input data signal D _bComposition or logic also are connected to the grid that PMOS manages MP2.With respect to the SAFF_CP flip-flop circuit, two or logical circuit are not only finished the control action to the condition presetting electricity, simultaneously also as the input control circuit of data-signal D.When CLK is a high level, MP1 and MP2 end, and NMOS pipe MN1 conducting if this moment, input data signal D was a high level, because the driving force of node Y is higher than nodes X, makes the nodes X discharge, and it is constant that positive feedback makes node Y keep high level.This moment, second level latch was driven by nodes X and Y, and because CLK is a high level, NMOS pipe MN2 and MN3 conducting make that trigger complementary output end Q is a high level, Q _bBe low level.When CLK is the low level while, if input signal D still keeps high level, the MP1 remain off can not carry out precharge to nodes X; At this moment, for second level latch, because CLK is a low level, MN2 and MN3 end, and the complementary output signal of trigger also can be maintained.When CLK is the low level while, if input signal D is turned to low level, the MP1 conducting is to the precharge of X node; And when next rising edge clock arrived, because the driving force of nodes X is higher than node Y, node Y discharge, positive feedback made nodes X keep high level and drive second level latch, make that trigger complementary output end Q is a low level, Q _bBe high level.The output node X of first order latch and Y are connected respectively to two independently and have on the single clock phase latch of same circuits parameter, this method of attachment not only can guarantee when CLK is low level, and the complementary output end of trigger is can the inhibit signal level constant; Simultaneously, can guarantee the complementary output end Q and the Q of SAFF_CP_SFL trigger _bCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.Also have the metastable state effect for flip-flop circuit, when input data signal D when saltus step takes place very nearby in the distance rising edge clock signal, can cause from clock signal clk to output Q or Q _bTime-delay increase greatly, settling time and the time-delay sum of increase of definition flip-flop circuit are the metastable state time, the time-delay sum of circuit is total time-delay of circuit under metastable state time and the general situation.Simulation result by circuit can be found, the trigger SAFF_CP_SFL that the present invention proposes, can remove (as shown in Figure 3) redundant NMOS pipe MN2 in the original SAFF_CP circuit, MN3 and MN4, reduced circuit internal node electric capacity, thereby reduced power consumption, improved the operating rate of circuit, more superior settling time and metastable state time performance have been arranged.

Essential features of the present invention is: at first, circuit can adopt low amplitude of oscillation clock signal to drive, and has effectively reduced in the clock network system to consume in the online power consumption of clock interconnection line.The condition presetting control circuit that the flip-flop circuit employing is controlled by input data signal D is finished the condition presetting process to the circuit internal node, has reduced the power consumption of trigger itself.The condition presetting process of first order latch cooperates second level latch, guarantees that circuit is a low level and during not to X or the precharge of Y node at CLK, and the complementary output end of trigger is can the inhibit signal level constant.The output node X of first order latch and Y are connected respectively to two independently and have on the single clock phase latch of same circuits parameter, and this method of attachment can guarantee the complementary output end Q and the Q of SAFF_CP_SFL trigger _bCan realize the rising edge time-delay and the trailing edge time-delay of symmetry, and have more superior settling time and metastable state time performance.With respect to the SAFF_CP flip-flop circuit, SAFF_CP_SFL flip-flop circuit structure is simpler, has reduced by an extra high-voltage power supply line V _Well(to PMOS pipe MP1, MP2 provides substrate biasing, V _Well＞V _DD), help using and designing of circuit more; Simultaneously, owing to adopt the condition presetting control structure, can remove NMOS pipe MN2 redundant in the original SAFF_CP circuit, MN3 and MN4 have reduced circuit internal node electric capacity, thereby have reduced power consumption, have improved the operating rate of circuit.

For SAFF_CP_SFL trigger more proposed by the invention performance characteristics with respect to traditional flip-flop circuit FFDHD1X and trigger SAFF_CP, we adopt Grace 1.5-V 0.15 μ m technology, use circuit simulation tools HSPICE that three kinds of circuit structures have been carried out the emulation comparative analysis.Table 1 is depicted as three kinds of flip-flop circuit dynamic power consumptions, and Leakage Current power consumption and normalization circuit area data are relatively.Clock signal input CLK is 100MHz in the emulation of circuit dynamic power consumption, 50% duty ratio square-wave signal, wherein the clock signal of FFDHD1X trigger connects normal signal amplitude of oscillation clock (0V-1.5V), and the clock signal of SAFF_CP and SAFF_CP_SFL trigger connects low signal amplitude of oscillation clock (0V-0.75V).Data-signal input D is 20MHz, 50% duty ratio square-wave signal (0V-1.5V).Flip-flop circuit output termination 20fF capacitive load.Circuit input signal end CLK and D connect low level in the emulation testing of leakage current power consumption, and the testing power supply electric current is also averaged.Circuit area is that standard is done normalized with FFDHD1X cellar area in the Grace 0.15um technology digital standard cell library.Dynamic power consumption and leakage current power consumption data unit are respectively microwatt (uW) and micromicrowatt spy (pW).

Table 1 trigger dynamic power consumption, leakage current power consumption, normalization circuit area are relatively

	Dynamic power consumption (uW)	Leakage Current power consumption (pW)	The normalization circuit area
				??FFDHD1X	????4.996	????584	????1.0
??SAFF_CP	????3.610	????1180	????0.8
				??SAFF_CP_SFL	????3.601	????838	????0.75

Table 2A, table 2B and table 2C are depicted as the relation that three kinds of flip-flop circuit time-delays change with circuit load.Three kinds of flip-flop circuits adopt identical circuit arrangement, and input signal change-over time is 0.104ns, and circuit load is 0.0001pF～0.3pF.The SAFF_CP_SFL flip-flop circuit has suitable substantially circuit delay with respect to traditional FFDHD1X trigger and the rising edge time-delay is basic identical with the trailing edge time-delay, does not consider the metastable state effect here.TQ and tQ _bRepresent the time-delay of in-phase output end, reversed-phase output respectively; RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Delay data unit is nanosecond (ns).

Table 2A FFDHD1X flip-flop circuit time-delay and load relationship

Input signal change-over time=0.104ns

Fan-out load (pF)	???????0.0001		???????0.02		????????0.1		????????0.2		????????0.3
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.23	?0.23	?0.334	?0.335	?0.694	?0.595	?1.14	?0.898	?1.59	?1.2
											????tQ b(ns)	0.293	?0.295	?0.383	?0.366	?0.74	?0.609	?1.19	?0.911	?1.64	?1.21

Table 2B SAFF_CP flip-flop circuit time-delay and load relationship

Fan-out load (pF)	??????0.0001		???????0.02		????????0.1		????????0.2		???????0.3
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.073	?0.123	?0.174	?0.175	?0.560	?0.373	?0.992	?0.583	?1.434	?0.817
											????tQ b(ns)	0.073	?0.125	?0.174	?0.178	?0.541	?0.360	?0.994	?0.604	?1.440	?1.033

Table 2C SAFF_CP_SFL flip-flop circuit time-delay and load relationship

Fan-out load (pF)	???????0.0001		???????0.02		????????0.1		????????0.2		????????0.3
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.067	?0.114	?0.166	?0.175	?0.559	?0.357	?0.989	?0.602	?1.429	?0.808
											????tQ b(ns)	0.067	?0.114	?0.165	?0.174	?0.556	?0.355	?0.986	?0.601	?1.426	?0.807

Table 3A, table 3B and table 3C are depicted as three kinds of flip-flop circuit time-delays and the input signal relation of change-over time.Three kinds of flip-flop circuits adopt identical circuit arrangement, and circuit load is 0.02pF.The SAFF_CP_SFL flip-flop circuit has less circuit delay with respect to traditional FFDHD1X trigger and the rising edge time-delay is basic identical with the trailing edge time-delay, does not consider the metastable state effect here.TQ and tQ _bRepresent the time-delay of in-phase output end, reversed-phase output respectively; RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Delay data unit is nanosecond (ns).

Table 3A FFDHD1X flip-flop circuit time-delay and change-over time relation

Circuit load=0.02pF

Import change-over time (ns)	??????0.0228		???????0.104		???????0.507		????????1		????????1.5
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.309	?0.311	?0.334	?0.335	?0.39	?0.394	?0.433	?0.438	?0.461	?0.471
											????tQ b(ns)	0.359	?0.341	?0.383	?0.366	?0.443	?0.422	?0.486	?0.465	?0.518	?0.493

Table 3B SAFF_CP flip-flop circuit time-delay and change-over time relation

Import change-over time (ns)	??????0.0228		???????0.104		???????0.507		????????1		????????1.5
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.163	?0.166	?0.174	?0.175	?0.187	?0.176	?0.163	?0.152	?0.124	?0.100

????tQ b(ns)

????0.163

?0.168

?0.174

?0.178

?0.188

?0.179

?0.167

?0.155

??0.119

??0.115

Table 3C SAFF_CP_SFL flip-flop circuit time-delay and change-over time relation

Import change-over time (ns)	??????0.0228		???????0.104		??????0.507		????????1		????????1.5
											The hopping edge	RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL	?RISE	?FALL
????tQ(ns)	0.156	?0.165	?0.166	?0.175	?0.168	?0.170	?0.122	?0.139	?0.027	?0.114
											????tQ b(ns)	0.156	?0.165	?0.165	?0.174	?0.172	?0.167	?0.137	?0.149	?0.104	?0.100

The settling time of flip-flop circuit and metastable state time are the important indicators that influences the flip-flop circuit performance.In emulation testing, compared trigger SAFF_CP and SAFF_CP_SFL, input signal change-over time is 0.05ns, circuit load is 0.02pF.Simulation result sees Table 4, is settling time and the metastable state time performance of circuit output end Q.By simulation result as seen, the SAFF_CP_SFL trigger has more superior performance.

Table 4 trigger output Q settling time and metastable state time ratio are

		Settling time (ps)	The metastable state time (ps)	Total time-delay (ps)
					??SAFF_CP	The D rising edge	????236	????280	??447
The D trailing edge	????265	????350	??523
				??SAFF_CP_SFL		The D rising edge	????80	????100	??259.73
The D trailing edge	????108	????173	??350.13

Claims (2)

1. high-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger is characterized in that, it contains: first order latch, and it comprises:

First or logical circuit, it is made up of as the NMOS pipe of the output of described logical circuit two its drain electrode backs in parallel, and wherein, the source electrode of a NMOS pipe connects clock signal clk, and grid meets data-signal D _bThe source electrode of another NMOS pipe and grid meet another data-signal D simultaneously; The substrate of these two NMOS pipes is ground connection all;

Second or logical circuit, it is made up of as the NMOS pipe of the output of described logical circuit two other its drain electrode back in parallel, and wherein, the source electrode of a NMOS pipe connects above-mentioned same clock signal clk, and grid meets above-mentioned same data-signal D; And the source electrode of another NMOS pipe and grid all meet above-mentioned same data-signal D simultaneously _b, the grid of described NMOS pipe oppositely links to each other with first or the D signal end of logical circuit through an inverter; The substrate of these two NMOS pipes is ground connection all;

First PMOS pipe parallel circuits, the PMOS pipe that it connects power end after by two its source electrode parallel connections is formed in parallel, and wherein, the grid of first PMOS pipe connects above-mentioned first or the output of logical circuit; The substrate of these two PMOS pipes all connects above-mentioned same power end;

First NMOS pipe, its substrate ground connection, and the grid of second PMOS pipe in grid and above-mentioned first PMOS pipe parallel circuits links to each other afterwards as second output of described first order latch, represent with Y, the source electrode of described first NMOS pipe then links to each other with another sys node of above-mentioned first PMOS pipe parallel circuits afterwards as first output of described first order latch, represents with X;

Second PMOS pipe parallel circuits, the PMOS pipe that it connects above-mentioned same power end after by two other its source electrode parallel connection is formed in parallel, wherein, the grid of first PMOS pipe connects above-mentioned second or the output of logical circuit, and the substrate of two PMOS pipes all connects above-mentioned same power end;

Second NMOS pipe, its substrate ground connection, and the grid of second PMOS pipe in grid and above-mentioned second PMOS pipe parallel circuits links to each other with first output of the above-mentioned first order latch of representing with X after linking to each other again; The source electrode of described second NMOS pipe with link to each other with second output of the above-mentioned first order latch of representing with Y again after another parallel connected end of above-mentioned second PMOS parallel circuits links to each other;

Another source electrode and substrate be the NMOS pipe of ground connection all, and its grid connects above-mentioned same clock signal clk, and its drain electrode links to each other with the drain electrode of above-mentioned first, second two NMOS pipes simultaneously;

Second level latch, it is separate and have after the single clock phase latch parallel connection of same circuits parameter the more above-mentioned same power end of a termination and constitute behind the other end common ground by first, second two, wherein, each single clock phase latch is in series by a PMOS pipe, a NMOS pipe and another NMOS pipe successively and constitutes, the substrate of all two PMOS pipes directly connects above-mentioned same power end, and the substrate of all 4 NMOS pipes is ground connection all; Connect first output of above-mentioned first order latch after wherein the grid of the grid of a PMOS pipe in second single clock phase latch and another NMOS pipe described in this single clock phase latch links to each other, the source electrode that is positioned at a middle NMOS pipe of series circuit in this single clock phase latch connects an inverter, the output of this inverter is the output of above-mentioned trigger, uses Q _bExpression; Wherein, after linking to each other, the grid of described another NMOS pipe in the grid of a PMOS pipe in the first single clock phase latch and this single clock phase latch meets second output Y of above-mentioned first order latch, the source electrode that is positioned at a middle NMOS pipe of series circuit in this first single clock phase latch connects another inverter, the output of this inverter is the output of above-mentioned trigger, is expressed as Q; The grid that in above-mentioned first, second two single clock phase latch two are positioned at the NMOS pipe in the middle of the series circuit separately all connects above-mentioned same clock signal clk.

2. high-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger according to claim 1 is characterized in that:

In the latch of the described second level, output signal is that inverter input and the output signal of Q is Q _bThe inverter input between be connected with a holding circuit, it is formed by two inverter reverse parallel connections.

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