CN1641795A - Method for verifying testing ROM - Google Patents

Method for verifying testing ROM Download PDF

Info

Publication number
CN1641795A
CN1641795A CN 200410015919 CN200410015919A CN1641795A CN 1641795 A CN1641795 A CN 1641795A CN 200410015919 CN200410015919 CN 200410015919 CN 200410015919 A CN200410015919 A CN 200410015919A CN 1641795 A CN1641795 A CN 1641795A
Authority
CN
China
Prior art keywords
rom
trom
storage unit
test
checksum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 200410015919
Other languages
Chinese (zh)
Other versions
CN100421183C (en
Inventor
蒋英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Integrated Circuit Co Ltd
Original Assignee
Shanghai Huahong Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Integrated Circuit Co Ltd filed Critical Shanghai Huahong Integrated Circuit Co Ltd
Priority to CNB2004100159194A priority Critical patent/CN100421183C/en
Publication of CN1641795A publication Critical patent/CN1641795A/en
Application granted granted Critical
Publication of CN100421183C publication Critical patent/CN100421183C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention discloses a method to identify and test ROM. By using the method, the speed and accuracy of identifying and testing ROM would improved. It pre-distributes four storage unit in the testing ROM to store zero complement of the high bit and the low bit of the summation of the testing ROM, and complementing the content of the content in the two storages unit that store the high bit and zero complement of high bit and the content of the two storage units that store low bit and the low bit zero complement. Compilation identification program would calculate sum of the binary code of testing ROM. Its high bit and the low bit would be stored to the storage unit and its zero complement would be stored to the corresponding storage unit. Finally, totalizing the binary code by the program after being modified by compilation and identifying whether the content in testing ROM is right by the summarization.

Description

The validation test method of ROM
Technical field
The present invention relates to a kind of verification method, especially relate to the method for validation test usefulness ROM in the IC design.
Background technology
At present, at the IC design field, ROM checking is general, and what adopt is that the method for summation is verified, that is: relatively the content in all ROM cell and whether with all the elements of expection and equate.For TROM (test use ROM), program can in TROM, distribute two unit store TROM with a high position with low level so that compare when becoming survey and test oneself.And this program itself can be sued for peace in the unit of all interior TROM to comprising these two unit.That is: that establish TROM and be stored in variable TROM_CheckSum_High and TROM_CheckSum_Low, because these two values were exactly two unit among the TROM originally, in to the TROM summation, also comprise summation to these two unit, if the value of these two unit changes, the checksum of TROM and also can changing, simultaneously, the checksum of TROM and change also can cause and the change of the value of these two unit among the TROM will form a kind of circulation like this.
How can ask soon but also accurately not only whole TROM's and? traditional way is to go to attempt with the linear way into of forcing, that is: estimate earlier TROM's and big probable value, it is inserted among TROM_CheckSum_High and the TROM_CheckSum_Low, and then to the TROM summation, with the value of obtaining and remove to revise TROM_CheckSum_High and TROM_CheckSum_Low again.Repeat above process, till to the last the value among the value of CheckSum and TROM_CheckSum_High and the TROM_CheckSum_Low is coincide.
Utilize this method, have very big randomness, data convergent speed has much relations with checking personnel's experience.And, because the mode that checking adopt to be attempted carries out, for manpower and time of checking personnel all be a kind of waste.
Summary of the invention
The objective of the invention is to above-mentioned deficiency, propose a kind of method with fair speed and accuracy verification test usefulness ROM at prior art.
Above-mentioned purpose of the present invention is achieved through the following technical solutions: at first, in testing, allocate four storage unit in advance with ROM, be used for respectively storing test with ROM's and a high position and the complement code of low level and high-order and low level, before the first compiling of proving program, the content complementation of two storage unit of the complement code that the order storage is high-order and high-order, the content complementation of two storage unit of the complement code of storage low level and low level; Afterwards, compile this proving program and to its binary code obtain the test with ROM and; Then respectively with itself and a high position and lower memory in storage that test is distributed among with ROM and a high position and the storage unit of low level in, and respectively its complement code is stored in pre-assigned storage among the test usefulness ROM and a high position and the storage unit of the complement code of low level in; At last, by compiling amended program and to the summation of its binary code, utilize the test obtained with ROM's and right value judge test with ROM with whether change, thereby whether validation test uses the content of ROM correct.
Compare with prior art, the present invention has following beneficial effect: because the present invention adopts the method for supplement, only need once just can obtain the TROM sum after the compiling.After inserting this value in the source program, summation after the compiling once more, should and certain and asked last time and equal.Like this, only need once compiling just to obtain the value of CheckSum, only need compiling once more, just verified the correctness of CheckSum, guaranteed the rapidity and the correctness of its checking.
Description of drawings
Fig. 1 is a synoptic diagram of asking checksum with linear into the method for forcing;
Fig. 2 is the present invention asks CheckSum with the supplement method a synoptic diagram;
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
As shown in Figure 1, when traditional linearity into method of forcing is asked checksum, estimate earlier TROM's and big probable value, it is inserted among TROM_CheckSum_High and the TROM_CheckSum_Low, and then to the TROM summation, with the value of obtaining and remove to revise TROM_CheckSum_High and TROM_CheckSum_Low again.Repeat above process, till to the last the value among the value of CheckSum and TROM_CheckSum_High and the TROM_CheckSum_Low is coincide.
As shown in Figure 2, for guarantee TROM's and storage unit in inserting TROM before and afterwards itself and can remain unchanged, two other storage unit of can in TROM, reallocate, be used for respectively storing preservation TROM's and complement code.Such as: establish the A unit be used for preserving TROM's and a high position, the B unit be used for preserving TROM's and low level.Simultaneously, distribute two storage unit C and D more in addition, the complement code that is used for storing A and B respectively makes the full F of A+C=, the full F of B+D=.
After program is finished, through compiling, according to its binary code, obtain TROM and.Such as obtain TROM's and a high position be that A ' low level is B '.Then, if with the value of A ' and B ' be filled into corresponding and a high position and the storage unit of low level in A and B go, according to the value of A ' and B ', revise value C ' and D ' among corresponding complement code storage unit C and the D simultaneously, make A '+C '=full F; B '+D '=full F.
According to this scheme, if these four unit and remain unchanged, just can guarantee TROM with constant.Can by the program revised of compiling and to its binary code sue for peace verify TROM with whether change.According to the method, can definitely guarantee for revising program later, TROM obtain with TROM in preserved and a high position and low level consistent.
During programming, no matter adopt which kind of language to realize that its basic skills is similar.With word length is that 32 processor is an example, as long as before concrete operation, following variable is carried out initialization like this:
Complement_TROM_CheckSum_High=0xffffffff;
Complement_TROM_CheckSum_Low=0xffffffff;
TROM_CheckSum_High=0;
TROM_CheckSum_Low=0;
After program is finished, compile this program, and to corresponding binary file ask once and, that suppose to obtain and high 32 be TROM_CheckSum_High1, low 32 is TROM_CheckSum_Low1, then if real TROM with insert corresponding storage unit, simultaneously the value of its complement code is also done corresponding change and gets final product.As follows:
TROM_CheckSum_High=TROM_CheckSum_High1;
TROM_CheckSum_Low=TROM_CheckSum_Low1;
Complement_TROM_CheckSum_High=
0xffffffff-TROM_CheckSum_High;
Complement_TROM_CheckSum_Low=
0xffffffff-TROM_CheckSum_Low;
Utilize this method, TROM's and necessarily before and after revising do not become, so TROM's and do not need to repeat again to obtain, this value just can be used as TROM's and right value verify TROM.As long as with the content addition of each unit among the TROM, the value that draws with TROM's and right value compare and can verify whether the content among the TROM correct.

Claims (1)

1, a kind of validation test method of ROM, it is characterized in that: at first, in testing, allocate four storage unit in advance with ROM, be used for respectively storing test with ROM's and a high position and the complement code of low level and high-order and low level, before the first compiling of proving program, the content complementation of two storage unit of the complement code that the order storage is high-order and high-order, the content complementation of two storage unit of the complement code of storage low level and low level; Afterwards, compile this proving program and to its binary code obtain the test with ROM and; Then respectively with itself and a high position and lower memory in storage that test is distributed among with ROM and a high position and the storage unit of low level in, and respectively its complement code is stored in pre-assigned storage among the test usefulness ROM and a high position and the storage unit of the complement code of low level in; At last, by compiling amended program and to the summation of its binary code, utilize the test obtained with ROM's and right value judge test with ROM with whether change, thereby whether validation test uses the content of ROM correct.
CNB2004100159194A 2004-01-17 2004-01-17 Method for verifying testing ROM Expired - Fee Related CN100421183C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100159194A CN100421183C (en) 2004-01-17 2004-01-17 Method for verifying testing ROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100159194A CN100421183C (en) 2004-01-17 2004-01-17 Method for verifying testing ROM

Publications (2)

Publication Number Publication Date
CN1641795A true CN1641795A (en) 2005-07-20
CN100421183C CN100421183C (en) 2008-09-24

Family

ID=34868141

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100159194A Expired - Fee Related CN100421183C (en) 2004-01-17 2004-01-17 Method for verifying testing ROM

Country Status (1)

Country Link
CN (1) CN100421183C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426219C (en) * 2006-12-20 2008-10-15 北京中星微电子有限公司 Data operating method and apparatus in integrated circuit
CN103853866A (en) * 2012-12-07 2014-06-11 上海华虹宏力半导体制造有限公司 Method and system for verifying ROM (Read Only Memory) code data graphs in aggregate data layout

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740925A (en) * 1985-10-15 1988-04-26 Texas Instruments Incorporated Extra row for testing programmability and speed of ROMS
CN1153572A (en) * 1994-07-14 1997-07-02 国民西敏寺银行 Testing of memory content
JP3603394B2 (en) * 1995-07-19 2004-12-22 富士通株式会社 Verification method and verification method in LSI development
JP2000030500A (en) * 1998-07-10 2000-01-28 Mitsubishi Electric Corp Nonvolatile semiconductor storage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426219C (en) * 2006-12-20 2008-10-15 北京中星微电子有限公司 Data operating method and apparatus in integrated circuit
CN103853866A (en) * 2012-12-07 2014-06-11 上海华虹宏力半导体制造有限公司 Method and system for verifying ROM (Read Only Memory) code data graphs in aggregate data layout
CN103853866B (en) * 2012-12-07 2016-12-21 上海华虹宏力半导体制造有限公司 The method of calibration of the ROM code datagraphic in total data domain and system

Also Published As

Publication number Publication date
CN100421183C (en) 2008-09-24

Similar Documents

Publication Publication Date Title
Proulx Programming patterns and design patterns in the introductory computer science course
US8417998B2 (en) Targeted black box fuzzing of input data
US20080270855A1 (en) Method For Detecting Memory Error
US20140019806A1 (en) Classifying processor testcases
Filliâtre Verifying two lines of C with Why3: an exercise in program verification
US20160378639A1 (en) Debugging using program state definitions
CN113672515A (en) WASM intelligent contract vulnerability detection method based on symbolic execution
CN110321457A (en) Access log resolution rules generation method and device, log analytic method and system
CN103793032B (en) Method and apparatus for determining electrification reset
CN108241632A (en) A kind of data verification method of data base-oriented Data Migration
CN103870383A (en) Test coverage statistical method and system based on JVM
US20120117550A1 (en) Method, computer program and device for providing security for intermediate programming code for its execution by a virtual machine
CN108694049B (en) Method and equipment for updating software
CN112185453A (en) Read interference test method and device, computer readable storage medium and electronic equipment
US20150088483A1 (en) Simulated component connector definition and connection process
CN1641795A (en) Method for verifying testing ROM
CN112181790B (en) Capacity statistical method and system of storage equipment and related components
CN105335141B (en) Graphic processing method and device
Buckley et al. Teaching software testing using data structures
CN116663489A (en) RTL module resetting method and device, electronic equipment and storage medium
US8554522B2 (en) Detection of design redundancy
CN105718617B (en) The reversed method for automatic modeling of Bus structural body tested automatically for Matlab
CN109087676A (en) A kind of programmed method and device of nonvolatile memory
US20160349317A1 (en) Method and apparatus for obtaining a maximally compressed verification test set
Kleine Büning et al. Refined Modularization for Bounded Model Checking Through Precondition Generation

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080924

Termination date: 20170117