CN1632681A - Manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of liquid crystal display device Download PDFInfo
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- CN1632681A CN1632681A CN 200510006490 CN200510006490A CN1632681A CN 1632681 A CN1632681 A CN 1632681A CN 200510006490 CN200510006490 CN 200510006490 CN 200510006490 A CN200510006490 A CN 200510006490A CN 1632681 A CN1632681 A CN 1632681A
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Abstract
It is a process method of LCD device, which comprises the following steps: to use one grating electrode as mask and to form first N type of LDD and second N type of LDD to the semi-conductive layer through the means of inclination drilling, wherein, the first and second LDD are separately connected with the active or leakage electrodes; likewise to use one grating electrode as mask to form third and fourth P type of LDD through inclination drilling means, wherein, the above third and fourth P type of LDD are separately connected with the above first and second N shape of LDD.
Description
Technical field
The present invention is relevant for a kind of formation method of liquid crystal indicator, and is particularly to a kind of low-doped drain (Lightly Doped Drain that has; The formation method of liquid crystal indicator LDD).
Prior art
In order to increase the aperture opening ratio of LCD, the raceway groove of low temperature polycrystalline silicon liquid crystal indicator must be dwindled, raceway groove is relatively along with dwindling, the result causes short-channel effect (Shortchannel effect), makes voltage can produce thermoelectronic effect (Hotelectron effect) when executive component.
Again because channel shortening, make depletion region (Depletion region) between being adjacent to source electrode and draining along with voltage-operated and more and more approaching, even link together.Relatively, it is serious and obvious that leakage current of source electrode and drain electrode (Leakage current) and punch through (Punch-through effect) also become thereupon, makes that degeneration of low temperature polycrystalline silicon liquid crystal indicator electrology characteristic and meeting are unstable.
Routine techniques is in the technology that forms LDD, need to use photoresistance or form gap (Spacer) and be used as the mask (Mask) that ion injects, therefore need be through being coated with, exposing, developing and the photoresistance removal, perhaps monox deposition, dry etching and the step that forms gap, can increase process complexity and manufacturing cost like this, reduce competitiveness of product greatly.
Therefore, industry is needed a kind of liquid crystal indicator technology of more simplifying and the liquid crystal indicator with low-doped drain of low cost of manufacture badly, and except can reducing thermoelectronic effect, leakage current and penetration effect, product is also more competitive.
Summary of the invention
One of fundamental purpose of the present invention is to provide the liquid crystal indicator of the low-doped drain of a kind of liquid crystal indicator technology of more simplifying and low cost of manufacture, makes product more competitive.
Another object of the present invention is to provide the liquid crystal indicator technology of a kind of N of having type LDD.
Another object of the present invention is to provide the liquid crystal indicator technology of a kind of P of having type LDD.
According to above-mentioned purpose, the invention provides a kind of manufacture method of liquid crystal indicator, the mask that directly uses grid (Gate electrode) to inject as ion is to form source/drain (source/drain); In addition, form N type LDD and P type LDD, and reach the position that changes LDD, as buried type LDD (Buried lightly doped drain) by changing different incident angles and energy with the method that tilts to inject (tilted implantation).
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
The accompanying drawing summary
Figure 1A shows the process section of the liquid crystal indicator with N type LDD in accordance with a preferred embodiment of the present invention to 1E;
Fig. 2 A shows process section according to the liquid crystal indicator with N type LDD of another preferred embodiment of the present invention to 2E;
Fig. 3 A shows process section according to the liquid crystal indicator with N type LDD of another preferred embodiment of the present invention to 3E;
Fig. 4 A shows process section according to the liquid crystal indicator with N type LDD of another preferred embodiment of the present invention to 4E;
Fig. 5 A shows the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 5G;
Fig. 6 A shows the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 6G;
Fig. 7 A shows the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 7G;
Fig. 8 A shows the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 8G.
Embodiment
In accordance with a preferred embodiment of the present invention, shown in Figure 1A to 1E, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 102 is provided, then, forms a cushion 104 on aforesaid substrate 102 surfaces, on above-mentioned cushion 104, form a semiconductor layer 110, on above-mentioned semiconductor layer 110, form a gate insulator 120 again, on above-mentioned gate insulator 120, form a gate electrode 130 then, shown in Figure 1A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 130, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 110, to form source/drain regions 140/150, shown in Figure 1B.Above-mentioned N type alloy ties up to about direction perpendicular to aforesaid substrate 102 surfaces and reaches between 1 * 10 with the energy between 10 to 20KeV
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 110.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 130, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 110, with the part overlapping N type doped regions of formation, and form N type LDD160 and 161 with above-mentioned source/drain regions 140/150, it is positioned at above-mentioned gate insulator 120 belows, shown in Fig. 1 C and 1D.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 102 normals to a surface.Then, form an interlayer dielectric layer 170, cover the surface of above-mentioned gate electrode 130 and aforesaid substrate 102.Then form lead 180, to connect above-mentioned source/drain regions 140/150, shown in Fig. 1 E at above-mentioned interlayer dielectric layer 170.
According to another preferred embodiment of the present invention, shown in Fig. 2 A to 2E, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 202 is provided, then, forms a cushion 204 on aforesaid substrate 202 surfaces, on above-mentioned cushion 204, form a semiconductor layer 210, on above-mentioned semiconductor layer 210, form a gate insulator 220 again, on above-mentioned gate insulator 220, form a gate electrode 230 then, shown in Fig. 2 A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 230, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 210, to form N type doped regions 232 and 234, shown in Fig. 2 B and 2C.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 202 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 230, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 210, forming source/drain regions 240/250, and overlapping and form N type LDD260 and 261 with the part of above-mentioned N type doped regions 232 and 234, it is positioned at above-mentioned gate insulator 220 belows, shown in Fig. 2 D.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 202 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 210.Then, form an interlayer dielectric layer 270, cover the surface of above-mentioned gate electrode 230 and aforesaid substrate 202.Then form lead 280, to connect above-mentioned source/drain regions 240/250, shown in Fig. 2 E at above-mentioned interlayer dielectric layer 270.
According to another preferred embodiment of the present invention, shown in Fig. 3 A to 3E, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 302 is provided, then, forms a cushion 304 on aforesaid substrate 302 surfaces, on above-mentioned cushion 304, form a semiconductor layer 310, on above-mentioned semiconductor layer 310, form a gate insulator 320 again, on above-mentioned gate insulator 320, form a gate electrode 330 then, as shown in Figure 3A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 330, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 310, to form source/drain regions 340/350, shown in Fig. 3 B.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 302 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 310.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 330, reaches between 5 * 10 with the energy between 50 to 110KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 310, with the part overlapping N type doped regions of formation with above-mentioned source/drain regions 340/350, and formation N type LDD360 and 361 is positioned at the close position of above-mentioned gate insulator 320 belows, shown in Fig. 3 C and 3D, above-mentioned II, about 0 to 30 degree of I deviation in driction substrate 302 normals to a surface.Then, form an interlayer dielectric layer 370, cover the surface of above-mentioned gate electrode 330 and aforesaid substrate 302.Then form lead 380, to connect above-mentioned source/drain regions 340/350, shown in Fig. 3 E at above-mentioned interlayer dielectric layer 370.
According to another preferred embodiment of the present invention, shown in Fig. 4 A to 4E, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 402 is provided, then, forms a cushion 404 on aforesaid substrate 402 surfaces, on above-mentioned cushion 404, form a semiconductor layer 410, on above-mentioned semiconductor layer 410, form a gate insulator 420 again, on above-mentioned gate insulator 420, form a gate electrode 430 then, shown in Fig. 4 A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 430, reaches between 5 * 10 with the energy between 50 to 110KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 410, to form N type doped regions 432/434, shown in Fig. 4 B and 4C, above-mentioned II, about 0 to 30 degree of I deviation in driction substrate 402 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 430, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 410, forming source/drain regions 440/450, and overlapping and form the close position that N type LDD460 and 461 is positioned at above-mentioned gate insulator 420 belows with the part of above-mentioned N type doped regions 432 and 434, shown in Fig. 4 D.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 402 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 410.Then, form an interlayer dielectric layer 470, cover the surface of above-mentioned gate electrode 430 and aforesaid substrate 402.Then form lead 480, to connect above-mentioned source/drain regions 440/450, shown in Fig. 4 E at above-mentioned interlayer dielectric layer 470.
In order to suppress the expansion of source electrode and drain electrode depletion region comprehensively, reduce leakage current (Leakage current) and punchthrough effect (Punch-through effect) between source electrode and the drain electrode, the present invention more provides a kind of P type LDD that source electrode and drain electrode are surrounded, and its formation method such as Fig. 5 are to shown in Figure 8.
In accordance with a preferred embodiment of the present invention, shown in Fig. 5 A to Fig. 5 G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 502 is provided, then, forms a cushion 504 on aforesaid substrate 502 surfaces, on above-mentioned cushion 504, form a semiconductor layer 510, on above-mentioned semiconductor layer 510, form a gate insulator 520 again, on above-mentioned gate insulator 520, form a gate electrode 530 then, shown in Fig. 5 A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 530, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 510, to form source/drain regions 540/550, shown in Fig. 5 B.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 502 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 510.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 530, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12 to 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 510, with the part overlapping N type doped regions of formation, and form N type LDD560 and 561 with above-mentioned source/drain regions 540/550, it is positioned at above-mentioned gate insulator 520 belows, shown in Fig. 5 C and 5D.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 502 normals to a surface.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 530, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 510, contain this source/drain regions 540/550 and this N type LDD560 and 561 respectively to form P type doped regions, and then produce P type LDD565/566, shown in Fig. 5 E and 5F.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 502 normals to a surface.
Then, form an interlayer dielectric layer 570, cover the surface of above-mentioned gate electrode 530 and aforesaid substrate 502.Then form lead 580, to connect above-mentioned source/drain regions 540/550, shown in Fig. 5 G at above-mentioned interlayer dielectric layer 570.
According to another preferred embodiment of the present invention, shown in Fig. 6 A to 6G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 602 is provided, then, forms a cushion 604 on aforesaid substrate 602 surfaces, on above-mentioned cushion 604, form a semiconductor layer 610, on above-mentioned semiconductor layer 610, form a gate insulator 620 again, on above-mentioned gate insulator 620, form a gate electrode 630 then, as shown in Figure 6A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 630, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 610, to form N type doped regions 632 and 634, shown in Fig. 6 B and 6C.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 602 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 630, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 610, forming source/drain regions 640/650, and overlapping and form N type LDD660 and 661 with the part of above-mentioned N type doped regions 632 and 634, it is positioned at above-mentioned gate insulator 620 belows, shown in Fig. 6 D.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 602 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 610.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 630, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 610, contain above-mentioned source/drain regions 640/650 and above-mentioned N type LDD660 and 661 respectively to form P type doped regions, and then produce P type LDD665/666, shown in Fig. 6 E and 6F.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 602 normals to a surface.
Then, form an interlayer dielectric layer 670, cover the surface of above-mentioned gate electrode 630 and aforesaid substrate 602.Then form lead 680, to connect above-mentioned source/drain regions 640/650, shown in Fig. 6 G at this interlayer dielectric layer 670.
According to another preferred embodiment of the present invention, shown in Fig. 7 A to 7G, the formation method of this liquid crystal indicator comprises following key step: at first, a substrate 702 is provided, then, forms a cushion 704 on aforesaid substrate 702 surfaces, on above-mentioned cushion 704, form a semiconductor layer 710, on above-mentioned semiconductor layer 710, form a gate insulator 720 again, on above-mentioned gate insulator 720, form a gate electrode 730 then, shown in Fig. 7 A.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 730, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 710, to form P type doped regions 740/750, shown in Fig. 7 B and 7C.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 702 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 730, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 710, forming source/drain regions 760/770, and above-mentioned source/drain regions 760/770 respectively with the overlapping of above-mentioned P type doped regions 740/750, and form P type LDD7401/7501, shown in Fig. 7 D.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 702 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 710.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 730, reaches between 5 * 10 with the energy between 10 to 50KeV in I, II direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 710, to form overlapping with the part of above-mentioned P type doped regions 740/750 and above-mentioned source/drain regions 760/770 respectively N type doped regions, and producing N type LDD780 and 790, it is positioned at above-mentioned gate insulator 720 belows, shown in Fig. 7 E and 7F.Above-mentioned I, about 40 to 80 degree of II deviation in driction substrate 702 normals to a surface.
Then, form an interlayer dielectric layer 792, cover the surface of above-mentioned gate electrode 730 and aforesaid substrate 702.Then form lead 794, to connect above-mentioned source/drain regions 760/770, shown in Fig. 7 G at above-mentioned interlayer dielectric layer 792.
According to another preferred embodiment of the present invention, shown in Fig. 8 A to Fig. 8 G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 802 is provided, then, forms a cushion 804 on aforesaid substrate 802 surfaces, on above-mentioned cushion 804, form a semiconductor layer 810, on above-mentioned semiconductor layer 810, form a gate insulator 820 again, on above-mentioned gate insulator 820, form a gate electrode 830 then, shown in Fig. 8 A.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 830, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 810, to form P type doped regions 840/850, shown in Fig. 8 B and 8C.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 802 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 830, reaches between 5 * 10 with the energy between 10 to 50KeV in I, II direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 810, with overlapping with the part of the above-mentioned P type doped regions 840/850 respectively N type doped regions 860/870 of formation, and form P type LDD8401/8501, shown in Fig. 8 D and 8E.Above-mentioned I, about 40 to 80 degree of II deviation in driction substrate 802 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 830, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 810, to form source/drain regions 872/874, and above-mentioned source/drain regions 872/874 respectively with the overlapping of above-mentioned P type doped regions 840/850 and above-mentioned N type doped regions 860/870, and generation N type LDD880 and 890, it is positioned at above-mentioned gate insulator 820 belows, shown in Fig. 8 F.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 802 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 810.
Then, form an interlayer dielectric layer 892, cover the surface of above-mentioned gate electrode 830 and aforesaid substrate 802.Then form lead 894, to connect above-mentioned source/drain regions 872/874, shown in Fig. 8 G at above-mentioned interlayer dielectric layer 892.
Though it is open that the present invention has come as mentioned above with several preferred embodiments; but it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; should make arbitrarily and to change and revise, so protection scope of the present invention is when looking being as the criterion that the accompanying Claim book defined.
Claims (15)
1, a kind of manufacture method of liquid crystal indicator comprises:
A substrate is provided;
On this substrate, form a cushion;
On this cushion, form semi-conductor layer;
On this semiconductor layer, form a gate insulator;
On this gate insulator, form a gate electrode;
With this gate electrode is mask, injects first alloy in this semiconductor layer, to form source/drain regions;
With this gate electrode is mask, injects second alloy in this semiconductor layer in the direction of first angle, with part overlapping first doped regions of formation with this source/drain regions; And
With this gate electrode is mask, injects the 3rd alloy in this semiconductor layer in the direction of second angle, with part overlapping second doped regions of formation with this source/drain regions.
2, the manufacture method of liquid crystal indicator as claimed in claim 1 more comprises:
With this gate electrode is mask, injects the 4th alloy in this semiconductor layer in the direction of third angle degree, and to form the 3rd doped regions, wherein the 3rd doped regions contains one of this source/drain regions and this first doped regions;
And
With this gate electrode is mask, injects the 5th alloy in this semiconductor layer in the direction of the 4th angle, and to form the 4th doped regions, wherein the 4th doped regions contains one of this source/drain regions and this second doped regions.
3, the manufacture method of liquid crystal indicator as claimed in claim 1, this source/drain regions form with this first doped regions and this second doped regions respectively and overlap.
4, the manufacture method of liquid crystal indicator as claimed in claim 1, this first alloy is in the direction that is approximately perpendicular to this substrate surface is injected this semiconductor layer, to form source/drain regions.
5, the manufacture method of liquid crystal indicator as claimed in claim 1, this first alloy, this second alloy, and the 3rd alloy be to inject in this semiconductor layer with ion implantation.
6, the manufacture method of liquid crystal indicator as claimed in claim 2, the 4th alloy, the 5th alloy are to inject in this semiconductor layer with ion implantation.
7, the manufacture method of liquid crystal indicator as claimed in claim 1, this first alloy, this second alloy, and the 3rd alloy be to be selected from by As, P, AsH
x, and PH
xIn the group of being formed one.
8, the manufacture method of liquid crystal indicator as claimed in claim 2, the 4th alloy, the 5th alloy are to be selected from by B, BH
x, and BF
xIn the group of being formed one.
9, the manufacture method of liquid crystal indicator as claimed in claim 1, this first alloy, this second alloy, and the 3rd alloy respectively with between 10 to 20KeV, 10 to 50KeV, and 10 to 50KeV energy inject in this semiconductor layer.
10, the manufacture method of liquid crystal indicator as claimed in claim 2, the 4th alloy, the 5th alloy are respectively with in 40 to 80KeV, 40 energy to 80KeV inject this semiconductor layer.
11, the manufacture method of liquid crystal indicator as claimed in claim 1, this first alloy, this second alloy, and the 3rd alloy respectively with between 1 * 10
15To 5 * 10
15Ions/cm
2, 5 * 10
12To 1 * 10
14Ions/cm
2, and 5 * 10
12To 1 * 10
14Ions/cm
2Dosage inject in this semiconductor layer.
12, the manufacture method of liquid crystal indicator as claimed in claim 2, the 4th alloy, the 5th alloy are respectively with between 5 * 10
11To 2 * 10
12Ions/cm
2, 5 * 10
11To 2 * 10
12Ions/cm
2Dosage inject in this semiconductor layer.
13, the manufacture method of liquid crystal indicator as claimed in claim 1, this second alloy, the 3rd alloy are roughly injected in this semiconductor layer at the pitch angle of 0 to 80 degree, 0 to 80 degree with the normal that departs from this semiconductor-based basal surface respectively.
14, the manufacture method of liquid crystal indicator as claimed in claim 2, the 4th alloy, the 5th alloy are roughly injected in this semiconductor layer at 40 to 60 pitch angle of spending, reach 40 to 60 degree with the normal that departs from this semiconductor-based basal surface respectively.
15, the manufacture method of liquid crystal indicator as claimed in claim 1 more comprises forming an interlayer dielectric layer, covers the surface of this gate electrode and this substrate; And, connect this source/drain regions at this interlayer dielectric layer formation lead.
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| CNB2005100064907A CN100368912C (en) | 2005-02-03 | 2005-02-03 | Manufacturing method of liquid crystal display device |
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|---|---|---|---|
| CNB2005100064907A CN100368912C (en) | 2005-02-03 | 2005-02-03 | Manufacturing method of liquid crystal display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623314A (en) * | 2012-03-23 | 2012-08-01 | 上海华力微电子有限公司 | Source-drain lightly-doping method, semiconductor device and manufacturing method thereof |
| CN106783626A (en) * | 2017-01-04 | 2017-05-31 | 京东方科技集团股份有限公司 | The manufacture method of thin film transistor (TFT), array base palte and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3767602B2 (en) * | 1994-12-27 | 2006-04-19 | セイコーエプソン株式会社 | Liquid crystal display |
| CN1196832A (en) * | 1996-06-28 | 1998-10-21 | 精工爱普生株式会社 | Thin film transistor, method of its manufacture and circuit and liquid crystal display using thin film transistor |
| CN1151405C (en) * | 2000-07-25 | 2004-05-26 | 友达光电股份有限公司 | Thin-film transistor LCD and its manufacture |
| JP2002050764A (en) * | 2000-08-02 | 2002-02-15 | Matsushita Electric Ind Co Ltd | Thin-film transistor, array substrate, liquid crystal display, organic el display, and its manufacturing method |
| JP2002185008A (en) * | 2000-12-19 | 2002-06-28 | Hitachi Ltd | Thin-film transistor |
| JP4037117B2 (en) * | 2001-02-06 | 2008-01-23 | 株式会社日立製作所 | Display device |
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2005
- 2005-02-03 CN CNB2005100064907A patent/CN100368912C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623314A (en) * | 2012-03-23 | 2012-08-01 | 上海华力微电子有限公司 | Source-drain lightly-doping method, semiconductor device and manufacturing method thereof |
| CN106783626A (en) * | 2017-01-04 | 2017-05-31 | 京东方科技集团股份有限公司 | The manufacture method of thin film transistor (TFT), array base palte and display device |
| WO2018126636A1 (en) * | 2017-01-04 | 2018-07-12 | 京东方科技集团股份有限公司 | Manufacturing method of thin film transistor, array substrate, and display device |
| US10566199B2 (en) | 2017-01-04 | 2020-02-18 | Boe Technology Group Co., Ltd. | Methods of manufacturing thin film transistor, array substrate and display device |
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