CN1612293A - Method for manufacturing multi-layer structure having strain and field effect transistor having strain layer - Google Patents
Method for manufacturing multi-layer structure having strain and field effect transistor having strain layer Download PDFInfo
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- CN1612293A CN1612293A CN 200310103091 CN200310103091A CN1612293A CN 1612293 A CN1612293 A CN 1612293A CN 200310103091 CN200310103091 CN 200310103091 CN 200310103091 A CN200310103091 A CN 200310103091A CN 1612293 A CN1612293 A CN 1612293A
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 87
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 46
- 230000000750 progressive effect Effects 0.000 claims description 42
- 239000011435 rock Substances 0.000 claims description 32
- 230000008021 deposition Effects 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 238000010276 construction Methods 0.000 claims description 17
- SVXHDONHRAZOCP-UHFFFAOYSA-N ethane;silicon Chemical compound [Si].CC SVXHDONHRAZOCP-UHFFFAOYSA-N 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- POXCVKMBBFNXLZ-UHFFFAOYSA-N propane;silicon Chemical compound [Si].CCC POXCVKMBBFNXLZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000001186 cumulative effect Effects 0.000 claims description 5
- 150000003376 silicon Chemical class 0.000 claims 4
- 238000000151 deposition Methods 0.000 abstract description 19
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 12
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910007264 Si2H6 Inorganic materials 0.000 abstract 1
- 229910005096 Si3H8 Inorganic materials 0.000 abstract 1
- 239000002243 precursor Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000013078 crystal Substances 0.000 description 9
- 239000004575 stone Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 238000006557 surface reaction Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 229910000078 germane Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- 229910003902 SiCl 4 Inorganic materials 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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Abstract
The invention includes following steps: first, depositing a step-graded silicon-germanium (Si1-x Gex) layer; next, depositing an upper cover layer of silicon-germanium on a buffer layer of the step-graded silicon-germanium; finally, depositing a monocrystalline silicon layer on the upper cover layer of silicon-germanium in order to form a strained layer. As Si2H6 or Si3H8 being as precursor of the preparing procedure, the buffer layer of the step-graded silicon-germanium, the upper cover layer of silicon-germanium and the monocrystalline silicon layer are produced through reduced pressure chemical vapor deposition (RPCVD). The invention also discloses the method for manufacturing field-effect transistor possessing strained layer.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, particularly make the sandwich construction of tool strain and have the method for the field-effect transistor of strained layer relevant for a kind of.
Background technology
For the integration that cooperates integrated circuit increases demand with the usefulness of lifting subassembly, the downsizing constantly of semiconductor subassembly size.Yet, for example, in the commonly used semiconductor subassembly of integrated circuit,, make it can be under low operating voltage as metal-oxide half field effect transistor (MOSFET), have high drive current and usefulness at a high speed and be suitable difficulty.Therefore, many people are in the method for making great efforts to seek to improve the usefulness of mosfet device.
Someone's band structure modification of proposing to utilize stress to cause increases the mobility of carrier at present, to increase the drive current of field-effect transistor, can improve the usefulness of fet devices, and this kind method has been applied in the various assemblies.The silicon channel of these assemblies is the situations that are in strain.
Traditionally, be by building crystal to grow silicon channel layer in SiGe (SiGe) layer of lax (relaxed) or substrate, with the silicon layer of preparation strain.Before the silicon channel layer of growth strain, need the Si that is out of shape gradually in silica-based upward growth lattice usually
1-xGe
xLayer, wherein the ratio x of germanium increases to 0.2 gradually from 0, is called progressive (step-graded) silicon germanium buffer herein.Follow the lax SiGe (Si of growth one deck on progressive silicon germanium buffer again
0.7Ge
0.3) last cap rock.
Above-mentioned these germanium-silicon layers and strained silicon layer are to prepare in brilliant (epitaxy) mode of heap of stone, and be wherein common with Low Pressure Chemical Vapor Deposition again.Generally speaking, employed reacting gas (processing procedure predecessor) is silicon tetrachloride (SiCl
4), dichlorosilane (SiH
2Cl
2), trichlorosilane (SiHCl
3), silane (SiH
4) etc.Its growth mechanism can be learnt by the relation curve of growth speed and temperature.Usually, the relation curve slope of above-mentioned four kinds of gases in the high-temperature region (more than 800 ℃) less, and bigger at low-temperature space, between have a breakover point.In the little zone of slope, growth speed is temperature influence more not, mainly is directly proportional with the matter biography speed of reacting gas to substrate, and this zone is called matter and passes controlled area (masstransfer controlled region).On the other hand, in the big zone of slope, growth speed is relevant with surface reaction speed, and with the temperature exponent function relation, this zone is called surface reaction control district (surface reaction controlled region).Pass the formed brilliant uniformity of film of heap of stone in controlled area (during high temperature) in matter and be better than surface reaction control district (surface reactionControlled region), but be unfavorable for integrating strain film to manufacture of semiconductor owing to the required growth temperature of the reacting gas that uses is higher, therefore in the existing manufacture of semiconductor, building crystal to grow carries out more than the surface reaction control district.
Yet the preparation of the brilliant film of heap of stone under low temperature (for example, below 700 ℃) is quite consuming time, when particularly using above-mentioned reacting gas.For example, (every wafer need spend more than one hour on the sandwich construction of making the tool strain at least for lowpressure CVD, LPCVD) building crystal to grow by low-pressure chemical vapor deposition.Moreover (ultra-highvacuum CVD, UHVCVD), every wafer need spend more than ten hours at least if adopt the ultravacuum chemical vapour deposition (CVD).That is, badly influence production capacity and manufacturing cost because of expending long manufacturing time.
U.S. Pat 5,951 discloses a kind of method of germanium-silicon layer No. 757, and it utilizes silane and germane to form germanium-silicon layer as the processing procedure predecessor behind hydrogen passivation one process for sapphire-based basal surface again.Moreover, U.S. Pat 6,410, disclose a kind of manufacture method No. 371 with silicon insulating barrier (SOI) of silicon/SiGe/Si floor active layers, after it had the silicon base of silica/silicon/germanium-silicon layer by making one silicon base and with silicon dioxide layer, this had the silicon insulating barrier substrate of silicon/SiGe/Si layer active layers to bind (bonding) technology be combined at the silicon dioxide layer with two silicon base via high temperature.Moreover, U.S. Pat 6,515,335 disclose a kind of method of making lax germanium-silicon layer in the substrate of silicon insulating barrier, it is earlier by form a wettable layer (wetting layer) in a silicon insulating barrier substrate, form the SiGe island in regular turn and cover cap rock on the SiGe of island comprehensively by molecular beam epitaxy (MBE) or CVD afterwards, then via a tempering program make wettable layer, SiGe island, and SiGe on cap rock generation cross reaction and form a monocrystalline silicon germanium layer, form the crystal silicon layer of heap of stone of a strain at last more thereon.In above-mentioned these methods, not that still to use silane be exactly that processing procedure is too complicated as the processing procedure predecessor, and the effective lifting subassembly production capacity of making.
Summary of the invention
In view of this, the object of the present invention is to provide and a kind ofly make the sandwich construction of tool strain and have the method for the field-effect transistor of strained layer.Its by adopt two silicon ethane or three silicon propane as the predecessor of chemical vapor deposition process to replace predecessors such as traditional methane or dichlorosilane, so as to significantly promoting the production capacity that deposition rate and then lifting subassembly are made.
According to above-mentioned purpose, the invention provides a kind of method of making the sandwich construction of tool strain.At first, provide a substrate, again deposition one progressive SiGe (Si in substrate
1-xGe
x) resilient coating, wherein x is cumulative to 0.3 by 0 with progressive silicon germanium buffer thickness increase.Subsequently, cap rock on deposition one SiGe on the progressive silicon germanium buffer.At last, on cap rock on the SiGe, deposit a monocrystalline silicon layer to form a strained layer.Wherein, be as the processing procedure predecessor, to form cap rock and monocrystalline silicon layer on progressive silicon germanium buffer, the SiGe in regular turn by two silicon ethane/three silicon propane.
Moreover above-mentioned substrate can be a silicon base, and more comprises a silicon buffer layer and be formed between substrate and the progressive silicon germanium buffer, and its thickness is 0.1 to 0.9 micron scope.
Moreover the thickness of progressive silicon germanium buffer is 2 to 5 microns scope.The thickness of cap rock is 0.5 to 1 micron scope on the SiGe.The thickness of monocrystalline silicon layer is in the scope of 100 to 300 dusts.
Moreover cap rock and monocrystalline silicon layer can form by rpcvd (RPCVD) on progressive silicon germanium buffer, the SiGe.Wherein, the process temperatures of rpcvd is 600 ℃ to 800 ℃ scope, and processing procedure pressure is in the scope of 50Torr to 760Torr.
According to above-mentioned purpose, the invention provides the method that a kind of manufacturing has the field-effect transistor of strained layer again.At first, provide a silicon base, again deposition one progressive SiGe (Si on silicon base
1-xGe
x) resilient coating, wherein x is cumulative to 0.3 by 0 with progressive silicon germanium buffer thickness increase.Subsequently, cap rock on deposition one SiGe on the progressive silicon germanium buffer.Then, on cap rock on the SiGe deposition one monocrystalline silicon layer with as a strained channel layer.At last, forming a gate structure above the strained channel layer and in the strained channel layer in the gate structure outside, forming one source pole/drain area.Wherein, be as the processing procedure predecessor, to form cap rock and monocrystalline silicon layer on progressive silicon germanium buffer, the SiGe in regular turn by two silicon ethane/three silicon propane.
Moreover, more comprising a silicon buffer layer and be formed between silicon base and the progressive silicon germanium buffer, its thickness is 0.1 to 0.9 micron scope.
Moreover the thickness of progressive silicon germanium buffer is 2 to 5 microns scope.The thickness of cap rock is 0.5 to 1 micron scope on the SiGe.The thickness of monocrystalline silicon layer is in the scope of 100 to 300 dusts.
Moreover cap rock and monocrystalline silicon layer can form by rpcvd (RPCVD) on progressive silicon germanium buffer, the SiGe.Wherein, the process temperatures of rpcvd is 600 ℃ to 800 ℃ scope, and processing procedure pressure is in the scope of 50Torr to 760Torr.
Moreover gate structure comprises a brake-pole dielectric layer, a gate electrode, reaches a gate clearance wall.Wherein, brake-pole dielectric layer is arranged at strained channel layer top, and gate electrode is arranged at this brake-pole dielectric layer top, and the gate clearance wall is arranged at the gate electrode sidewall.
Description of drawings
Figure 1A is to show the flow process generalized section that has the field-effect transistor of strained layer according to the manufacturing of the embodiment of the invention to Fig. 1 C.
Fig. 2 shows the logarithm deposition rate of differential responses gas and the graph of relation of reaction temperature.
Symbol description:
The 10-substrate;
The 12-silicon buffer layer;
The progressive silicon germanium buffer of 14-;
Cap rock on the 16-SiGe;
The 18-monocrystalline silicon layer;
The 20-brake-pole dielectric layer;
The 22-gate electrode;
24-gate clearance wall;
The 25-gate structure;
The 26-source/drain.
Embodiment
Below cooperate Figure 1A to illustrate that to Fig. 1 C and Fig. 2 the manufacturing of the embodiment of the invention has the method for the field-effect transistor of strained layer.
At first, please refer to Figure 1A, a substrate 10 be provided, this substrate 10 can be a monocrystal silicon substrate, the substrate of silicon insulating barrier (silicon on insulator, SOI) or other semiconductor-based end.Herein, be with a crystallization direction for the monocrystal silicon substrate of (100) as example.Can comprise a silicon buffer layer 12 in the substrate 10, it is in order to the crystal seed layer (seed layer) as the subsequent deposition silicon germanium buffer.In the present embodiment, silicon buffer layer 12 can be formed on the substrate 10 by brilliant mode of heap of stone, for example, uses silicon-containing compound as reacting gas, carries out chemical vapor deposition (CVD).Silicon buffer layer 12 thickness that form are in the scope of 0.1 to 0.9 micron (μ m), and preferable thickness is about 0.5 μ m.
Then, deposition one germanium-silicon layer on silicon buffer layer 12.In the present embodiment, this germanium-silicon layer comprises two parts up and down.The bottom is divided into one progressive (setp-graded) SiGe (Si
1-xGe
x) resilient coating 14, and top is divided into cap rock 16 (shown in Figure 1B) on the SiGe of lax (relaxed).In progressive silicon germanium buffer 14, the atomic ratio x of germanium is cumulative to 0.3 by 0 with progressive silicon germanium buffer 14 thickness increase, and the speed of increase is in the scope of 0.06/ μ m to 0.15/ μ m.That is, progressive silicon germanium buffer 14 and silicon buffer layer 12 at the interface, the content of germanium is about 0, and the top surface place of progressive silicon germanium buffer 14, the content of germanium is about 0.3.
In the present embodiment, progressive silicon germanium buffer 14 can form by crystal type of heap of stone.Its method can be, and uses two silicon ethane (disilane, Si
2H
6) or three silicon propane (trisilane, Si
3H
8) as the processing procedure predecessor in silicon source, and use germane (germane, GeH
4) as the processing procedure predecessor in germanium source, carry out rpcvd (reduced pressure CVD, RPCVD).Wherein, the process temperatures of deposition is 600 ℃ to 800 ℃ scope.Moreover processing procedure pressure is in the scope of 50Torr to 760Torr.The thickness of the progressive silicon germanium buffer 14 that forms is in the scope of 2 to 5 μ m, and preferable thickness is about 2.1 μ m.
Next, please refer to Figure 1B, similarly, on progressive silicon germanium buffer 14, deposit a lax SiGe (Si by brilliant mode of heap of stone
1-yGe
y) last cap rock 16.Be different from progressive silicon germanium buffer 14, the germanium atom ratio y on the SiGe in the cap rock 16 is a constant, and for example y is in 0.25 to 0.3 scope.In the present embodiment, cap rock 16 on the SiGe, similarly, use two silicon ethane or the three silicon propane processing procedure predecessor as the silicon source, and use the processing procedure predecessor of germane as the germanium source, carry out rpcvd.Wherein, the process temperatures of deposition is 600 ℃ to 800 ℃ scope.Moreover the flow of two silicon ethane/three silicon propane is 50 to the scope of 200sccm, and the flow of germane is in 50 to 200sccm scope.Moreover processing procedure pressure is in the scope of 50Torr to 760Torr.The thickness of cap rock 16 is in the scope of 0.5 to 1 μ m on the SiGe that forms, and preferable thickness is about 0.9 μ m.Herein, the progressive silicon germanium buffer 14 in the germanium-silicon layer is to arrange (threadingdislocation) in order to the lattice defect-difference of assembling and reduce wherein, and cap rock 16 then provides the usefulness of follow-up formation strained layer on the SiGe.
On forming progressive silicon germanium buffer 14 and SiGe, after the cap rock 16, then deposit a monocrystalline silicon layer 18 thereon, to form a strained silicon layer, in order to strained channel layer as follow-up transistor fabrication.In the present embodiment, monocrystalline silicon layer 18 also adopts brilliant mode of heap of stone to form.That is, use two silicon ethane or three silicon propane processing procedure predecessor as the silicon source, carry out rpcvd.Wherein, the process temperatures of deposition is 600 ℃ to 800 ℃ scope.Moreover processing procedure pressure is in the scope of 50Torr to 760Torr.The thickness of the monocrystalline silicon layer 18 that forms is in the scope of 100 to 300 dusts (), and preferable thickness is about 135 .Thus, just finish the sandwich construction of tool strain of the present invention.
At last, please refer to Fig. 1 C, above strained silicon layer 18, form a gate structure 25.It comprises a brake-pole dielectric layer 20, a gate electrode 22, reaches a gate electrode 24.Brake-pole dielectric layer 20 is strained silicon layer 18 tops that are arranged at as channel layer.Moreover 22 of gate electrodes are arranged at brake-pole dielectric layer 20 tops.In addition, gate clearance wall 24 is arranged at the gate electrode sidewall.
Herein, the method that forms gate structure 25 is as follows: at first, can by thermal oxidation method above strained silicon layer 18, form one silica layer (not illustrating) wherein the temperature of oxidation be to be lower than 800 ℃.Then, can be by conventional deposition technique, for example chemical vapour deposition (CVD) forms a compound crystal silicon layer (not illustrating) above silicon oxide layer, and utilize known little shadow and etching technique, define the brake-pole dielectric layer 20 that constitutes by silicon oxide layer and by gate electrode 22 that compound crystal silicon layer constituted.Afterwards, can deposit a silicon nitride layer (not illustrating) on strained silicon layer 18 surfaces with gate electrode sidewall and surperficial compliance by chemical vapour deposition (CVD) equally, and utilize anisotropic etching, reactive ion etching (reactive ion etching for example, RIE), etches both silicon nitride layer, to stay the silicon nitride layer 24 of part at gate electrode 22 sidewalls, this promptly is made for the usefulness of gate clearance wall.
After finishing the making of gate structure 25, can on the strained channel layer 18 in gate structure 25 outsides and SiGe, form doped region 26 in the cap rock 16 to be made for the usefulness of source/drain by implanting ions.Thus, just finishing the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) (MOSFET) with strained layer makes.
Be noted that,, yet have the knack of this skill person, can, the present invention is integrated in the making of other semiconductor subassembly, for example CMOS transistor according to the needs of circuit unit design though the present invention is to be example to make MOSFET on the sandwich construction of tool strain.
Next, please refer to Fig. 2, its logarithm deposition rate (μ m/min) that shows different processing procedure predecessors and reaction temperature (℃) graph of relation.As discussed previously, each curve A among the figure, B, C, D, and the slope of E less when high temperature, and bigger at low temperature, between have a breakover point.The zone that slope is little is matter and passes the controlled area, and the big zone of slope is the surface reaction control district.Moreover the A curve representation is with silicon tetrachloride (SiCl
4) be the processing procedure predecessor, the B curve representation is with trichlorosilane (SiHCl
3) be the processing procedure predecessor, C curve is represented with dichlorosilane (SiH
2Cl
2) be the processing procedure predecessor, the D curve representation is with silane (SiH
4) be the processing procedure predecessor, the E curve representation is with two silicon ethane (Si
2H
6) be the processing procedure predecessor.Significantly, using under known processing procedure predecessor (being curve A, B, C, the D) situation, if will pass the controlled area deposit film in matter, required reaction temperature higher (more than 850 ℃) and be not suitable for the building crystal to grow strained layer.Yet if processing procedure predecessor used in the present invention (being curve E), reaction temperature can be reduced to below 800 ℃.
On the other hand, in response to the restriction of low temperature (for example below 700 ℃) brilliant processing procedure of heap of stone now, must be at surface reaction control district deposit film, the present invention's (curve E) deposition rate also is higher than known techniques (curve A, B, C, D), also can significantly promote deposition rate and effectively shorten the processing procedure time, and then the production capacity of lifting subassembly making and reduction cost of manufacture.
Claims (20)
1. a method of making the sandwich construction of tool strain comprises the following steps:
One substrate is provided;
Deposition one progressive SiGe (Si in this substrate
1-xGe
x) resilient coating, wherein x is cumulative to 0.3 by 0 with this progressive silicon germanium buffer thickness increase;
Cap rock on deposition one SiGe on this progressive silicon germanium buffer; And
Deposition one monocrystalline silicon layer is to form a strained layer on cap rock on this SiGe;
Wherein by two silicon ethane/three silicon propane as the processing procedure predecessor, to form cap rock and this monocrystalline silicon layer on this progressive silicon germanium buffer, this SiGe in regular turn.
2. the method for the sandwich construction of manufacturing tool according to claim 1 strain, wherein this substrate is a silicon base.
3. the method for the sandwich construction of manufacturing tool according to claim 2 strain comprises that more a silicon buffer layer is formed between this substrate and this progressive silicon germanium buffer.
4. the method for the sandwich construction of manufacturing tool according to claim 3 strain, wherein the thickness of this silicon buffer layer is 0.1 to 0.9 micron scope.
5. the method for the sandwich construction of manufacturing tool according to claim 1 strain, wherein the thickness of this progressive silicon germanium buffer is 2 to 5 microns scope.
6. the method for the sandwich construction of manufacturing tool according to claim 1 strain, wherein on this SiGe the thickness of cap rock 0.5 to 1 micron scope.
7. the method for the sandwich construction of manufacturing tool according to claim 1 strain, wherein the thickness of this monocrystalline silicon layer is in the scope of 100 to 300 dusts.
8. the method for the sandwich construction of manufacturing tool according to claim 1 strain wherein forms cap rock and this monocrystalline silicon layer on this progressive silicon germanium buffer, this SiGe by rpcvd (RPCVD).
9. the method for the sandwich construction of manufacturing tool according to claim 8 strain, wherein the process temperatures of this rpcvd is 600 ℃ to 800 ℃ scope.
10. the method for the sandwich construction of manufacturing tool according to claim 8 strain, wherein the processing procedure pressure of this rpcvd is in the scope of 50Torr to 760Torr.
11. a manufacturing has the method for the field-effect transistor of strained layer, comprises the following steps:
One silicon base is provided;
Deposition one progressive SiGe (Si on this silicon base
1-xGe
x) resilient coating, wherein x is cumulative to 0.3 by 0 with this progressive silicon germanium buffer thickness increase;
Cap rock on deposition one SiGe on this progressive silicon germanium buffer;
Deposition one monocrystalline silicon layer on cap rock on this SiGe is with as a strained channel layer;
Above this strained channel layer, form a gate structure; And
In this strained channel layer in this gate structure outside, form one source pole/drain area;
Wherein by two silicon ethane/three silicon propane as the processing procedure predecessor, to form cap rock and this monocrystalline silicon layer on this progressive silicon germanium buffer, this SiGe in regular turn.
12. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, comprises that more a silicon buffer layer is formed between this silicon base and this progressive silicon germanium buffer.
13. manufacturing according to claim 12 has the method for the field-effect transistor of strained layer, wherein the thickness of this silicon buffer layer is 0.1 to 0.9 micron scope.
14. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, wherein the thickness of this progressive silicon germanium buffer is 2 to 5 microns scope.
15. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, wherein on this SiGe the thickness of cap rock 0.5 to 1 micron scope.
16. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, wherein the thickness of this monocrystalline silicon layer is in the scope of 100 to 300 dusts.
17. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, wherein forms cap rock and this strained silicon layer on this progressive silicon germanium buffer, this SiGe by rpcvd (RPCVD).
18. manufacturing according to claim 17 has the method for the field-effect transistor of strained layer, wherein the process temperatures of this rpcvd is 600 ℃ to 800 ℃ scope.
19. manufacturing according to claim 17 has the method for the field-effect transistor of strained layer, wherein the processing procedure pressure of this rpcvd is in the scope of 50Torr to 760Torr.
20. manufacturing according to claim 11 has the method for the field-effect transistor of strained layer, wherein this gate structure more comprises:
One brake-pole dielectric layer is arranged at this strained channel layer top;
One gate electrode is arranged at this brake-pole dielectric layer top; And
One gate clearance wall; Be arranged at this gate electrode sidewall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101807605A (en) * | 2010-02-05 | 2010-08-18 | 上海宏力半导体制造有限公司 | Semiconductor device and manufacture method thereof |
| WO2011069370A1 (en) * | 2009-12-11 | 2011-06-16 | 清华大学 | Method of forming high-germanium component channel material layer |
| CN101652832B (en) * | 2007-01-26 | 2011-06-22 | 晶体公司 | Thick pseudomorphic nitride epitaxial layers |
| CN102315246A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院上海硅酸盐研究所 | Relaxation SiGe virtual substrate and preparation method thereof |
| CN102412124A (en) * | 2011-09-30 | 2012-04-11 | 上海晶盟硅材料有限公司 | Method for producing novel substrate, epitaxial wafer and semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5273930A (en) * | 1992-09-03 | 1993-12-28 | Motorola, Inc. | Method of forming a non-selective silicon-germanium epitaxial film |
| US5951757A (en) * | 1997-05-06 | 1999-09-14 | The United States Of America As Represented By The Secretary Of The Navy | Method for making silicon germanium alloy and electric device structures |
| US6649480B2 (en) * | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
| JP4792180B2 (en) * | 2001-07-31 | 2011-10-12 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus |
| CN1172376C (en) * | 2001-12-29 | 2004-10-20 | 中国科学院上海微系统与信息技术研究所 | Material similar to silicon structure on isolation layer and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101652832B (en) * | 2007-01-26 | 2011-06-22 | 晶体公司 | Thick pseudomorphic nitride epitaxial layers |
| WO2011069370A1 (en) * | 2009-12-11 | 2011-06-16 | 清华大学 | Method of forming high-germanium component channel material layer |
| CN101807605A (en) * | 2010-02-05 | 2010-08-18 | 上海宏力半导体制造有限公司 | Semiconductor device and manufacture method thereof |
| CN101807605B (en) * | 2010-02-05 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and manufacture method thereof |
| CN102315246A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院上海硅酸盐研究所 | Relaxation SiGe virtual substrate and preparation method thereof |
| CN102315246B (en) * | 2010-06-30 | 2013-03-13 | 中国科学院上海硅酸盐研究所 | Relaxation SiGe virtual substrate and preparation method thereof |
| CN102412124A (en) * | 2011-09-30 | 2012-04-11 | 上海晶盟硅材料有限公司 | Method for producing novel substrate, epitaxial wafer and semiconductor device |
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| CN100397574C (en) | 2008-06-25 |
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