CN1851900A - Making method of adopting phase-change to realizing strain silicon on insulator - Google Patents
Making method of adopting phase-change to realizing strain silicon on insulator Download PDFInfo
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- CN1851900A CN1851900A CN200610025284.5A CN200610025284A CN1851900A CN 1851900 A CN1851900 A CN 1851900A CN 200610025284 A CN200610025284 A CN 200610025284A CN 1851900 A CN1851900 A CN 1851900A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 82
- 239000010703 silicon Substances 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000012212 insulator Substances 0.000 title claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 79
- 239000013081 microcrystal Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 230000009466 transformation Effects 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 239000007795 chemical reaction product Substances 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 22
- 230000002427 irreversible effect Effects 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000003672 processing method Methods 0.000 abstract 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- -1 silicon ion Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
This invention discloses a processing method for strain silicon realized on an insulator by a phase transformation technology, which smartly combines a dense and smooth noncrystalline silicon deposition method, a low temperature bonding technology, an irreversible phase transformation control from noncrystalline silicon to micro-crystal silicon and an internal oxidation technology of the micro-crystal silicon to avoid the exorbitant method of GeSi extension and chemical polish in preparing the SSOI materials.
Description
Technical field
The present invention relates to the manufacturing technology of strained silicon, particularly utilize the making of the method realization strained-silicon-on-insulator of irreversible transition.
Background technology
Strained silicon has high carrier mobility and is confirmed.(Silicon on insulator, SOI) top layer silicon in can make this superior SOI complementary metal oxide semiconductors (CMOS) (CMOS) circuit obtain a more superior performance as strained silicon technology being introduced silicon on the insulator.Therefore, the strained silicon that preparation has insulating buried layer can become in the future desirable silica-based microelectronic material in conjunction with the advantage of SOI and strained silicon in one, also becomes a present international popular research topic thus.Isolate (separation-by-implanted-oxygen though there is human oxygen to inject at present, SIMOX) technology has prepared at the strained silicon (strained-silicon-on-SiGe-on-insulator that has on the germanium silicon layer of insulating barrier, SGOI), but, buried oxide layer needs high annealing temperature because forming, cause the diffusion of germanium (Ge), the effect as the germanium silicon (SiGe) of strain masterplate layer is reduced greatly.Utilize smart-cut (Smart-Cut) that is layer transfer technology in the similar SOI technology of preparing to prepare the SGOI material, but because the germanium silicon layer under the strained silicon layer exists, force CMOS technology is made corresponding change, to get rid of the adverse effect that the germanium silicon layer brings as far as possible.Therefore prepare strained silicon directly the research on insulator become the important research target of desirable silica-based microelectronic material.For this reason, usually people adopt band silica and extension strained silicon layer Direct Bonding on germanium silicon, remove germanium silicon layer or the transfer of similar smart-cut technology realization extension strained silicon layer with the method for selective etching again, finally realize the preparation of strained-silicon-on-insulator (SSOI/SSDOI) material.There is bibliographical information to utilize of the growth of the germanium and silicon epitaxial of graded, realizes the making of SSDOI/SSOI then by the mode of bonding and selective etching to the ultra-thin strained silicon of realization.Nearest domestic researcher reports that employing injects nitrogen to initial SOI thin-layer silicon after carrying out germanium and silicon epitaxial on the SOI substrate, after the germanium silicon layer of extension is removed in annealing and selective etching, realized 0.72% dependent variable of silicon, but the surface after its corrosion is obviously coarse.There is bibliographical information to utilize the phosphorus glass (BPSG) of boronation to replace silica again, can realizes the adjusting of viscosity by the composition ratio in the phosphorus glass that changes boronation as insulating barrier.Its manufacturing process as shown in Figure 1.The phosphorus glass of deposition boronation on substrate 1 at first, regrowth silicon and inject hydrogen (H behind the epitaxial Germanium silicon on the substrate 2
+) (Fig. 1 a), then with substrate 1 and substrate 2 bondings (Fig. 1 b), stay germanium silicon layer and silicon layer by layer transfer and corrosion technology, it is patterned into square island (Fig. 1 c), high annealing makes the expansion of the layer on upper strata drive the silicon coherence lateral expansion (Fig. 1 d) of lower floor then, because the compliance of the phosphorus glass of boronation exists, warpage can not take place in strained silicon.Utilize selective etching to remove top layer germanium silicon layer at last and stay strained silicon (Fig. 1 e).But because the insulating barrier that this manufacture craft is used is the phosphorus glass of boronation, though the thick Si of 5nm
3N
4Be deposited between the phosphorus glass of boronation and the silicon layer stoping boron (B), the diffusion of phosphorus (P) in the CMOS high-temperature technology, but increased technology difficulty after all and potential risks are arranged.
Up to now, all making reports that relate to biaxial stretch-formed strained silicon have nearly all adopted Si germanium silicon growth and chemico-mechanical polishing (CMP) technology, and the use of these two kinds of technologies all has higher cost.U.S.'s Intel (Intel) company also is reported in the uniaxial tensile strain of the tensile stress realization silicon of the silicon nitride that utilizes deposition in the device making technics, thereby improve the performance of N type field effect transistor (FET) electron mobility, in the source/the drain region performance of the method realization single compressing stress of selective epitaxy germanium silicon with raising P type field effect transistor hole mobility.
Summary of the invention
The objective of the invention is in order to overcome current technology of preparing defect of high cost, provide cheaply a kind of and with the complete manufacture method of compatible strained-silicon-on-insulator of silicon-based semiconductor technology.
In order to realize purpose of the present invention, technical scheme of the present invention is: a kind of manufacture method that adopts phase-change method to realize strained-silicon-on-insulator, and characteristics are that it may further comprise the steps:
1. being 10-20 nanometer (nm) at top layer silicon thickness, is the fine and close smooth amorphous silicon (α-Si) of 40～80 nanometers with low-pressure chemical vapor deposition (LPCVD) growth one layer thickness on the top layer silicon of the ultra-thin SOI silicon chip of thickness 3000～4000 dusts () of buried oxide layer;
2. again with the silica of another silicon substrate thermal oxide growth one deck 200 nanometers;
The ultra-thin SOI silicon chip that deposits amorphous silicon with step 1 gained with the silicon chip of the hot growing silicon oxide of step 2 gained at 400 ℃ of following low-temperature bondings;
4. the buried regions silica that the silicon chip behind the bonding is thinned to again soi wafer stops;
5. the bonding silicon chip after will corroding again makes amorphous silicon become microcrystal silicon mutually to being incubated under the high temperature more than 600 ℃;
6. elevated temperature to 800 ℃～1150 ℃ of insulations again, the bonding reaction that bonding is not at low temperatures finished continues, the microcrystal silicon reaction that reaction product water that emit this moment and partial phase change obtain generates silica, becomes the buried oxide layer part of the SSOI material of making behind the microcrystal silicon complete oxidation;
7. after cooling, the upper strata oxide etch is removed, finished the making of strained-silicon-on-insulator.
The mechanism of this method is: because the density of amorphous silicon can reach 2.3～2.6g/cm
3, and the density of crystalline silicon is 2.3g/cm
3Though at the stress that amorphous silicon produced with low-pressure chemical vapor deposition (LPCVD) growth mirror-smooth (roughness is less than 1nm) below 570 ℃ is compression, but after 600 ℃ of annealing, can change compression into tensile stress, obviously be owing to the irreversible transition of amorphous silicon to microcrystal silicon taken place at 600 ℃, temperature further raises, and tensile stress reduces more than 850 ℃ the time, and the stress of film is to wait the technological parameter adjusting by annealing.Simultaneously, because the primary product of bonding reaction is a water, the water that cleans the resulting bonding reaction product of pretreated bonding by standard cleaning or nitric acid is limited, but utilize the oxygen plasma bonding techniques, can increase the bonding reaction product water as required and suitably, make in the short time part finish low-temperature bonding (this moment only firmly bonding and bonding reaction is incomplete), but bonding reaction continues in follow-up high-temperature technology, continuing slowly to emit superfluous bonding reaction product water this moment reacts with the microcrystal silicon that only needs to change tensile stress in 30 minutes at 600 ℃, form silica, finish the fully interior oxidation of microcrystal silicon.So irreversible expansion took place in volume after fine and close amorphous silicon became microcrystal silicon mutually, drive its upper strata silicon and produce tensile strain, therefore, this method is feasible.
The invention has the beneficial effects as follows: this method is controlled and the ingenious combination of the interior oxidation technology of microcrystal silicon to the irreversible transition of microcrystal silicon by fine and close smooth amorphous silicon deposition technology, low-temperature bonding technology, amorphous silicon, avoided germanium and silicon epitaxial and CMP (Chemical Mechanical Polishing) process expensive in the existing SSOI material preparation, and do not need fully as requiring follow-up considerations such as CMOS process modifications after the SGOI material, realize a kind of making of brand-new SSOI material, reach the cost of manufacture target that reduces SSOI simultaneously.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing.
One of manufacture method of the existing strained-silicon-on-insulator of Fig. 1;
Fig. 2 is the material cutaway view of initial ultra-thin SOI silicon chip;
Fig. 3 is the schematic diagram behind the fine and close smooth amorphous silicon of growth skim on the ultra-thin SOI material (α-Si) (or be aided with silicon ion inject to increase the density of amorphous silicon);
Fig. 4 is the schematic diagram behind another silicon chip;
Fig. 5 is the schematic diagram behind Fig. 3 and silicon sheet at low temperature bonding shown in Figure 4 and the attenuate;
Fig. 6 be attenuate bonding silicon chip shown in Figure 5 at the amorphous silicon of 600 ℃ of experience after the microcrystal silicon phase transformation, experience 800 ℃～1150 ℃ interior oxidation again, and remove the SSOI material schematic diagram behind the oxide of initial ultra-thin SOI material;
Fig. 7 is a legend.
Embodiment
The preparation process of strained-silicon-on-insulator of the present invention (SSOI) material is exemplified below:
1. used ultra-thin SOI silicon chip as shown in Figure 2, the thickness of top layer silicon is in 15 nanometer thickness, the thickness of buried oxide layer is at 3500 , on top layer silicon with low-pressure chemical vapor deposition grow a layer thickness the fine and close smooth amorphous silicon of 40 nanometers (α-Si), as shown in Figure 3;
2. again with the silica of another silicon substrate thermal oxide growth one deck 200 nanometers, as shown in Figure 4;
3. with the resulting silicon chip of step 1 and 400 ℃ of bonding (SiO of step 2 gained silicon sheet at low temperature
2/ α-Si);
With the silicon chip behind the bonding again attenuate corrode to the buried oxide layer of soi wafer and stop, as shown in Figure 5, the attenuate corrosion is with machinery and chemical corrosion;
5. the bonding silicon chip with step 3 gained made amorphous silicon become microcrystal silicon mutually in 30 minutes 600 ℃ of insulations;
6. will be by the bonding silicon chip of the 4th, the 5th step after the attenuate corrosion 1000 ℃ of insulations, make the not bonding reaction continuation reaction of complete reaction of low-temperature bonding, discharge the bonding reaction product water simultaneously, because the microcrystal silicon that water and phase transformation obtain reaction generates silica (SiO
2), make a buried oxide layer part that becomes prepared SSOI material behind the microcrystal silicon complete oxidation;
7. after the cooling upper strata oxide etch is removed, just finished the making of strained-silicon-on-insulator, as shown in Figure 6.
The first step of this method also can increase the density method of amorphous silicon with the method that silicon ion injects.
Above said content only is the basic explanation of the present invention under conceiving, and according to any equivalent transformation that technical scheme of the present invention is done, all should belong to protection scope of the present invention.
Claims (1)
1, a kind of manufacture method that adopts phase-change method to realize strained-silicon-on-insulator is characterized in that it may further comprise the steps:
1) being the 10-20 nanometer at top layer silicon thickness, is the fine and close smooth amorphous silicon (α-Si) of 90-110 nanometer with the low-pressure chemical vapor deposition layer thickness of growing on the top layer silicon of the ultra-thin SOI silicon chip of thickness 3000～4000 of buried oxide layer;
2) again with the silica of another silicon chip thermal oxide growth one deck 190-210 nanometer;
3) the ultra-thin SOI silicon chip that deposits amorphous silicon with step 1 gained with the silicon chip of the hot growing silicon oxide of step 2 gained at 400 ℃ of following low-temperature bondings;
4) silicon chip behind the bonding is thinned to again the buried regions silica termination of soi wafer with machinery and chemical corrosion;
5) the bonding silicon chip after will corroding again is incubated under the high temperature more than 600 ℃, makes amorphous silicon become microcrystal silicon mutually;
6) elevated temperature to 800 ℃～1150 ℃ of insulations again, the bonding reaction that bonding is not at low temperatures finished continues, this moment the reaction product water of emitting with the microcrystal silicon reaction generation silica that the step phase transformation obtains, make a buried oxide layer part that becomes the SSOI material of making behind the microcrystal silicon complete oxidation;
7) after cooling, the upper strata oxide etch is removed, finished the making of strained-silicon-on-insulator.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100252845A CN100431132C (en) | 2006-03-30 | 2006-03-30 | Making method of adopting phase-change to realizing strain silicon on insulator |
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|---|---|---|---|
| CNB2006100252845A CN100431132C (en) | 2006-03-30 | 2006-03-30 | Making method of adopting phase-change to realizing strain silicon on insulator |
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| Publication Number | Publication Date |
|---|---|
| CN1851900A true CN1851900A (en) | 2006-10-25 |
| CN100431132C CN100431132C (en) | 2008-11-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103541004A (en) * | 2012-03-22 | 2014-01-29 | 三菱综合材料株式会社 | polycrystalline silicon ingot and manufacture methode for the same |
| CN103745914A (en) * | 2013-12-24 | 2014-04-23 | 上海新傲科技股份有限公司 | Growth method of strained layer and substrate with strained layer |
| CN111146141A (en) * | 2019-12-13 | 2020-05-12 | 中国科学院微电子研究所 | Preparation method of on-chip single crystal material |
| CN115132754A (en) * | 2022-06-30 | 2022-09-30 | 惠科股份有限公司 | Backlight module, preparation method thereof and display panel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
| US6972247B2 (en) * | 2003-12-05 | 2005-12-06 | International Business Machines Corporation | Method of fabricating strained Si SOI wafers |
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2006
- 2006-03-30 CN CNB2006100252845A patent/CN100431132C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103541004A (en) * | 2012-03-22 | 2014-01-29 | 三菱综合材料株式会社 | polycrystalline silicon ingot and manufacture methode for the same |
| CN103745914A (en) * | 2013-12-24 | 2014-04-23 | 上海新傲科技股份有限公司 | Growth method of strained layer and substrate with strained layer |
| CN111146141A (en) * | 2019-12-13 | 2020-05-12 | 中国科学院微电子研究所 | Preparation method of on-chip single crystal material |
| CN115132754A (en) * | 2022-06-30 | 2022-09-30 | 惠科股份有限公司 | Backlight module, preparation method thereof and display panel |
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| CN100431132C (en) | 2008-11-05 |
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