CN1610127A - Structure of double-grid metal oxide semiconductor transistor and producig method thereof - Google Patents
Structure of double-grid metal oxide semiconductor transistor and producig method thereof Download PDFInfo
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- CN1610127A CN1610127A CN 200410067219 CN200410067219A CN1610127A CN 1610127 A CN1610127 A CN 1610127A CN 200410067219 CN200410067219 CN 200410067219 CN 200410067219 A CN200410067219 A CN 200410067219A CN 1610127 A CN1610127 A CN 1610127A
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Abstract
The double grid MOS transistor has structure including bottom grid electrode, bottom grid dielectric layer, top grid electrode, top grid dielectric layer, source area, drain area and channel area, where, the bottom grid is wider than the top grid and the channel area is monocrystal semiconductor film. The double grid MOS transistor structure has relatively bottom grid to overcome short channel effect, small top grid for high speed, and active area prepared on the large area high quality monocrystal semiconductor film for high speed and low power consumption. The preparation process of double grid structure includes preparing bottom grid, transferring monocrystal semiconductor film to upper part of bottom grid, preparing active area of transistor on the monocrystal semiconductor film, and preparing top grid dielectric layer and grid electrode to form high performance double grid MOS transistor.
Description
Affiliated field
The present invention relates to a kind of made from MOS device architecture and preparation method thereof.Belong to microelectronics technology.
Background technology
The develop rapidly of very lagre scale integrated circuit (VLSIC) has promoted the development of information industry.Contradiction between the needed high speed of huge information processing capacity, high integration and the power dissipation becomes increasingly conspicuous, and presses for the very lagre scale integrated circuit (VLSIC) of high speed, low-power consumption.
SOI (silicon on the insulator) has important effect in fields such as low pressure, low-power consumption, high temperature, anti-irradiation, be considered to 21st century silicon integrated circuit technology (Collinge J-P, Silicon-on-insulator technology:Materials to VLSI, 2
NdEd.Boston, MA, USA:KluwerAcademic Publishers, 1997).Along with the raising of device integrated level, SOI seems even more important in deep-submicron and nano-device.The SOI device is owing to active layer and substrate isolation, and parasitic capacitance is little, therefore helps improving the speed of circuit, reduces power consumption; In addition, SOI can solve device and the technological problems that some reduction of device size are brought, as latch-up of shallow junction, soft failure and body silicon CMOS (CMOS (Complementary Metal Oxide Semiconductor) transistor) etc.But in the SOI MOSFET that exhausts entirely, back of the body grid-control is made of very weak, causes the depletion region of a broad, by source electric leakage place infiltration, makes short-channel effect clearly easily.
In order to overcome the short-channel effect among the SOI MOSFET, double grids MOSFET has been proposed.Its raceway groove is the very thin silicon of one deck, and this layer silicon fiml has two grid, respectively on the two sides of raceway groove.Double grids MOSFET also have extraordinary subthreshold value characteristic curve (D.Hisamoto, " FD/DG-SOIMOSFET, " in IEDM Tech.Dig., 2001, pp.429-432.).
Double grids MOSFET since structure more special, the preparation method than conventional MOSFET complexity many, polysilicon and above the silicon dioxide insulating layer preparation active area be one of key issue.The method that preparation has the double grids MOSFET of top grid and back of the body grid mainly contains three kinds at present: first kind is the method deposition of amorphous silicon on insulating barrier that adopts chemical vapor deposition (CVD), adopt the method for high annealing or laser annealing that amorphous silicon is transformed into polysilicon then, preparation source, leakage and raceway groove (Shengdong Zhang on polysilicon then, et al, IEEE Transactions on electron devices, 50 (2003) 2297-2300; United States Patent (USP): US 6391695B1).This method can't be prepared the transistor with high mobility, thereby has limited the performance of MOSFET.Second method is perforate between insulating barrier and substrate, adopt the method for epitaxial lateral overgrowth to prepare preparation (the Hon-Sum Philip Wong that monocrystalline silicon thin film is used for active area, et al., IEDM, (1997) P 427-430), though this method can form monocrystalline silicon, the difficult control of quality.The third method is behind epitaxial monocrystalline silicon on the germanium silicon, the germanium sacrificial silicon layer is removed, form the monocrystalline silicon bridge, and then thermal oxidation and deposit spathic silicon, formation has the double-gated devices (S.Harrism, IEDM (2003) P449-452) of top grid and bottom gate, this method complex process, and because bottom polycrystalline grid are to form under the monocrystalline silicon bridge, the difficult control of its technology.
Summary of the invention
The present invention proposes a kind of novel double grids MOSFET structure and preparation method, in this structure, long bottom gate is used to overcome short-channel effect, and the top grid purpose of trying one's best little is for raising speed, the active area preparation is on the large-area high-quality single-crystal semiconductor thin film, can improve speed, reduce power consumption.Single-crystal semiconductor thin film is obtained by the film transfer technology among the present invention, can obtain the single-crystal semiconductor thin film of large-area high-quality, and technology is simple.This double grids MOSFET structure also can be applied on double-deck static random access memory.
Made from MOS transistor provided by the invention, comprise bottom gate electrode, bottom gate dielectric layer, top gate electrode, top gate dielectric layer, source region, drain region and channel region, wherein bottom gate is than top grid width, and channel region is semiconductive thin films such as monocrystalline silicon, germanium silicon, strained silicon.
The transistorized preparation method of high-quality made from MOS (MOS) who is provided comprises: prepare bottom gate electrode and gate dielectric layer on insulating barrier, comprising: polysilicon, TiN and oxide layer; The single crystal semiconductor substrate that will contain the substrate of bottom gate and another potting defectiveness layer is bonding at room temperature; Bonding pad is peeled off at the defect layer place; Method with chemico-mechanical polishing is thrown the surface flat; The source and the leakage of preparation metal oxide semiconductor transistor on semiconductive thin film; Prepare top gate dielectric layer and gate electrode.
Concrete prepared process is:
On oxidized silicon chip by photoetching, etching, prepare preparation top gate line required hole;
2. cross embrane method with chemical vapour deposition technique or sputter and in the hole, deposit W or a kind of metal gate of tungsten silicide, and, realize flattening surface simultaneously with the metal removal of chemical Mechanical Polishing Technique with surface deposition;
3. be approximately 1000～2000 with reactive ion etching method etching metal to residual thickness, in the hole, further deposit transition zone material and the 2500-4500 polysilicon membrane of 100～500 ;
4. remove with chemical Mechanical Polishing Technique polysilicon and transition zone material that the surface is unnecessary, and make surfacingization;
5. with the oxide layer of the method for thermal oxidation or atomic layer growth growth 10～150 ;
6. will contain the semiconductor chip low-temperature bonding that the substrate of carrying on the back grid and another boron hydrogen are annotated altogether; Before bonding, two bonding surfaces are cleaned in RCA1 (ammoniacal liquor, hydrogen peroxide and deionized water) that adjusts and RCA2 (hydrochloric acid, hydrogen peroxide and deionized water), then oxygen plasma is carried out on two bonding pad surfaces and activate.The condition of oxygen plasma is: 15 millibars of air pressure, plasma power are 100W, and oxygen flow is 80sccm.After cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.Bonding pad was annealed 5 minutes down at 300-400 ℃, and bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.
7. after with chemical Mechanical Polishing Technique the semiconductive thin film surface throwing of shifting being put down, the leakage and the source of preparation MOS transistor on semiconductive thin film.
8. further prepare the top grid, comprise gate oxide, polysilicon and metal gate.
9. preparation line.
The preparation method of described dual-gate MOS transistor is characterized in that defect layer is to annotate hydrogen layer, boron hydrogen to annotate layer, hydrogen helium altogether and annotate a kind of in layer or the porous silicon altogether.Among the present invention, the hydrogen in the defective buried regions, boron, helium plasma are introduced by ion implantor, and the semi-conductive thickness of the position of defective buried regions and top layer is by the energy decision of ion implantor.The dosage of hydrogen ion and helium ion is (4-9) * 10
16Cm
-2, the dosage of boron ion is 5 * 10
14Cm
-2～5 * 10
15Cm
-2Imbedding of porous layer is to adopt earlier electrochemical method to prepare porous silicon, epitaxy single-crystal semiconductor layer on the porous silicon substrate again, like this below the single-crystal semiconductor layer with regard to potting porous silicon.
Described dual-gate MOS transistor preparation method, it is characterized in that low-temperature bonding, two bonding pads elder generation is bonding at room temperature, is to strengthen bond strength, before bonding, two substrate surfaces are carried out chemistry or plasma treatment, descend long term annealing at low temperature (temperature is less than 400 ℃) behind the bonding.
Described dual-gate MOS transistor preparation method is characterized in that low temperature peels off, and the method for peeling off is a kind of in low-temperature heat or the mechanical stripping, goes out to peel off at defect layer.The method that adopts boron, hydrogen to annotate altogether can make exfoliation temperature be lower than 400 ℃, and wherein hydrogen ion dosage is (1～9) * 10
16Cm
-2, the dosage of boron ion is 5 * 10
15Cm
-2～5 * 10
16Cm
-2Mechanical stripping comprises wedge insertion, water column impact etc.
Described dual-gate MOS transistor preparation method is characterized in that the porous silicon buried regions is an epitaxial semiconductor layer on the porous silicon substrate that adopts electrochemical production.The peeling off of porous silicon comprise hot soarfing from and mechanical stripping.
Made from MOS transistor arrangement of the present invention, long bottom gate is used to overcome short-channel effect, and the top grid purpose of trying one's best little is for raising speed, and active area prepares on the large-area high-quality single-crystal semiconductor thin film, can improve speed, reduce power consumption.The preparation method of this double-gate structure is, afterwards single-crystal semiconductor thin film is transferred to bottom gate top preparing bottom gate (comprising gate electrode and gate dielectric layer), the transistorized active area of preparation on high-quality single-crystal semiconductor thin film, prepare top gate dielectric layer and gate electrode then, form high performance made from MOS transistor.
Description of drawings
Fig. 1 is the preparation of Damascus fairlead.Wherein 10 is insulating barriers, the 11st, and the hole of in insulating barrier, opening.
Fig. 2 is the deposition of tungsten.In hole 11, insert tungsten 12, and throw its surface flat with chemical Mechanical Polishing Technique.
Fig. 3 is the etching of tungsten.Residual thickness is approximately 1000～2000 , exposes hole 13.
Fig. 4 is the preparation of polysilicon gate.In hole 13, insert the TiN film 14 of 100～500 and 2500-4500 polysilicon membrane 15 bottom gate as MOS transistor.
Fig. 5 is a flattening surface.Polysilicon and the TiN surface is unnecessary with chemical Mechanical Polishing Technique remove, and make surfacingization.
Fig. 6 is the preparation of thin oxide layer in the bottom gate.16 is oxide layers of 10～150 .
Fig. 7 is a bonding process, the substrate shown in Fig. 6 and is contained the semiconductor chip bonding of defect layer 21.Wherein 20 is silicon substrates, the 22nd, and a kind of in the semiconductive thin films such as silicon, germanium silicon, strained silicon.Before bonding, oxide layer 16 and semiconductive thin film 22 surfaces are carried out chemical cleaning and plasma treatment.
Fig. 8 is that the bonding substrate contains the substrate of carrying on the back grid after peel off at the defect layer place, and semiconductive thin film 22 is transferred on the insulating barrier, and the surface is thrown flat with chemical Mechanical Polishing Technique.
Fig. 9 prepares MOS transistor on semiconductive thin film 22 substrates, wherein 31 is the source region, and 32 is the drain region, and 33 is the top gate oxide, and 34 is polysilicon gate, and 35 is metal gate.
Figure 10 is the preparation technology who contains the bubble defect layer.Figure A is the bottom that hydrogen ion and boron ion is injected into semiconductor layer 22, and semiconductor layer comprises semiconductive thin films such as silicon, germanium silicon, strained silicon, forms the defect layer 211 shown in the figure B.This substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby monocrystalline silicon thin film is transferred to the insulating substrate that contains device.(shown in Fig. 7 and 8) Figure 11 is the preparation technology who contains the semiconductor chip of porous silicon defect layer.20 is heavy mixed silicon slices among the figure A; Silicon chip is placed on HF and alcoholic solution, adopts anodised method to form porous silicon 212; Figure B is an epitaxial semiconductor film 222 on porous silicon 212, so just formed the semiconductor chip that contains porous silicon layer, this substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby semiconductor layer is transferred to the insulating substrate that contains device.(shown in Fig. 7 and 8)
Embodiment
Following examples will help to understand the present invention, but not limit content of the present invention.
Embodiment 1:
Dual-gate MOS transistor and preparation method thereof.
Be illustrated in figure 9 as dual-gate MOS transistor structure of the present invention, its concrete processing step is:
On oxidized silicon chip by photoetching, etching, prepare the required hole 11 of preparation back of the body grid; (referring to Fig. 1)
2. with method deposits tungsten in the hole of chemical vapour deposition (CVD), at first use WF
6" hydrogen reduction reaction " takes place in gas and hydrogen, carries out the crystal growth layer deposition, uses WF then
6" silicomethane reduction reaction " takes place in gas and silicomethane, and reaction temperature is 400 ℃.With chemical Mechanical Polishing Technique the tungsten on surface is removed, polishing fluid is the Semi-Sperse W2585 of Cabot company, realizes flattening surface; (referring to Fig. 2)
3. etching tungsten to residual thickness is approximately 1500 , further deposits TiN film and the 3500 polysilicon membranes of 250 in the hole; (referring to Fig. 3 and 4)
4. remove with chemical Mechanical Polishing Technique polysilicon and TiN that the surface is unnecessary, and make surfacingization; (referring to Fig. 5)
5. with grow oxide layer about 100 of the method for thermal oxidation, oxidizing temperature is 400 ℃; (referring to Fig. 6)
6. will contain the semiconductor chip low-temperature bonding that the substrate of carrying on the back grid and another boron hydrogen are annotated altogether; Before bonding with two bonding surfaces deionized water=1: 3: 10) and RCA2 (hydrochloric acid: hydrogen peroxide: clean deionized water=1: 1: 5), then the oxygen plasma activation is carried out on two bonding pad surfaces at the RCA1 that adjusts (ammoniacal liquor: hydrogen peroxide:.The condition of oxygen plasma is: 15 millibars of air pressure, plasma power are 100W, and oxygen flow is 80sccm.After cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.Bonding pad was annealed 5 minutes down at 300-400 ℃, and bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.(referring to Fig. 7 and 8)
7. after with chemical Mechanical Polishing Technique the semiconductive thin film surface throwing of shifting being put down, the leakage and the leakage of preparation MOS transistor on semiconductive thin film.(referring to Fig. 9)
8. further prepare the top grid, comprise gate oxide, polysilicon and metal gate.(referring to Fig. 9)
9. preparation line.
Embodiment 2:(is referring to Figure 10)
Be that to contain the concrete preparation technology of (100) silicon chip of bubble defective buried regions as follows:
1. on the body silicon substrate, adopt high vacuum chemical vapour deposition epitaxial germanium-silicon thin membrane (content of Ge is 15%), take out growth room's vacuum to 10
-10Torr base is pressed, and heating target platform to 500 ℃ feeds disilane and Germane gas and carries out film growth.
2. at first implantation dosage is 1 * 10
15Cm
-2The boron ion, implantation dosage is 5 * 10 then
16Cm
-2Hydrogen ion, the ion implanted layer degree of depth is at germanium silicon layer and silicon substrate at the interface.All the other are with embodiment 1.
Embodiment 3:(is referring to Figure 11)
Contain the preparation of the semiconductor chip of buried porous layer, concrete technology is as follows:
Adopting P type, (100) crystal orientation, resistivity is the silicon chip of 0.01-0.02 Ω cm, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2For stablizing the pre-oxidation 1 hour under 400 ℃ oxygen atmosphere of porous silicon structure.Remove the porous silicon surface oxide layer with the HF weak solution before the extension.The vacuum degree of outer time-delay ultra high vacuum plated film instrument is 10
-9Mbar, beginning 10nm silicon epitaxy speed is 0.02nm/S, is 0.04nm/S afterwards, underlayer temperature is 800 ℃.All the other are with embodiment 1.
Claims (9)
1, the transistorized structure of a kind of made from MOS is characterized in that it is made of bottom gate electrode, bottom gate dielectric layer, top gate electrode, top gate dielectric layer, source region, drain region and channel region; Bottom gate is than top grid width, and channel region is a semiconductive thin film, and active area is on single-crystal semiconductor thin film.
2, according to the transistorized structure of the described made from MOS of claim 1, it is characterized in that described single-crystal semiconductor thin film be in monocrystalline silicon, germanium silicon, the strained silicon any one, bottom gate electrode and gate dielectric layer are polysilicon, TiN and oxide layer.
3, the transistorized preparation method of a kind of made from MOS is characterized in that preparing bottom gate electrode and gate dielectric layer on insulating barrier; The single crystal semiconductor substrate that will contain the substrate of bottom gate and a potting defectiveness layer is bonding at room temperature; Bonding pad is peeled off at the defect layer place; Method with chemico-mechanical polishing is thrown the surface flat; The source and the leakage of preparation metal oxide semiconductor transistor on semiconductive thin film; Prepare top gate dielectric layer and gate electrode.
4, by the transistorized preparation method of the described made from MOS of claim 3, it is characterized in that concrete prepared process is:
1. on the oxidized silicon chip by photoetching, etching, prepare preparation top gate line required hole;
2. chemical vapour deposition technique or sputter are crossed embrane method and deposit W or a kind of metal gate of tungsten silicide in the holes, and with the metal removal of chemical Mechanical Polishing Technique with surface deposition, realize flattening surface simultaneously;
3. be approximately 1000～2000 with reactive ion etching method etching metal to residual thickness, in the hole, further deposit transition zone material and the 2500-4500 polysilicon membrane of 100～500 ;
4. remove with chemical Mechanical Polishing Technique polysilicon and transition zone material that the surface is unnecessary, and make surfacingization;
5. with the oxide layer of the method for thermal oxidation or atomic layer growth growth 10～150 ;
6. will contain the semiconductor chip low-temperature bonding that the substrate of carrying on the back grid and another boron hydrogen are annotated altogether; Before bonding, two bonding surfaces are successively cleaned in ammoniacal liquor, hydrogen peroxide and deionized water and hydrochloric acid, hydrogen peroxide and deionized water, then oxygen plasma being carried out on two bonding pad surfaces activates, after cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.Bonding pad was annealed 5 minutes down at 300-400 ℃, and bonding pad is peeled off at notes hydrogen layer place, in order to improve bond strength, anneals 4 hours down at 400 ℃;
7. after with chemical Mechanical Polishing Technique the semiconductive thin film surface throwing of shifting being put down, the leakage and the source of preparation MOS transistor on semiconductive thin film;
8. further prepare the top grid, comprise gate oxide, polysilicon and metal gate;
9. prepare line.
5,, it is characterized in that defect layer is to annotate hydrogen layer, boron hydrogen to annotate layer, hydrogen helium altogether and annotate a kind of in layer or the porous silicon altogether according to claim 3 or the transistorized preparation method of 4 described made from MOS.
6, according to the described made from MOS transistor of claim 4 preparation method, it is characterized in that:
A. hydrogen ion dosage is (4～9) * 10
16Cm
-2
B. the dosage of boron ion is 5 * 10
15Cm
-2～5 * 10
16Cm
-2
C. to imbed be gloss electrochemical production porous silicon to porous layer, epitaxy single-crystal semiconductor layer on the porous silicon substrate again, and with this epitaxial wafer with contain the insulating barrier substrate bonding of carrying on the back grid.
7,, it is characterized in that a kind of in heating or the machinery of method that defect layer peels off according to the described made from MOS transistor of claim 4 preparation method.
8, by the described made from MOS transistor of claim 6 preparation method, the method that it is characterized in that epitaxial monocrystalline silicon on the porous silicon substrate is any one of the outer Yanzhong of chemical vapour deposition (CVD), molecular beam epitaxy or electron beam.
9, by the described made from MOS transistor of claim 4 preparation method, the condition that it is characterized in that two bonding pad surfaces are carried out plasma-activated is 15 millibars of air pressure, and plasma power is 100W, and oxygen flow is 80sccm.
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| CN102956699A (en) * | 2011-08-22 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor device |
| CN101017783B (en) * | 2006-02-06 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for making the separated dual-bar field effect transistor |
| US9012963B2 (en) | 2011-08-22 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device |
| CN104617101A (en) * | 2013-11-05 | 2015-05-13 | 台湾积体电路制造股份有限公司 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
| US9601624B2 (en) | 2014-12-30 | 2017-03-21 | Globalfoundries Inc | SOI based FINFET with strained source-drain regions |
| CN107063498A (en) * | 2017-05-19 | 2017-08-18 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of temperature sensor and preparation method thereof |
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| CN1224087C (en) * | 2002-08-26 | 2005-10-19 | 中国科学院微电子中心 | Fluted plane bigrid structure MOS device and its manufacturing method |
| US6833569B2 (en) * | 2002-12-23 | 2004-12-21 | International Business Machines Corporation | Self-aligned planar double-gate process by amorphization |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101017783B (en) * | 2006-02-06 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for making the separated dual-bar field effect transistor |
| CN102956699A (en) * | 2011-08-22 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor device |
| US9012963B2 (en) | 2011-08-22 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device |
| CN102956699B (en) * | 2011-08-22 | 2015-05-06 | 中国科学院微电子研究所 | Semiconductor device |
| CN104617101A (en) * | 2013-11-05 | 2015-05-13 | 台湾积体电路制造股份有限公司 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
| US9601624B2 (en) | 2014-12-30 | 2017-03-21 | Globalfoundries Inc | SOI based FINFET with strained source-drain regions |
| CN107063498A (en) * | 2017-05-19 | 2017-08-18 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of temperature sensor and preparation method thereof |
| CN111146141A (en) * | 2019-12-13 | 2020-05-12 | 中国科学院微电子研究所 | Preparation method of on-chip single crystal material |
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