CN1599076A - Quasi-dual-gate field effect transistor - Google Patents
Quasi-dual-gate field effect transistor Download PDFInfo
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- CN1599076A CN1599076A CN 200410009436 CN200410009436A CN1599076A CN 1599076 A CN1599076 A CN 1599076A CN 200410009436 CN200410009436 CN 200410009436 CN 200410009436 A CN200410009436 A CN 200410009436A CN 1599076 A CN1599076 A CN 1599076A
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- grid
- effect transistor
- field effect
- gate field
- quasi
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- 230000005669 field effect Effects 0.000 title claims abstract description 24
- 230000009977 dual effect Effects 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000002156 mixing Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
- H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
Abstract
The invention provides a quasi dual junction grid field effect transistor and belongs to the field of the micro-electronic semiconductor technology. The quasi dual junction grid field effect transistor includes the source, drain region, isolation region, body, front grid and back grid. The front grid is the multi crystalline silicon and there is a layer of grid oxygen between the front grid and the channel region. The back grid is the adulterated single crystal of silicon and connects with the body directly to form the P-N junction. Compared with the traditional FinFET, the structure of the invention has two different types of control grids. The back grid (P-N junction gate) is used to exhaust the channel region and to restrain the leakance, while the front grid is used to make the inversion layer in the channel region and to produce great drive current. That the back grid and the front grid of the invention connect with each other directly increases the grid control power of the device greatly and dulls the restrain to the breadth of the isolation region.
Description
Technical field
The invention belongs to the semiconductor microelectronics technical field, be specifically related to a kind of quasi dual gate field effect transistor.
Background technology
Along with constantly dwindling of device size, the leakage current of device becomes the major obstacle that device dwindles.In recent decades, researcher constantly proposes new technology and device architecture, such as SOI (Silicon-on-Insulator) technology, and double-gated devices, tri-gate devices, the Ω gate device, or even enclose gate device.Purpose all is in order to reduce the leakage current of device, the grid-control ability of enhance device.Through development in recent years, double-gated devices is shown one's talent gradually, is generally believed it is one of device that most possibly is used in industrial quarters by scientific circles.Double-gated devices has very perfectly electrology characteristic, for example very little leakage current, very big drive current and very desirable subthreshold characteristic.And FinFET is realized effective and efficient manner (X.Huang, W.-C.Lee, C.Kuo, the D.Hisamoto of double-gate structure always by understanding, L.Chang, J.Kedzierski, E.Anderson, H.Takeuchi, Y.-K.Choi, K.Asano, V.Subramanian, T.-J.King, J.Bokor, C.Hu, " Sub-50nm P-channel FinFET, " IEEE Trans.Electron Devices, vol.48, pp.880-886, May 2001.).With reference to figure 1, the FinFET field-effect transistor comprises: the control gate of source, drain region 3, isolated area 6, body 4 and two symmetries, be provided with isolated area 6 between source, drain region 3 and the body 4, preceding grid 1 and back grid 5 are polysilicon, are equipped with grid oxygen 2 between preceding grid 1 and body 4, back grid 5 and the body 4.For FinFET, in order effectively to suppress its leakage current, the width of isolated area (fin) must constantly reduce, but the width of fin can cause the parasitic series resistance of FinFET very big as very little, and its drive current is lost.For example for the FinFET of 10 nanometers, in order to suppress its leakage current, the width of its fin can not be greater than 5 nanometers, and this is to be difficult to realize on technology.And along with the reducing of device size, the thermoelectronic effect of device becomes more and more serious, and therefore the integrity problem of grid oxygen becomes more and more serious, thereby influences the integrated on a large scale of device.
Summary of the invention
The present invention has overcome the fault of construction of above-mentioned FinFET field-effect transistor, a kind of quasi dual gate field effect transistor is provided, both can obtain the electrology characteristic of very low leakage current and very high drive current, the thermoelectronic effect of device can obtain very big alleviation again, thereby more helps integrated on a large scale.
Another object of the present invention is: alleviated the restriction to the isolated area width.
Technology contents of the present invention: a kind of quasi dual gate field effect transistor, comprise: source, drain region, body and forward and backward grid, be provided with isolated area between source, drain region and the body, it is characterized in that: preceding grid are polysilicon, be provided with grid oxygen between preceding grid and the body, the monocrystalline silicon of back grid for mixing, back grid are fixedlyed connected with body, form the P-N knot.
The width of body can be controlled in 3/5～1 scope of forward and backward gate length.
The width of isolated area can be 2～4 times of length of forward and backward grid.
The length controlled of isolated area is built in 1～1.5 times of the length of forward and backward grid.
The source-drain area doping content can be greater than 1 * 10
20Cm
-3, the doping effect is N
+
The body doping content can be controlled in 1 * 10
13Cm
-3～1 * 10
17Cm
-3Between, the doping effect is P
-
The isolated area doping content can be greater than 1 * 10
19Cm
-3, the doping effect is N
+
Forward and backward grid doping content can be higher than 1 * 10
20Cm
-3, the doping effect is P
+
Technique effect of the present invention: the structure that is different from traditional FinFET field-effect transistor, two control gates adopt different structures, wherein the back grid are the monocrystalline silicon of doping, realized that control gate directly is connected with body, strengthened the grid-control ability of device greatly, alleviated restriction, and because this control gate provides heat conducting approach, the thermoelectronic effect of device has obtained very big alleviation to the isolated area width; On the other hand,, can obtain very high drive current, thereby realize low electric leakage easily, the high superperformance that drives because preceding grid are common polysilicon gate.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is a traditional double grid field effect transistor structural representation;
Fig. 2 is a quasi dual gate field effect transistor structural representation of the present invention.
Grid 6---isolated area behind grid 2-grid oxygen 3-source, the drain region 4---body 5---before the 1---
Fig. 3 is the influences of two different control gates to device performance.
Concrete embodiment
With reference to figure 2, quasi dual gate field effect transistor of the present invention comprises: source region 3, drain region 3, isolated area 6, body 4 and preceding grid 1, back grid 5, be provided with isolated area 6 between source, drain region 3 and the body 4, preceding grid 1 are polysilicon, be provided with one deck grid oxygen 2 between preceding grid 1 and the body 4, the monocrystalline silicon of back grid 5 for mixing, back grid 5 directly are connected with body 4, form the P-N knot.Because be connected between back grid and the body, the width of body can be controlled in 3/5～1 scope of forward and backward gate length, the width of isolated area also can be 2～4 times of length of forward and backward grid, and the length controlled of isolated area is built in 1～1.5 times of the length of forward and backward grid.
Design parameter of the present invention is as follows: with forward and backward gate length is that the quasi dual gate field effect transistor of 15nm is an example, and wherein the length of body is 15nm, and the width of body is 12nm, and the body impurity is a boron, forms P
-Doping effect, doping content are 1 * 10
13Cm
-3～1 * 10
17Cm
-3Between; The width of isolated area is 30nm; The length of isolated area is 20nm, and the isolated area doping content can be greater than 1 * 10
19Cm
-3, the doping effect is N
+Source-drain area length is 80nm, and the width of source-drain area is 200nm, and source-drain area mixes and forms N
+The district, doping content is greater than 1 * 10
20Cm
-3Forward and backward grid doping content can be higher than 1 * 10
20Cm
-3, the doping effect is P
+The grid oxygen that is provided with between preceding grid and the body, gate oxide thickness is 1nm.
According to the design parameter of above-mentioned quasi dual gate field effect transistor, adopt N type＜100 of 4 inch 400 micron thickness〉single polishing monocrystalline silicon piece, resistivity 2-4 Ω cm, the technical process and the parameter of preparation quasi dual gate field effect transistor are as follows:
1, silicon chip carries out oxidation after cleaning, and the thickness of silicon dioxide is 30-40nm, deposit 100-150nm silicon nitride etch groove, and the width of groove is 40nm, implanted dopant boron forms back of the body grid N
+The district after the annealing, forms 1.0 * 10
20Centimetre
-3, and from monocrystalline silicon surface 30nm; Carry out the threshold value adjustment and inject phosphorus, the injection degree of depth is 30nm, and forming concentration is 1 * 10
15Cm
-3The body light doping section; These two different doping form characteristic gate modulation structure---the p-n junction of device of the present invention;
2, gate oxidation 1 nanometer, deposit polysilicon 160nm, impurity boron reaches P after the annealing
+The grid-control district;
3, chemical polishing polishes to silicon nitride; Corroding silicon nitride cleans up;
4, implanted dopant phosphorus reaches 1.0 * 10 after the annealing
20Cm
-3N
+The district, the source-drain area of formation device;
5, deposit passivation layer, opening contact hole, metal line;
6, deposit protective layer, encapsulation.
Compare with traditional FinFET, the present invention has two dissimilar control gates, and Fig. 3 has provided the influence of two different control gates to device performance, can clearly be seen that the not same-action of two different grid, wherein back grid (P-N ties grid) are used for exhausting channel region, suppress leakage current; Preceding grid are used for producing inversion layer at channel region, produce big drive current.Adopt fluid dynamics and quantum effect model in the simulation; Composite model has adopted SRH, Auger, Band2band and Avalanche model; The mobility model has adopted doping Dependence, Highfield saturation, Enormal and PhuMob model.
Claims (8)
1, a kind of quasi dual gate field effect transistor, comprise: source, drain region, body and forward and backward grid, be provided with isolated area between source, drain region and the body, it is characterized in that: preceding grid are polysilicon, before be connected by grid oxygen between grid and the body, the monocrystalline silicon of back grid for mixing, back grid are fixedlyed connected with body, form the P-N knot.
2, quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: the width of body is controlled at 3/5～1 scope of forward and backward gate length.
3, quasi dual gate field effect transistor as claimed in claim 1 or 2 is characterized in that: the width of isolated area is 2～4 times of length of forward and backward grid.
4, quasi dual gate field effect transistor as claimed in claim 3 is characterized in that: the length of isolated area is controlled at 1～1.5 times of length of forward and backward grid.
5, quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: the source-drain area doping content is greater than 1 * 10
20Cm
-3, the doping effect is N
+
6, quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: the body doping content is controlled at 1 * 10
13Cm
-3～1 * 10
17Cm
-3Between, the doping effect is P
--
7, quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: the isolated area doping content is greater than 1 * 10
19Cm
-3, the doping effect is N
+
8, quasi dual gate field effect transistor as claimed in claim 1 is characterized in that: forward and backward grid doping content is higher than 1 * 10
20Cm
-3, the doping effect is P
+
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410009436 CN1599076A (en) | 2004-08-17 | 2004-08-17 | Quasi-dual-gate field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410009436 CN1599076A (en) | 2004-08-17 | 2004-08-17 | Quasi-dual-gate field effect transistor |
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| Publication Number | Publication Date |
|---|---|
| CN1599076A true CN1599076A (en) | 2005-03-23 |
Family
ID=34662483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410009436 Pending CN1599076A (en) | 2004-08-17 | 2004-08-17 | Quasi-dual-gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1599076A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011160424A1 (en) * | 2010-06-24 | 2011-12-29 | 复旦大学 | Grid-control pn field effect transistor and controlling method thereof |
| CN104659084A (en) * | 2015-02-11 | 2015-05-27 | 中国电子科技集团公司第五十八研究所 | Anti-radiation fin-type channel dual-gate field effect transistor and manufacturing method thereof |
-
2004
- 2004-08-17 CN CN 200410009436 patent/CN1599076A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011160424A1 (en) * | 2010-06-24 | 2011-12-29 | 复旦大学 | Grid-control pn field effect transistor and controlling method thereof |
| CN104659084A (en) * | 2015-02-11 | 2015-05-27 | 中国电子科技集团公司第五十八研究所 | Anti-radiation fin-type channel dual-gate field effect transistor and manufacturing method thereof |
| CN104659084B (en) * | 2015-02-11 | 2017-09-26 | 中国电子科技集团公司第五十八研究所 | Radioresistance fin channel dual-bar field-effect transistor and preparation method thereof |
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