CN1591786B - A selective etch process for making a semiconductor device having a high-K gate dielectric - Google Patents
A selective etch process for making a semiconductor device having a high-K gate dielectric Download PDFInfo
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- CN1591786B CN1591786B CN2004100570938A CN200410057093A CN1591786B CN 1591786 B CN1591786 B CN 1591786B CN 2004100570938 A CN2004100570938 A CN 2004100570938A CN 200410057093 A CN200410057093 A CN 200410057093A CN 1591786 B CN1591786 B CN 1591786B
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
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- 238000005516 engineering process Methods 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
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- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000002253 acid Substances 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 229910052736 halogen Inorganic materials 0.000 claims description 6
- 150000002367 halogens Chemical class 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 150000004820 halides Chemical class 0.000 claims description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- XRFHCHCLSRSSPQ-UHFFFAOYSA-N strontium;oxygen(2-);titanium(4+) Chemical class [O-2].[O-2].[O-2].[Ti+4].[Sr+2] XRFHCHCLSRSSPQ-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 2
- 229910052788 barium Inorganic materials 0.000 claims description 2
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 2
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- -1 yittrium oxide Chemical compound 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 3
- 125000005843 halogen group Chemical group 0.000 claims 2
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 claims 1
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XDXSUJKMVSURTH-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[O--].[Sc+3].[Ta+5].[Pb++] Chemical compound [O--].[O--].[O--].[O--].[O--].[Sc+3].[Ta+5].[Pb++] XDXSUJKMVSURTH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 239000012702 metal oxide precursor Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Chemical & Material Sciences (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.
Description
Technical field
The method that the present invention relates to be used for producing the semiconductor devices specifically, relates to the method that is used to make the semiconductor device that comprises high dielectric constant gate dielectric layer.
Background technology
The conventional method that is used for etching high-k (k) gate dielectric is used anisotropic plasma etch and isotropism wet etching technique.If the speed of dry etch process etched substrate is far faster than the dielectric speed of its etching, dry etching may damage the substrate that is positioned at below the high k gate-dielectric so.Though wet-etching technology can be with respect to the substrate selective etch dielectric of below, this technology may etching be positioned at the dielectric below the gate electrode, and this may weaken or this structure of cutout.
Therefore, need a kind of improvement technology that is used to make the semiconductor device that comprises high k gate-dielectric.Need such technology, promptly with respect to the substrate of below and with respect to covered by gate electrode that part of of high K film and the exposed portions serve of the high k film of selective etch.Method of the present invention provides this technology.
Summary of the invention
According to a first aspect of the invention, the invention provides a kind of method that is used for producing the semiconductor devices, comprising: on substrate, form high dielectric constant gate dielectric layer; And add impurity the first of described high dielectric constant gate dielectric layer to, to guarantee and can optionally remove described first with respect to the second portion of described high dielectric constant gate dielectric layer.
According to a second aspect of the invention, the present invention also provides a kind of method that is used for producing the semiconductor devices, and comprising: form high dielectric constant gate dielectric layer on substrate; On described high dielectric constant gate dielectric layer, form gate electrode; The described gate electrode of etching is to expose the first of described high dielectric constant gate dielectric layer; In the described first of described high dielectric constant gate dielectric layer, add impurity; And the described first of optionally removing described high dielectric constant gate dielectric layer with respect to the second portion of described high dielectric constant gate dielectric layer.
According to a third aspect of the invention we, the invention provides a kind of method that is used for producing the semiconductor devices, comprising: on substrate, form high dielectric constant gate dielectric layer; On described high dielectric constant gate dielectric layer, form gate electrode based on polysilicon; The described gate electrode based on polysilicon of etching is to expose the first of described high dielectric constant gate dielectric layer; Use plasma enhanced chemical vapor deposition technology in the first of described high dielectric constant gate dielectric layer, to add impurity; Then, the first with described high dielectric constant gate dielectric layer is exposed in the acid of selecting from comprise the group that contains hydracid and phosphoric acid.
Description of drawings
Figure 1A represents the cross section of the structure that may form when realizing the embodiment of the inventive method to Fig. 1 D.Do not draw in proportion in the feature shown in these figure.
Embodiment
A kind of method that is used for producing the semiconductor devices has been described.This method is included on the substrate and forms high k gate dielectric, and the first of the described high k gate dielectric of modification is to guarantee and can optionally remove this first with respect to the second portion of described high k gate dielectric.In the following description, a large amount of details have been provided to provide to complete explanation of the present invention.But, for a person skilled in the art clearly, except those modes of clear description here, can also implement the present invention in a lot of modes.Therefore, the invention is not restricted to the detail that describes below.
In the method for the invention, on substrate, form high k gate dielectric.Substrate can comprise body silicon or silicon-on-insulator minor structure.Perhaps, substrate can comprise other materials---it can not make up with silicon with the silicon combination yet---for example: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though described several examples of the material that can form substrate here, can be used as basic any material of making semiconductor device thereon and all drop in the spirit and scope of the present invention.
High k gate dielectric will comprise the material of its dielectric constant greater than the dielectric constant of silicon dioxide.Preferably, the dielectric constant of high k gate dielectric is at least about the twice of the dielectric constant of silicon dioxide, that is, its dielectric constant is approximately greater than 8.The material that is used to make high k gate dielectric comprises: hafnium oxide, hafnium silicon oxide, lanthana, zirconia, silica zirconium, titanium oxide, tantalum oxide, strontium titanium oxides barium, titanium oxide barium, strontium titanium oxides, yittrium oxide, aluminium oxide and tantalum oxide scandium lead.Especially preferred is hafnium oxide, zirconia, titanium oxide and aluminium oxide.Though described some examples of the material that can be used to form high k gate dielectric here, described layer can be made by other materials, and this is clearly to those skilled in the art.
Can use the conventional deposition method of for example traditional chemical vapour deposition (" CVD "), low pressure chemical vapor deposition or physical vapour deposition (PVD) (" PVD ") technology on substrate, to form high k gate dielectric.Preferably, use traditional atomic layer CVD technology.In this technology, can in the CVD reactor, supply with metal oxide precursor (for example metal chloride) and steam with the flow velocity of selecting, this reactor is worked under the selection temperature and pressure then, to generate the smooth interface of atom level between substrate and high k gate dielectric.The CVD reactor should be worked the sufficiently long time, has the layer of expectation thickness with formation.In major applications, the thickness of high k gate dielectric should be less than about 40 dusts, and more preferably at about 5 dusts between about 20 dusts---promptly, thickness is less than or equal to about 5 monoatomic layers.
Deposit like this, high k gate dielectric may comprise the impurity of not expecting, for example residual chlorine, and it can make described layer incompatible with polysilicon.Can after having absorbed the considerable impurity that is present at first in the high k gate dielectric, remove this sacrifice layer sacrifice layer then and come the described layer of purifying by deposition of sacrificial layer on described laminar surface.Perhaps, can then this metal level be reoxidized, come the high k gate dielectric of purifying by described layer is reduced to metal level.For example the oxygen content that increases in the high k gate dielectric by wet method or dry oxidation technology may be gratifying.In order to guarantee and compatibility based on the gate electrode of polysilicon, can otherwise come the high k gate dielectric of modification, for example, perhaps can between film and gate electrode, the intermediate layer be set by to wherein adding nitrogen.
On substrate, form after the high k gate dielectric, can on this layer, form gate electrode.In a preferred embodiment, gate electrode comprises polysilicon.Can be by at first deposit spathic silicon layer 102---the structure of generation Fig. 1 a forms such gate electrode on dielectric layer 101 and substrate 100.Can use conventional method to come deposit spathic silicon layer 102, and its thickness is preferably at about 500 dusts between about 4000 dusts.Then, can etch polysilicon layer 102, with the first 103 that exposes high k gate dielectric 101, generate the structure of Fig. 1 b.
After etch polysilicon layer 102, must remove the first 103 of exposing.But before etching first 103, method modification of the present invention first 103 is shown in Fig. 1 c, to guarantee and can come selective removal first 103 with respect to the second portion 104 of high k gate dielectric 101.Can add the first 103 that impurity comes the high k gate dielectric 101 of modification by this part to dielectric layer.In a preferred embodiment, impurity comprises halogen, and described halogen can be included in the halogenic molecule or can close to form halide with hydrogenation.
Can use plasma enhanced chemical vapor deposition (" PECVD ") technology in the first 103 of high k gate dielectric 101, to add impurity.In this pecvd process, halogen or halide gas (or combination of these gases) can supplied with in reactor before the bombardment plasma.Reactor should be in the first 103 of the high k gate dielectric 101 of the following sufficiently long time modification of work of appropriate condition (for example temperature, pressure, radio frequency and power), to guarantee and can optionally remove first 103 with respect to other materials.In a preferred embodiment, use the low-power pecvd process, for example use and a kind ofly under less than about 200 watts, carry out.
In particularly preferred embodiment, in reactor, supply with hydrogen bromide (" HBr ") and chlorine (Cl with suitable flow velocity
2), will come the first 103 of the high k gate dielectric 101 of modification in the mode of expectation with the plasma that guarantees to generate by these gases.The wafer bias that (is preferably about 100 watts) between about 50 to about 100 watts can be used the sufficiently long time, the expectation of finishing first 103 changes.Continue less than about 1 minute or may just enough cause such conversion with regard to so short plasma exposure process in 5 seconds.
Though described some examples of the technology that is used for the high k dielectric layer of modification 101 firsts 103 here, for a person skilled in the art clearly, can use other processing.Therefore, the technology that is used for modification first 103 is not limited to above-described those technologies.Method of the present invention has considered to use any suitable wet method or dry chemistry, as long as it is described processing can be added impurity in high k dielectric layer 101 firsts 103, just passable to guarantee optionally to remove first 103 with respect to the second portion 104 of high k gate dielectric 101.
After the first of modification 103, with its removal.The existence of the impurity that is added makes and can optionally remove first 103 with respect to second portion 104, i.e. etching first 103 is to generate the structure of Fig. 1 d.In a preferred embodiment, by first 103 is exposed to for example contain hydracid (for example hydrobromic acid or hydrochloric acid) or phosphoric acid than in the strong acid, remove first 103.
When use contained hydracid, this acid preferably comprised HBr or the HCl of volume content between about 0.5% to about 10%---and more preferably volume content about 5%.Use the etching technics of such acid can be, and continue about 5 minutes to about 30 minutes in room temperature or near carrying out under the room temperature---can carry out longer exposure if desired certainly.When using phosphoric acid, this acid preferably comprises the H of volume content between about 75% to about 95%
3PO
4Use the etching technics of this acid preferably under about 140 ℃ to about 180 ℃, to carry out, and more preferably under about 160 ℃, carry out.When using this acid, exposing step should continue about 30 seconds to about 5 minutes---and for the thick film of 20 dusts preferably lasting about 1 minute.
Though described some examples that are used for optionally removing the technology of first 103 here, for a person skilled in the art clearly, can use other technologies with respect to second portion 104.Therefore, the technology that is used for etching first 103 is not limited to above-described those technologies.Method of the present invention considers to use any suitable processing of optionally removing the first 103 of high k gate dielectric 101 with respect to the second portion 104 of high k gate dielectric 101.
Because it is as well known to those skilled in the art generally being used to finish other steps of semiconductor device, so will no longer be described in more detail them here.Though gate electrode preferably includes polysilicon, gate electrode replacedly can be formed by the various metals that high k gate-dielectric can use therewith.In addition, gate electrode can comprise the combination of polysilicon and one or more metals or semi-metallic.
As mentioned above, anisotropically the first 103 of the high k gate dielectric 101 of modification makes adjacent structure not be subjected to the influence of this processing step, can guarantee that wet-etching technology subsequently can not etch into the substrate of below or the second portion of adjacency significantly.As a result, when using this technology to come the high k gate dielectric of etching, the substrate of below will can not suffer any influential breaking-up, and can be with gate electrode cutout or undercutting to very serious degree.
Though the foregoing description is the example of technology that can make it possible to optionally remove with respect to the second portion of described layer the first of high k gate dielectric, the invention is not restricted to these specific embodiments.Thereby the present invention has considered to be used to change the part of high k gate dielectric guarantees that dielectric layer etching will can seriously not damage the substrate of below or other processing of undercutting gate electrode so that it can be selectively removed.
Though top description has indicated some particular step and the material that can use in the method for the invention, it should be appreciated by those skilled in the art that and to make many modifications and replacement.Therefore, all this modifications, change, replacement and replenish and all should be considered to drop in the spirit and scope of the present invention that are defined by the following claims.
Claims (15)
1. method that is used for producing the semiconductor devices comprises:
On substrate, form high dielectric constant gate dielectric layer; And
Second impurity is added to the entire first portion of described high dielectric constant gate dielectric layer, wherein carry out the interpolation of described second impurity under less than 200 watts power by plasma enhanced chemical vapor deposition (" PECVD "), with the whole described first that guarantees optionally to remove described high dielectric constant gate dielectric layer with respect to the second portion of described high dielectric constant gate dielectric layer, wherein said second impurity comprises halide.
2. the method for claim 1, wherein, described high dielectric constant gate dielectric layer forms by atomic layer chemical vapor deposition, thickness at 5 dusts between 40 dusts, and it comprises the material that chooses from following group, and described group by hafnium oxide, hafnium silicon oxide, lanthana, zirconia, silica zirconium, titanium oxide, tantalum oxide, strontium titanium oxides barium, titanium oxide barium, strontium titanium oxides, yittrium oxide, aluminium oxide and the tantalum oxide scandium is plumbous forms.
3. method as claimed in claim 2 also comprises the step of optionally removing the described first of described high dielectric constant gate dielectric layer with respect to the described second portion of described high dielectric constant gate dielectric layer.
4. the method for claim 1, wherein described second impurity also comprises halogen.
5. method as claimed in claim 3, wherein, be exposed to next described first of optionally removing described high dielectric constant gate dielectric layer in the acid by described first with respect to the described second portion of described high dielectric constant gate dielectric layer with described high dielectric constant gate dielectric layer.
6. method as claimed in claim 5, wherein, described acid comprises and contains hydracid.
7. method as claimed in claim 5, wherein, described acid comprises hydrobromic acid.
8. method that is used for producing the semiconductor devices comprises:
On substrate, form high dielectric constant gate dielectric layer;
On described high dielectric constant gate dielectric layer, form gate electrode;
The described gate electrode of etching is to expose the first of described high dielectric constant gate dielectric layer;
Add second impurity by plasma enhanced chemical vapor deposition (" PECVD ") technology in the whole described first of described high dielectric constant gate dielectric layer under less than 200 watts power, wherein said second impurity comprises halogen and halid mixture; And
Be exposed to by described first and comprise the whole described first of optionally removing described high dielectric constant gate dielectric layer with respect to the second portion of described high dielectric constant gate dielectric layer in the hydrobromic acid described high dielectric constant gate dielectric layer.
9. method as claimed in claim 8, wherein, described gate electrode comprises polysilicon.
10. method as claimed in claim 8, wherein, described gate electrode is a metal gate electrode.
11. one is used in the method for making semiconductor device, comprising:
On substrate, form high dielectric constant gate dielectric layer;
On described high dielectric constant gate dielectric layer, form gate electrode based on polysilicon;
The described gate electrode based on polysilicon of etching is to expose the first of described high dielectric constant gate dielectric layer;
Add second impurity by plasma enhanced chemical vapor deposition in the entire first portion of described high dielectric constant gate dielectric layer under less than 200 watts power, wherein said second impurity comprises halide; Then,
The entire first portion of described high dielectric constant gate dielectric layer is exposed to comprises in the hydrobromic acid, to remove the entire first portion of described high dielectric constant gate dielectric layer.
12. method as claimed in claim 11, wherein said plasma enhanced chemical vapor deposition technology is carried out under less than 200 watts, and wherein said second impurity comprises halogen and halid mixture.
13. method as claimed in claim 11, wherein, described second impurity comprises the mixture of hydrogen bromide and chlorine.
14. method as claimed in claim 11, wherein, described plasma enhanced chemical vapor deposition technology was carried out less than 1 minute.
15. method as claimed in claim 11, wherein, the described first of described high dielectric constant gate dielectric layer is exposed in the described acid 5 minutes to 30 minutes under about room temperature.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/652,546 US7037845B2 (en) | 2003-08-28 | 2003-08-28 | Selective etch process for making a semiconductor device having a high-k gate dielectric |
| US10/652,546 | 2003-08-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591786A CN1591786A (en) | 2005-03-09 |
| CN1591786B true CN1591786B (en) | 2010-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2004100570938A Expired - Fee Related CN1591786B (en) | 2003-08-28 | 2004-08-30 | A selective etch process for making a semiconductor device having a high-K gate dielectric |
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| Country | Link |
|---|---|
| US (1) | US7037845B2 (en) |
| EP (1) | EP1511073A1 (en) |
| KR (1) | KR100716689B1 (en) |
| CN (1) | CN1591786B (en) |
| TW (1) | TWI239563B (en) |
| WO (1) | WO2005024929A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7037863B2 (en) * | 2002-09-10 | 2006-05-02 | Samsung Electronics Co., Ltd. | Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices |
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| EP1511073A1 (en) | 2005-03-02 |
| US20050048791A1 (en) | 2005-03-03 |
| WO2005024929A1 (en) | 2005-03-17 |
| CN1591786A (en) | 2005-03-09 |
| TWI239563B (en) | 2005-09-11 |
| KR100716689B1 (en) | 2007-05-09 |
| KR20050021943A (en) | 2005-03-07 |
| TW200509244A (en) | 2005-03-01 |
| US7037845B2 (en) | 2006-05-02 |
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