CN1589018A - Control device and method for video frequency decoding buffer zone - Google Patents
Control device and method for video frequency decoding buffer zone Download PDFInfo
- Publication number
- CN1589018A CN1589018A CN 200410070028 CN200410070028A CN1589018A CN 1589018 A CN1589018 A CN 1589018A CN 200410070028 CN200410070028 CN 200410070028 CN 200410070028 A CN200410070028 A CN 200410070028A CN 1589018 A CN1589018 A CN 1589018A
- Authority
- CN
- China
- Prior art keywords
- image
- control module
- address
- buffering area
- decoding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 42
- 230000003139 buffering effect Effects 0.000 claims description 122
- 230000008569 process Effects 0.000 claims description 14
- 230000000694 effects Effects 0.000 claims description 6
- 230000008030 elimination Effects 0.000 claims description 5
- 238000003379 elimination reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 230000008520 organization Effects 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000007726 management method Methods 0.000 description 7
- 241001269238 Data Species 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical group CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
This invention discloses a video decode buffer zone control device and a device. The device includes a buffer zone control module, a reference image got control module, a decode image storage control module, a display image got control module and a display control module, among which, the buffer zone control module is used in computing and getting current decode image storage address, current reference image address and display image address to be delivered to the reference image acquire and control module, a decode image storage control module and a display image acquire control module to realize associated management to decode image, reference image and display image without using large RAM space.
Description
Technical field
The present invention relates to digital image processing techniques and SOC technology, particularly relate to the encoding and decoding technique of digital picture, more particularly, relate to the method and the device of a kind of video decode display buffer control.
Background technology
At present, popular video encoding and decoding standard nearly all adopts a kind of hybrid coding/decoding process, for example MPEG-1, MPEG-2, MPEG-4, H.26x reach the AVS standard that China is releasing.This coding/decoding structure has adopted the motion prediction in time and space to mend to taste, conversion, quantification and entropy (variable-length encoding) coding/decoding method, and their majorities all comprise following three kinds of image encoding patterns:
1, intraframe coding (I image/I frame): only use image self-information coding, not with reference to other picture decodings;
2, forward predictive coded (P image/P frame): the P image is predicted one or more I images or P image forward, and therefore if certain of front does not exist with reference to I image or P image, then this image just can not be decoded;
3, bi-directional predictive coding (B image/B frame): it can predict simultaneously a frame or multiframe decoded I image or P image forward and backward.So when decoding B image, the I image or the P view data that need decoding earlier to obtain being positioned on DISPLAY ORDER thereafter can be decoded, thereby cause the inconsistent of decoding order and DISPLAY ORDER.
Because the existence of B image is arranged, therefore when decoding, need be to the decoded picture exportable demonstration in rear of reordering, current, most solutions are that two buffering areas are set in decoder, and one is used for the buffer memory decoded picture, and provide reference picture for motion compensation; Another is used for the decoded picture of buffer memory after reordering according to DISPLAY ORDER.
Typical decode structures as shown in Figure 1.After the video code flow process entropy decoding of input, inverse quantization, the inverse transformation, if according to the coding that intra-frame encoding mode carries out, then need to carry out the infra-frame prediction compensation deals, otherwise carry out motion compensation, after the decoded data of gained carries out block-eliminating effect filtering, store in the decoding image buffering area.If current decoded picture is the B image, then directly duplicates current decoded picture and in the display buffer, show, if otherwise I or P frame then duplicate the I of previous decoding or P frame data in the display buffer.But, this mode need be duplicated a large amount of RAM data, promptly need the decoded data of every frame is copied to the display buffer from decoding buffer zone, and both needed to open up enough big buffering area for decoded picture, also need to open up enough big buffering area for display image, these all will bring high cost to decoding chip.
Because the data in decoding image buffering area and the display buffer are repetitions, therefore can consider unified management is carried out in their merging, but this moment, their management just became very complicated.Can not be before for example the decoded picture of certain in decoding image buffering area is not shown with its covering; Some standard, as H.264 (JVT) and AVS have adopted the multiframe reference policy, promptly P frame or B frame can be with reference to a plurality of images, even if certain decoded picture was copied to the display buffer and showed this moment, but because it also needs it can not be capped as the reference picture of other images.
Summary of the invention
Technical problem to be solved by this invention is, at the deficiencies in the prior art, the control device of a kind of video decode display buffer is proposed, this device passes through the coordinated management of the buffering area realization of low capacity to decoded picture, reference picture and display image, coordinate decoding, the demonstration of control of video, reduce the cost of decoding chip.
Another technical problem to be solved by this invention is, at the deficiencies in the prior art, a kind of control method of video frequency decoding buffer zone is proposed, realize that by the buffering area of a low capacity storage of decode image data, demonstration reach to the core codec module provides reference picture, need not duplicate a large amount of RAM data.
The present invention realizes by the following technical solutions:
A kind of video frequency decoding buffer zone control device, comprise that buffering area control module, reference picture obtain control module, decoded picture storage control module, display image and obtain control module, display control module, wherein, described buffering area control module is used for calculate obtaining current decoded picture memory address, current reference picture address, display image address, and with above address respectively correspondence send to reference picture and obtain control module, decoded picture storage control module, display image and obtain control module;
Described reference picture obtains the address that control module is sent according to the buffering area control module, obtains reference picture from decoding image buffering area, and sends to the motion compensating module in the decoding nucleus module, decodes;
The address that described decoded picture storage control module is sent according to the buffering area control module will be left in this address from the current decoded data of decoding nucleus module output;
Described display image obtains the address that control module is sent according to the buffering area control module, obtains display image from decoding image buffering area, and sends it to display control module;
The display image that described display control module control receives shows that on display the address with display image writes display status register simultaneously.
Device of the present invention can pass through the coordinated management of the buffering area realization of low capacity to decoded picture, reference picture and display image, coordinate decoding, the demonstration of control of video, do not need to duplicate lot of data, the buffer pool size that can meet the demands is little, has reduced the cost of decoding chip.
The present invention also proposes a kind of control method of video frequency decoding buffer zone, comprises following step:
Step 4, buffering area control module send to the decoded picture storage control module with the memory address of current decoded picture; The decoded picture storage control module will deposit decoding image buffering area in from the decoded data of decoding nucleus module output according to this memory address;
Method of the present invention only just can realize coordinated management to decoded picture, reference picture and display image with a very little buffering area of capacity, coordinates decoding, the demonstration of control of video, can make decoding speed and display speed synchronous,
Description of drawings
Fig. 1 is the structural representation of typical decoder module;
Fig. 2 is the operation principle schematic diagram of device of the present invention;
Fig. 3 is the flow chart of the method for the invention.
Embodiment
Below the present invention will be described in detail by accompanying drawing and specific embodiment.
Referring to Fig. 2, be the operation principle schematic diagram of device of the present invention.
As we know from the figure, this device comprises that buffering area control module 1, reference picture obtain control module 2, decoded picture storage control module 3, display image and obtain control module 4, display control module 5, the control of this device is stored in the decoding image buffering area 9 from the decoded data of decoding nucleus module 8 outputs, and takes out display images from decoding image buffering area 9 and deliver to the display 6 and show.
Wherein, the control core that described buffering area control module 1 is whole buffering area, calculate to obtain the address of the reference picture that current decoded picture need use, and send to reference picture and obtain control module 2, so that obtain reference data for the decoding present image;
Calculate the memory address that obtains current decoded picture, and send to the control that decoded picture storage control module 3 is carried out the decoded data storage;
Calculate the decoded picture address that next image need show, and send to display image and obtain control module 4, display image obtains control module 4 and sends display control module 5 to by this address acquisition video data again, these display control module 5 these video datas of control show on display 6, display control module 5 is stored in the address of current display image in the current display status register 7 simultaneously, whether buffering area control module 1 has been shown the decoding that determines whether continuing this image by the data that are stored in the current explicit address judgement memory address as calculated in the current display status register, if be shown, then continue decoding, otherwise wait for, till this address is shown.The concrete determination strategy whether conflict the address is as follows:
Also comprise a display image address emulation FIFO in the buffering area control module 1 of device of the present invention, described display image address emulation FIFO is used for that the memory buffer control module sends to that display image obtains control module but the display image address that also is not shown, buffering area control module 1 is every to explicit address of display control module transmission, just writes this address in this buffering area; And after calculating acquisition memory image address, the buffering area control module will be obtained the current explicit address in the current display status register, remove all explicit addresses that are positioned among the display image address emulation FIFO before this explicit address, because the image before this explicit address is shown;
The decoded picture memory address that search is calculated in the explicit address that is left in display image address emulation FIFO, if there is equal address to occur, the image that this address then is described also is not shown (mainly due to decoding speed greater than display speed), if the address that does not have to equate occurs, illustrate that the image of this address shows.
Described reference picture obtains reference picture address that control module 2 sends over according to buffering area control module 1 and obtains from decoding image buffering area (RAM) when reference image data sends in the decoding nucleus module 8 for motion compensation and use;
The memory address that decoded picture storage control module 3 sends over according to buffering area control module 1 is to decoding image buffering area 9 storage decoded datas;
Display image obtains display image address that control module 4 sends over according to buffering area control module 1 and obtains display image data offer display control module 5 from decoding image buffering area 9, is shown on display 6 by display control module 5 these video datas of control;
The display image data that display control module 5 controls are obtained normally shows on display 6, and feeds back current display image address information by current display status register to the buffering area control module.When display image obtains control module not to display control module transmission address information, display control module will be controlled the data that repeat to show last display image.
Decoded picture storage control module 3 will judge whether that at the decoded data that will export decoded data can store before decoding image buffering area 9 storage from the core codec chip, whether there is decoded data to store in order to judge, multiple mode can be arranged, as:
The decoded picture storage control module can comprise a decoded data FIFO, described decoded data FIFO is used for the current decoded data of buffer memory from the output of decoding nucleus module, when having judged whether that decoded data can be stored, have only whether this decoded data of retrieval FIFO is empty getting final product; Perhaps described decoded picture storage control module is connected with the block elimination effect filter of decoding nucleus module, receives the signal that whether has decoded data to export that block elimination effect filter sends, and can judge whether that according to this signal decoded data can store.
The present invention also provides a kind of control method of video frequency decoding buffer zone, as shown in Figure 3, comprises following step:
Step 4, buffering area control module send to the decoded picture storage control module with the memory address of current decoded picture; The decoded picture storage control module will deposit decoding image buffering area in from the decoded data of decoding nucleus module output according to this memory address;
Wherein, the decoded picture storage control module judges whether to still have decoded data from the output of decoding nucleus module, if any, continue storage, behind the two field picture of having decoded, return step 1, as do not have, then the decoded picture storage control module enters idle condition, waits for gathering data arrival next time.
The used buffer pool size of the present invention is determined by following formula:
S＝(RefNum+φ)×PictureSize
Wherein RefNum is the maximum reference picture number of standard code, for example is 2 in the AVS standard; φ is weights, decides according to concrete flowing water project organization, stores the recycling space of current decoded picture except being used for the space of stored reference image in its expression buffering area.For example in the AVS standard,, then except the space of 2 reference pictures, also have the space of 2 images can offer decoded picture storage control module and display control module use if buffer size is 4.For the AVS standard, its reference picture number is 2, and these two positions must keep so that other image comes reference.And storage and demonstration need a memory space at least, if having only a space, mutual wait can occur when decoding processing, and promptly the decoded picture of this position does not also show, and must deposit the decoded data of back toward this buffer location in.Decoder stopped and wait to show end this moment, carried out the decoding processing of next image again, thereby influenced overall performance.And adopt 4 buffering areas, then can address this problem preferably.Be generally 2 and can carry out normal continuous productive process;
PictureSize is the size of decoded picture.
Above-mentioned reference picture address, the memory address of decoded picture, the display image address obtains by following formula:
Addr＝Base+Pos×PictureSize，
Wherein, refer to the Position Number of this address at DPB (Decoded Picture Buffer, decoding image buffering area are called for short DPB) buffering area during the value of Pos, Base is meant DPB buffering area plot.
Pos value in the described reference picture address obtains by following process:
State information according to image in the current DPB buffering area, for the AVS standard, analyze the state information of 4 images in the current DPB buffering area, the position (0～3) of non-B image (being I or P image) of selecting wherein to have maximum image number is as the Pos value in the reference picture address, for the AVS standard, the position (0～3) of two non-B images (being I or P image) of selecting wherein to have maximum image number is as the Pos value in the reference picture address.
Pos value in the memory address of described decoded picture obtains by following process:
If the non-B image more than the reference picture number is arranged in the current DPB buffering area, the value of non-B picture position of getting the picture number minimum is as the Pos value in the memory address of decoded picture, for the AVS standard, because must have 2 to be reference picture in 4 buffering areas of DPB, they are right and wrong B image all, and other 2 can be the image of combination in any.If a right and wrong B image is arranged in other 2, that is to say, current DPB buffering area has 3 non-B images, at this moment, the minimum non-B image of numbering has not used meaning, this space can reuse, and the value of position that just will number minimum non-B image is as the Pos value in the memory address of decoded picture;
If it is the B image that other images except that the number of reference picture are arranged in the DPB buffering area, the value of then choosing the position of picture number minimum in the B image is as the Pos value in the memory address of decoded picture.For the AVS standard, if other 2 except that the non-B image of 2 reference pictures is the B image, because the B image is showing before reference picture thereafter all the time, as long as preserving, decoding finishes, the B image can show as early as possible that this is that DISPLAY ORDER is desired, and one of them B image has shown and finishes so, this image that showed has not just had the meaning of preservation yet so, and this space can be reused.So, with the value of the position of picture number minimum in the B image as the Pos value in the memory address of decoded picture.
The Pos value of described display image address obtains by following process:
Search for the image state of current DPB buffering area, find current non-B image and the B picture position that is not shown respectively with minimum image number.If all B images all show in the DPB buffering area, the value of position of non-B image of then getting lowest number is as the Pos value in the display image address; If B image and non-B image all have also not demonstration, if this moment lowest number the forward direction reference picture of the non-B image B image that is lowest number, the positional value of then getting non-B image is as the Pos value in the memory address, if the forward direction reference picture of the B image that the non-B image of lowest number is not a lowest number, the value of position of then getting the B image is as the Pos value in the memory address.
The described buffering area control module of step 2 judges that the process whether image of described decoded picture memory address correspondence has been shown is: the address of the current display image of depositing in the buffering area control module reading displayed status register, remove and be positioned at this explicit address all explicit addresses before among the display image address emulation FIFO, because the image before this explicit address is shown, the decoded picture memory address that search is calculated in the remaining explicit address of display image address emulation FIFO, if find to have equal address to occur, illustrate that then the image in this decoded picture memory address does not also show, if the address that does not have to equate occurs, illustrate that the image in this decoded picture memory address shows.
With AVS Video 1.0 coding standards is that example describes, in AVS 1.0 standards, the number that the reference picture number is B image between 2, two non-B images to the maximum can only be 0,1 and 2 three kind of numerical value, below by having the code stream order of 2 B images to describe between two non-B images for embodiment.
A typical decoder input order is as follows:
I
0?P
1B
2B
3?P
4B
5B
6?P
7B
8B
9?P
10B
11B
12?P
13B
14B
15?P
16B
17B
18?P
19
Corresponding demonstration output order is as follows:
I
0?B
2B
3P
1?B
5B
6P
4?B
8B
9P
7?B
11B
12P
10?B
14B
15P
13?B
17B
18P
16
The process of buffer management is by shown in the following table:
| ?????????????????????????????????DPB | ????Store | ??????????????MC | ????Display | |||||||||
| ????Cur | ????0 | ????1 | ????2 | ????3 | ????S 0 | ????N 0 | ????N 1 | ????ref 0 | ????ref 1 | ????D 0 | ||
| ????I 0 | ????I 0????[0] | ????0 | ????I 0 | ????N | ????N | ????N | ||||||
| ????P 1 | ????I 0????[0] | ????P 1????[0] | ????1 | ????P 1 | ????0 | ????N | ????I 0 | |||||
| ????B 2 | ????I 0????[1] | ????P 1????[0] | ????B 2????[0] | ????2 | ????B 2 | ????0 | ????1 | ????I 0 | ????P 1 | ????0 | ????I 0 | |
| ????B 3 | ????I 0????[1] | ????P 1????[0] | ????B 2????[0] | ????B 3????[0] | ????3 | ????B 3 | ????0 | ????1 | ????I 0 | ????P 1 | ????2 | ????B 2 |
| ????P 4 | ????I 0????[1] | ????P 1????[0] | ????P 4????[0] | ????B 3????[0] | ????2 | ????P 4 | ????0 | ????1 | ????I 0 | ????P 1 | ????3 | ????B 3 |
| ????B 5 | ????B 5????[0] | ????P 1????[0] | ????P 4????[0] | ????B 3????[1] | ????0 | ????B 5 | ????1 | ????2 | ????P 1 | ????P 4 | ????1 | ????P 1 |
| ????B 6 | ????B 5????[0] | ????P 1????[1] | ????P 4????[0] | ????B 6????[0] | ????3 | ????B 6 | ????1 | ????2 | ????P 1 | ????P 4 | ????0 | ????B 5 |
| ????P 7 | ????P 7????[0] | ????P 1????[1] | ????P 4????[0] | ????B 6????[0] | ????0 | ????P 7 | ????1 | ????2 | ????P 1 | ????P 4 | ????3 | ????B 6 |
| ????B 8 | ????P 7????[0] | ????B 8????[0] | ????P 4????[0] | ????B 6????[1] | ????1 | ????B 8 | ????2 | ????0 | ????P 4 | ????P 7 | ????2 | ????P 4 |
| ????B 9 | ????P 7????[0] | ????B 8????[0] | ????P 4????[1] | ????B 9????[0] | ????3 | ????B 9 | ????2 | ????0 | ????P 4 | ????P 7 | ????1 | ????B 8 |
| ????P 10 | ????P 7????[0] | ????P 10???[0] | ????P 4????[1] | ????B 9????[0] | ????1 | ????P 10 | ????2 | ????0 | ????P 4 | ????P 7 | ????3 | ????B 9 |
| ????B 11 | ????P 7????[0] | ????P 10???[0] | ????B 11???[0] | ????B 9????[1] | ????2 | ????B 11 | ????0 | ????1 | ????P 7 | ????P 10 | ????0 | ????P 7 |
| ????B 12 | ????P 7????[1] | ????P 10???[0] | ????B 11???[0] | ????B 12???[0] | ????3 | ????B 12 | ????0 | ????1 | ????P 7 | ????P 10 | ????2 | ????B 11 |
| ????P 13 | ????P 7????[1] | ????P 10???[0] | ????P 13???[0] | ????B 12???[0] | ????2 | ????P 13 | ????0 | ????1 | ????P 7 | ????P 10 | ????3 | ????B 12 |
| ????B 14 | ????B 14???[0] | ????P 10???[0] | ????P 13???[0] | ????B 12???[1] | ????0 | ????B 14 | ????1 | ????2 | ????P 10 | ????P 13 | ????1 | ????P 10 |
| ????B 15 | ????B 14???[0] | ????P 10???[1] | ????P 13???[0] | ????B 15???[0] | ????3 | ????B 15 | ????1 | ????2 | ????P 10 | ????P 13 | ????0 | ????B 14 |
| ????P 16 | ????P 16???[0] | ????P 10???[1] | ????P 13???[0] | ????B 15???[0] | ????0 | ????P 16 | ????1 | ????2 | ????P 10 | ????P 13 | ????3 | ????B 15 |
| ????B 17 | ????P 16???[0] | ????B 17???[0] | ????P 13???[0] | ????B 15???[1] | ????1 | ????B 17 | ????2 | ????0 | ????P 13 | ????P 16 | ????2 | ????P 13 |
| ????B 18 | ????P 16???[0] | ????B 17???[0] | ????P 13???[1] | ????B 18???[0] | ????3 | ????B 18 | ????2 | ????0 | ????P 13 | ????P 16 | ????1 | ????B 17 |
| ????P 19 | ????P 16???[0] | ????P 19???[0] | ????P 13???[1] | ????B 18???[0] | ????1 | ????P 19 | ????2 | ????0 | ????P 13 | ????P 16 | ????3 | ????B 18 |
| ????0 | ????P 16 | |||||||||||
It is as follows to show every meaning interpretation, in conjunction with a behavior example.
| ??????????????????????DPB | Store | ????MC | ?Display | |||||||||
| ??Cur | ??0 | 1 | 2 | 3 | S 0 | ?N 0 | ?N 1 | ?ref 0 | ?ref 1 | ?D 0 | ||
| ??P 10 | ??P 7??[0] | P 10??[0] | P 4????[1] | B 9????[0] | 1 | ??P 10 | ?2 | ?0 | ?P 4 | ?P 7 | ?3 | ?B 9 |
| ??B 11 | ??P 7??[0] | P 10??[0] | B 11???[0] | B 9????[1] | 2 | ??B 11 | ?0 | ?1 | ?P 7 | ?P 10 | ?0 | ?P 7 |
| ??P 7??[1] | P 10??[0] | B 11???[0] | ?2 | ?B 11 | ||||||||
Cur represents the image of current decoder input, as B
11, i.e. the 11st image, its type is the B image.0,1,2 and 3 of DPB represents 4 memory locations of buffering area respectively, as P
7P
10B
11B
9, i.e. 4 images of current storage are divided into two P images and two B images, and its picture number is divided into 7,10,11 and 9.B wherein
11It is the image that has just deposited in.Store represents the position of storing and corresponding image, and it is as shown in the table will import B
11Deposit 2 positions in.MC represents the position of reference picture, as above B
11Reference picture be P
7And P
10, the memory location of their correspondences is 0 and 1.Display represents the B with display position 2
11Image.[] of each postpone represents whether this Pos place image shows, 1 expression shows that 0 expression does not show.The demonstration here represents it is the address have been sent into image address emulation FIFO, and whether image really is shown the explicit address register information that need check that image display is returned.
The control method process of video frequency decoding buffer zone is as follows:
P
4Show that other 3 images all do not send apparent.
B
9Front and back be respectively that forward direction is P to reference picture
4, the back is to being P
7
According to the address that formula calculates reference picture address, decoded picture address stored, display image, wherein, described formula is:
Addr＝Base+Pos×PictureSize，
Base in the formula is meant DPB buffering area plot, refers to its Position Number at the DPB buffering area during value of Pos;
Wherein, determine the position of reference picture: choose two P images, i.e. P with maximum image number
7And P
10Be current decoded picture B
11Reference picture, its position is 0 and 1, obtains the address of reference picture according to the value of this position;
Determine the position of decoded picture storage: because this moment 3 P images are arranged, so should be deposited into the picture position of minimum image number, i.e. P
4So position 2 is can be with B
11Write the position 2 of DPB.Value according to this position obtains the decoded picture address stored;
Determine the position of display image: find two not show non-B image and B image, i.e. P respectively with minimum image number
10And B
11, because P
10Be B
11Back to reference picture, so this moment should show B
11Be B
11Decoding finishes and can notify display module to begin to show this image, obtains the address of display image according to the value of this position;
The address of the current display image of depositing in step 3, the buffering area controller reading displayed status register, remove and be positioned at this explicit address all explicit addresses before among the display image address emulation FIFO, because the image before this explicit address is shown, the decoded picture memory address that search is calculated in the explicit address that is left in emulation FIFO is because P
4The address not in display image address emulation FIFO, so image P in this decoded picture memory address is described
4Show.
Step 4, buffering area control module send to the decoded picture storage control module with the memory address of current decoded picture; The decoded picture storage control module judges whether to still have decoded data from the output of decoding nucleus module, as does not have, and then the decoded picture storage control module enters idle condition, waits for gathering data arrival next time; If any, according to this memory address, will deposit original P the decoding image buffering area in from the current decoded data of decoding nucleus module output
4The position, in the present embodiment because current decoded data B arranged
11So, with B
11Deposit original P in the decoding image buffering area in
4The position, this moment buffering area become P
7P
10B
11B
9
At this moment, current decoded data B
11Decoding, show and to finish dealing with, next repeat above-mentioned steps and handle next view data.
When implementation strategy is managed, can adopt a simple structure to realize the statistics of corresponding informance.
typedef?struct
{
int?pictype；
int?number；
int?disped；
int?motion[2]；
}DPBMap_T；
DPBMap_T??g_arrDPBMap[4]；
Used corresponding with last surface analysis to information, write down every data of 4 positions of DPB respectively by the g_arrDPBMap array, comprise pictype presentation video type, number presentation video numbering, disped represents whether show, motion writes down two reference picture positions of present image respectively.By safeguarding this structural array, just can obtain all required analysis of strategies information.
Adopt corresponding strategy can guarantee in the scope of 4 buffering areas, effectively manage each image storage.This strategy not only is suitable for the IPBB sequence, for the IPPP sequence, and the IPB sequence, perhaps the IPBBPBPBBPBP sequence all can be suitable for.Because management strategy is to determine from the relation between the image, it doesn't matter order to occur with concrete image type.
It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (19)
1, a kind of video frequency decoding buffer zone control device, it is characterized in that, comprise that buffering area control module, reference picture obtain control module, decoded picture storage control module, display image and obtain control module, display control module, wherein, described buffering area control module is used for calculate obtaining current decoded picture memory address, current reference picture address, display image address, and with above address respectively correspondence send to reference picture and obtain control module, decoded picture storage control module, display image and obtain control module;
Described reference picture obtains the address that control module is sent according to the buffering area control module, obtains reference picture from decoding image buffering area, and sends to the motion compensating module in the decoding nucleus module, is used for decoding;
The address that described decoded picture storage control module is sent according to the buffering area control module will be left in this address of decoding image buffering area from the current decoded data of decoding nucleus module output;
Described display image obtains the address that control module is sent according to the buffering area control module, obtains display image from decoding image buffering area, and sends it to display control module;
The display image that described display control module control receives shows that on display the address with display image writes display status register simultaneously.
2, video frequency decoding buffer zone control device according to claim 1, it is characterized in that, described buffering area control module also comprises a display image address emulation FIFO, and described display image address emulation FIFO is used for the memory buffer control module and sends to display image and obtain control module but also do not have the real display image address that shows.
3, video frequency decoding buffer zone control device according to claim 1, it is characterized in that, described decoded picture storage control module comprises a decoded data FIFO, and described decoded data FIFO is used for the current decoded data of buffer memory from the output of decoding nucleus module.
4, video frequency decoding buffer zone control device according to claim 1, it is characterized in that, described decoded picture storage control module is connected with the block elimination effect filter of decoding nucleus module, receives the signal whether decoded data output is arranged that block elimination effect filter sends.
5, a kind of control method of video frequency decoding buffer zone is characterized in that, comprises following step:
Step 1, buffering area control module obtain current decoded picture memory address, current reference picture address, display image address according to the view data of current decoding image buffering area and the state of this view data;
Step 2, buffering area control module send to reference picture with described current reference picture address and obtain control module, described reference picture obtains control module and obtains reference image data according to the reference picture address that the buffering area control module sends over from decoding image buffering area, and send it to the motion compensating module of decoding in the nucleus module, be used for decoding;
Step 3, buffering area control module judge whether the image of described decoded picture memory address correspondence is shown, if be not shown, whether the image that then continues detection decoded picture memory address correspondence is shown, if show, carries out next step;
Step 4, buffering area control module send to the decoded picture storage control module with the memory address of current decoded picture; The decoded picture storage control module will deposit decoding image buffering area in from the decoded data of decoding nucleus module output according to this memory address;
Step 5, buffering area control module send to display image with the display image address and obtain control module, and simultaneously described display image address are write display image address emulation fifo buffer; Display image obtains control module according to described display image address reading displayed view data and send it to display control module from decoding image buffering area;
Step 6, display control module receive and control described display image data and show on display, and display control module writes display status register with the initial address of this video data simultaneously.
6, video frequency decoding buffer zone control method according to claim 5 is characterized in that, the capacity of the decoding image buffering area in the described step 1 is determined by following formula:
S＝(RefNum+φ)×PictureSize
Wherein, S represents the capacity of decoding image buffering area, and RefNum is the maximum reference picture number of the standard code of using during to picture decoding; φ is weights, decides according to concrete flowing water project organization; PictureSize is the size of decoded picture.
7, video frequency decoding buffer zone control method according to claim 6 is characterized in that, described RefNum is that the maximum reference picture stipulated in the AVS standard is several 2, and φ is 2.
According to claim 5 or 6 described video frequency decoding buffer zone control methods, it is characterized in that 8, the current decoded picture memory address of acquisition, current reference picture address, display image address obtain by following formula in the described step 1:
Addr＝Base+Pos×PictureSize，
Wherein, Base is a DPB buffering area plot; The value of Pos is the Position Number of this address at decoding image buffering area.
9, video frequency decoding buffer zone control method according to claim 8, it is characterized in that, the acquisition process of the pos value in the current reference picture address is: according to the reference picture number in the decoding standard, begin to choose in turn the position of non-B image of reference picture number as the Pos value the reference picture address from the picture number of the non-B image of maximum in the DPB buffering area.
10, video frequency decoding buffer zone control method according to claim 9 is characterized in that, described standard is the AVS standard, and described reference picture number is 2.
11, video frequency decoding buffer zone control method according to claim 8 is characterized in that, the process that the pos value in the described current decoded picture memory address is obtained is:
If judge that the image except that reference picture has a non-B image in the current DPB buffering area, the value of non-B picture position of getting the picture number minimum is as the Pos value in the memory address of decoded picture; If other images in the DPB buffering area except that reference picture are the B image, the value of then choosing the position of picture number minimum in the B image is as the Pos value in the memory address of decoded picture.
12, video frequency decoding buffer zone control method according to claim 10, it is characterized in that, the process that pos value in the described current decoded picture memory address is obtained is: judge whether the non-B image number in the current DPB buffering area is 3, if 3, the value of non-B picture position of getting the picture number minimum is as the Pos value in the memory address of decoded picture; If not 3, be 2, in addition 2 is the B image, the value of getting the position of picture number minimum in the B image is as the Pos value in the memory address of decoded picture.
13, video frequency decoding buffer zone control method according to claim 8 is characterized in that, the process that the pos value in the described display image address is obtained is:
Search for current DPB buffer status information, from state information, find out current non-B image and the B picture position that does not show with minimum image number, if all B images all show in the DPB buffering area, the value of position of non-B image of then getting lowest number is as the Pos value in the display image address; If also having B image and non-B image all to have does not also show, if the forward direction reference picture of the B image that the non-B image of lowest number is a lowest number, the value of position of then getting non-B image is as the Pos value in the memory address, if the forward direction reference picture of the B image that the non-B image of lowest number is not a lowest number, the value of position of then getting the B image is as the Pos value in the memory address.
14, video frequency decoding buffer zone control method according to claim 1, it is characterized in that, described method also comprises: the address of the current display image of depositing in the buffering area control module reading displayed status register, remove all display image addresses that are arranged among the display image address emulation FIFO before the current display image address that display status register deposits.
15, video frequency decoding buffer zone control method according to claim 14, it is characterized in that, the buffering area control module judges that the process whether image of described decoded picture memory address correspondence has been shown is in the described step 3: whether the explicit address among the buffering area control module search display image address emulation FIFO has the address that equates with the decoded picture memory address of calculating, if have, illustrate that then the image in this decoded picture memory address does not also show, if no, illustrate that the image in this decoded picture memory address shows.
16, video frequency decoding buffer zone control method according to claim 1, it is characterized in that, the decoded picture storage control module will deposit in from the decoded data of decoding nucleus module output before the decoding image buffering area according to described memory address in the described step 4, at first judge whether to deposit in the decoded data in the decoding image buffering area, if have, then this decoded data is deposited in the decoding image buffering area according to described memory address, if do not have, then the decoded picture storage control module enters idle condition, waits for that next decoded data is from the output of decoding nucleus module.
17, video frequency decoding buffer zone control method according to claim 16, it is characterized in that, described decoded picture storage control module will deposit its inner decoded data FIFO in from the decoded data of decoding nucleus module output, whether the decoded picture storage control module is empty according to described decoded data FIFO, judge whether to deposit in the decoded data in the decoding image buffering area, if have, then this decoded data is deposited in the decoding image buffering area according to described memory address, if do not have, then the decoded picture storage control module enters idle condition, waits for that next decoded data is from the output of decoding nucleus module.
18, video frequency decoding buffer zone control method according to claim 16, it is characterized in that, described decoded picture storage control module receives the signal whether decoded data output is arranged that the block elimination effect filter in the decoding nucleus module sends, and judges whether to deposit in decoded data in the decoding image buffering area according to this signal.
19, video frequency decoding buffer zone control method according to claim 1, it is characterized in that, if do not receive that display image obtains the display image data that control module sends over after display control module is presented at display with display image data, control described display image data and repeat on display, to show in the described step 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410070028 CN1271864C (en) | 2004-08-05 | 2004-08-05 | Control device and method for video frequency decoding buffer zone |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410070028 CN1271864C (en) | 2004-08-05 | 2004-08-05 | Control device and method for video frequency decoding buffer zone |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1589018A true CN1589018A (en) | 2005-03-02 |
| CN1271864C CN1271864C (en) | 2006-08-23 |
Family
ID=34604395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410070028 Active CN1271864C (en) | 2004-08-05 | 2004-08-05 | Control device and method for video frequency decoding buffer zone |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1271864C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101523920B (en) * | 2006-10-16 | 2013-12-04 | 汤姆森许可贸易公司 | Method for using a network abstract layer unit to signal an instantaneous decoding refresh during a video operation |
| CN105120286A (en) * | 2015-06-26 | 2015-12-02 | 福州瑞芯微电子股份有限公司 | High-efficiency video decoding reference frame access method and device |
| CN106713927A (en) * | 2016-11-14 | 2017-05-24 | 珠海格力电器股份有限公司 | Image output device and method, and decoder |
-
2004
- 2004-08-05 CN CN 200410070028 patent/CN1271864C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101523920B (en) * | 2006-10-16 | 2013-12-04 | 汤姆森许可贸易公司 | Method for using a network abstract layer unit to signal an instantaneous decoding refresh during a video operation |
| CN105120286A (en) * | 2015-06-26 | 2015-12-02 | 福州瑞芯微电子股份有限公司 | High-efficiency video decoding reference frame access method and device |
| CN106713927A (en) * | 2016-11-14 | 2017-05-24 | 珠海格力电器股份有限公司 | Image output device and method, and decoder |
| CN106713927B (en) * | 2016-11-14 | 2019-08-13 | 珠海格力电器股份有限公司 | A kind of image output device, method and decoder |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1271864C (en) | 2006-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1658675A (en) | Method for reading search window data for motion estimation by hardware | |
| US20080025412A1 (en) | Method and apparatus for processing video stream | |
| CN1794814A (en) | Pipelined deblocking filter | |
| CN1812576A (en) | Deblocking filters for performing horizontal and vertical filtering of video data simultaneously and methods of operating the same | |
| CN1574943A (en) | Apparatus and method for controlling reverse-play for digital video bitstream | |
| CN1595994A (en) | Method and device for sharing dynamic video compression buffer | |
| CN1589028A (en) | Predicting device and method based on pixel flowing frame | |
| CN1306826C (en) | Loop filter based on multistage parallel pipeline mode | |
| CN1214648C (en) | Method and apparatus for performing motion compensation in a texture mapping engine | |
| CN1852442A (en) | Layering motion estimation method and super farge scale integrated circuit | |
| CN1266942C (en) | Image processor | |
| CN1703094A (en) | Image interpolation apparatus and methods that apply quarter pel interpolation to selected half pel interpolation results | |
| CN1306824C (en) | Image boundarg pixel extending system and its realizing method | |
| CN1271864C (en) | Control device and method for video frequency decoding buffer zone | |
| CN1268136C (en) | Frame field adaptive coding method based on image slice structure | |
| CN1874512A (en) | High performance pipeline system in use for AVS video decoder | |
| CN1286323C (en) | Control device and its method for moving vector access in frame field video decoding | |
| Liu et al. | An 865-μW H. 264/AVC video decoder for mobile applications | |
| CN1925616A (en) | Macro block pair class frame field adaptive coding/decoding method | |
| CN1117484C (en) | Process for decoding and coding compressed video data stream with reduced memory requirements | |
| CN1306819C (en) | Video frequency decoding control method and device | |
| CN1449197A (en) | B image mode determining method and apparatus of video coding system | |
| CN1306821C (en) | Method and its device for forming moving vector prediction in video image | |
| CN1905675A (en) | Method for programmable entropy decoding based on shared storage and countra-quantization | |
| CN1780402A (en) | Video image motion compensator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ZHANXUN COMMUNICATIONS (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: UNITED XINYUAN DIGITAL AUDIO-VIDEO TECHNOLOGY (BEIJING) CO., LTD. Effective date: 20070615 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20070615 Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 100080 North building, room 6, 140 South Road, Haidian District Academy of Sciences, Beijing Patentee before: UNITED XINYUAN DIGITAL AUDIO V |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190315 Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd. Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20050302 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd. Contract record no.: X2021110000008 Denomination of invention: Video decoding buffer control device and method Granted publication date: 20060823 License type: Exclusive License Record date: 20210317 |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221018 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd. |