CN1306826C - Loop filter based on multistage parallel pipeline mode - Google Patents
Loop filter based on multistage parallel pipeline mode Download PDFInfo
- Publication number
- CN1306826C CN1306826C CNB2004100702068A CN200410070206A CN1306826C CN 1306826 C CN1306826 C CN 1306826C CN B2004100702068 A CNB2004100702068 A CN B2004100702068A CN 200410070206 A CN200410070206 A CN 200410070206A CN 1306826 C CN1306826 C CN 1306826C
- Authority
- CN
- China
- Prior art keywords
- filtering
- boundary
- data
- vertical
- horizontal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001914 filtration Methods 0.000 claims abstract description 234
- 230000005055 memory storage Effects 0.000 claims description 23
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
- 238000004364 calculation method Methods 0.000 claims description 10
- 239000000284 extract Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 29
- 230000002349 favourable effect Effects 0.000 abstract 1
- 230000008520 organization Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
Abstract
The present invention relates to a loop filter based on a multistage parallel pipeline mode. Filtering calculating processes of the whole macroblock boundary strength, the boundary threshold process and the whole macroblock boundary are divided into two stage pipeline operation; each block data boundary is orderly filtered by the whole macroblock boundary filtering process according to the block stage pipeline mode; vertical / horizontal filters of multistage pipelines are orderly send to per line/ column data of the block boundary which does need to be filtered to filter, and filtered line/ column data is obtained; each block data of the current macroblock is filtered, at the meantime, the filtered data is operated to write external storage. The present invention utilizes the multistage parallel pipeline to complete the video image of the loop filtering of each macroblock boundary, the filtering speed is increased, the pressure of the external storage visit is reduced, the real-time performance of the image loop filtering operation is ensured in the image codec process, and besides, the complexity of the whole hardware structure is controlled so as to be favorable to the design and the implementation.
Description
Technical field
The present invention relates to a kind of encoding and decoding technique of digital picture, the loop filter in especially a kind of high-performance real-time video processor belongs to the video coding and decoding technology field.
Background technology
In the image encoding standard of the h.26x series of the MPEG of International Standards Organization and International Telecommunications Union, adopt block-based estimation and discrete cosine to change, the problem that this coding method brings is to have boundary effect between the adjacent image point of data block, i.e. blocking effect.In order to alleviate the tangible blocking effect that exists in the image coding and decoding process, many boundary filtering modes have been proposed, wherein up-to-date international code standard MPEG4-part 10/h.264 and domestic coding standard AVS have adopted loop filtering (deblocking loopfilter) method of deblocking effect, have improved the subjective quality of coded image significantly.
As shown in Figure 1, be the macro-block loop filtering flow chart, at first calculate and treat the boundary intensity and the boundary threshold on each bar border in the loop filtering macro block, boundary intensity that utilization calculates and threshold value are carried out filtering to the vertical boundary of macro block brightness data, horizontal boundary to the macro block brightness data carries out filtering again, and then respectively vertical boundary, the horizontal boundary of macro block chroma data are carried out filtering according to sequencing, will finish vertical, the filtered brightness of horizontal boundary, chroma data output at last.
As shown in Figure 2, be piece vertical/horizontal filtering boundary figure, it is vertical boundary 1 (vertical edge) and horizontal boundary 2 (horizontal edge) that macro block needs the border of filtering.
Because this loop filtering mode need be carried out filtering operation to each borderline picture element of blocks of data on the one hand, bring very big operand, on the other hand, in the process of filtering, need pixel value is carried out irregular visit, if so adopt general hardware design structure, the speed of the whole filtering of influence greatly can't be finished the requirement of the central image real time codec of practical application.
MPEG4-part 10/h.264 and AVS standard are respectively the world/interior up-to-date video encoding and decoding standards, the method of the complexity that the above-mentioned loop filter of the solution that has proposed brings is very limited, have only in several pieces of scientific papers and analyze and discuss addressing this problem, some implementations are proposed, but some implementation method is not considered loop filtering process and reference frame storing process and movement compensation process simultaneously, be confined to realize the loop filtering algorithm, shortage is considered from the designed image codec is whole, be unfavorable for the design use under the actual conditions, some method has proposed the implementation based on command word, comprise instruction storage and instruction decode procedure, the design that is suitable for the software accelerator realizes, is not suitable for the project organization of hardware.Thereby when in actual demand, the real time codec of high-definition image being handled, especially at present the processing speed of video image is more and more higher, these methods often can not be practical because hardware realization difficulty or cost are too big, and demand urgently further being improved.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of loop filter based on multistage parallel pipeline mode, utilize the multistage parallel pipeline structure to finish the loop filtering of each macroblock boundaries of video image, guarantee the real-time of image loop filtering operation in the image coding and decoding process, reduce the pressure of access external memory, and controlled the complexity of whole hardware configuration, thereby helped design and realization.
Technical problem to be solved by this invention is achieved by the following technical solution:
A kind of loop filter based on multistage parallel pipeline mode, it comprises the three class pipeline module: macroblock boundaries computing module, vertical/horizontal filtration module and output module; The three class pipeline module is moved simultaneously by the flowing water order;
Described macroblock boundaries computing module comprises filtering boundary strength calculator, filtering boundary threshold calculations device and first in first out data buffer; Described filtering boundary strength calculator and filtering boundary threshold calculations device extract the data boundary that needs filtered macroblock from external memory storage respectively, calculate the boundary intensity and the threshold value of each piece in the whole macro block, deposit the first in first out data buffer in; Described first in first out data buffer is input to the vertical/horizontal filtration module by the order of first in first out with the boundary intensity and the threshold value of macro block filtering;
Described vertical/horizontal filtration module comprises vertical/horizontal filter, arrangement machine, intermediate data buffer, selector and loop filtering controller; Described selector connects external memory storage, and under the control of loop filtering controller, described selector extracts the macroblock boundaries data that need filtering in the external memory storage, deposits the intermediate data buffer in; Described intermediate data buffer is connected with arrangement machine, and this arrangement machine also is input to the vertical/horizontal filter with the macroblock boundaries data successively by the ranks sequence arrangement; The raw column data that described vertical/horizontal filter transmits arrangement machine under the control of loop filtering controller is carried out the vertical/horizontal boundary filtering, with needing the data of filtering once more to write back to the intermediate data buffer among the filtered result, the data of finishing filtering are write output module;
Described output module comprises the dateout buffer and writes external memory interface.The data of finishing filtering that the storage of described dateout buffer is transmitted from the vertical/horizontal filter, and with transfer of data to writing external memory interface; The described external memory interface of writing will be finished the data of filtering and write external memory storage under the control of loop filtering controller.
Whole device is divided into three class pipeline and finishes loop filtering operation: first order streamline calculates boundary intensity and boundary threshold that will each filtering boundary of filtered macroblock; Second level streamline will be to carrying out vertical filtering and horizontal filtering by each bar filtering boundary of filtered macroblock; Third level streamline outputs to external memory storage to the macro block data of finishing filtering.By the three class pipeline operation, each process of loop filtering operation is assigned to different pipeline step, promptly reduced the complexity of every level production line operation, improved the concurrency of whole loop filtering operation again.
In whole loop filter, horizontal boundary and vertical boundary filtering also are designed to the multi-stage pipeline mode in the pile line operation of the second level, utilize two parallel pipeline organizations like this, can satisfy the requirement of in the high definition video real time codec process loop filtering being operated fully.
Described vertical/horizontal filter comprises filtering condition decision device module and filtering calculator modules;
Described filtering condition decision device module comprises filtering condition decision device and data buffer, the boundary intensity and the threshold value of the raw column data that described filtering condition decision device reception arrangement machine transmits, the macro block filtering that the first in first out data buffer transmits, calculate the boundary filtering judgment condition, decision will be carried out the edge pixel point of filtering operation, and edge pixel point is input to down level production line by data buffer will carry out filtering;
Described filtering calculator modules comprises the filtering calculator, and it carries out filtering calculating to each picture element, and with the picture element output after the filtering calculating.
Described filtering condition decision device is divided into two-stage or the above pipeline module of two-stage again, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.
Described filtering calculator is divided into two-stage or the above pipeline module of two-stage again, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.
The present invention finishes the filtering to macroblock boundaries through the following steps:
Step 1, under the control of loop filtering controller, selector extracts the macroblock boundaries data that need filtering in the external memory storage, deposit the intermediate data buffer in, by arrangement machine the macroblock boundaries data are pressed the ranks sequence arrangement again, and be input to the vertical/horizontal filter successively; Filtering boundary strength calculator and filtering boundary threshold calculations device extract the data boundary that needs filtered macroblock from external memory storage respectively simultaneously, calculate the boundary intensity and the threshold value of each piece in the whole macro block, deposit the first in first out data buffer in, the first in first out data buffer is input to the vertical/horizontal filter by the order of first in first out with block boundary intensity and threshold value.
The block boundary filtering strength of step 2, filter controller use upper level operational computations and boundary threshold are to whole macroblock boundaries filtering, and the loop filtering controller is controlled the vertical/horizontal filtering of whole macroblock boundaries according to piece level production line mode; With needing the data of filtering once more to write back to the intermediate data buffer among the filtered result, the data of finishing filtering are write output module.
Step 3, finish to the filtering operation of a blocks of data simultaneously, the row/columns that from middle data buffer the next one is needed the block boundary of filtering is sent into the vertical/horizontal filter successively according to above method and is carried out filtering operation according to reading;
Step 4, the operation of execution in step two and step 3 repeatedly are up to the filtration of finishing current whole macroblock boundaries data;
Step 5, simultaneously to each blocks of data filtering of current macro, the final data of vertical/horizontal filter output writes the dateout buffer memory, waits external memory interface to be written to write the operation of external memory storage.
The present invention utilizes the multistage parallel pipeline structure to finish the loop filtering of each macroblock boundaries of video image, the reference frame storing process in the middle of the codec design and the actual interface problem of loop filtering have been considered simultaneously, guaranteed the real-time of image loop filtering operation in the image coding and decoding process, reduced the pressure of access external memory, and controlled the complexity of whole hardware configuration, thereby helped design and realization.
Description of drawings
Fig. 1 macro-block loop filtering flow chart;
Fig. 2 piece vertical-horizontal filtering boundary figure;
Fig. 3 is a structural representation of the present invention;
Fig. 4 secondary flowing water horizontal/vertical boundary filter schematic diagram.
Embodiment
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is further specified:
First embodiment:
A kind of based on multistage parallel pipeline mode loop filter and realize the step of the loop filtering algorithm of AVS standard:
As shown in Figure 3, a kind of loop filter based on multistage parallel pipeline mode, it comprises the three class pipeline module: macroblock boundaries computing module, vertical/horizontal filtration module and output module; The three class pipeline module is moved simultaneously by the flowing water order;
Described macroblock boundaries computing module comprises filtering boundary strength calculator, filtering boundary threshold calculations device and FIFO (first in first out) data buffer; Described filtering boundary strength calculator and filtering boundary threshold calculations device extract the data boundary that needs filtered macroblock from external memory storage respectively, calculate the boundary intensity and the threshold value of each piece in the whole macro block, deposit the data fifo buffer in; Described data fifo buffer is input to the vertical/horizontal filtration module by the order of first in first out with the boundary intensity and the threshold value of macro block filtering;
Described vertical/horizontal filtration module comprises vertical/horizontal filter, arrangement machine, intermediate data buffer, selector and loop filtering controller; Described selector connects external memory storage, and under the control of loop filtering controller, described selector extracts the macroblock boundaries data that need filtering in the external memory storage, deposits the intermediate data buffer in; Described intermediate data buffer is connected with arrangement machine, and this arrangement machine also is input to the vertical/horizontal filter with the macroblock boundaries data successively by the ranks sequence arrangement; The raw column data that described vertical/horizontal filter transmits arrangement machine under the control of loop filtering controller is carried out the vertical/horizontal boundary filtering, with needing the data of filtering once more to write back to the intermediate data buffer among the filtered result, the data of finishing filtering are write output module.
Described output module comprises the dateout buffer and writes external memory interface; The data of finishing filtering that the storage of described dateout buffer is transmitted from the vertical/horizontal boundary filtering, and with transfer of data to writing external memory interface; The described external memory interface of writing will be finished the data of filtering and write external memory storage under the control of loop filtering controller.
Whole device is divided into three class pipeline and finishes loop filtering operation: first order streamline calculates boundary intensity and boundary threshold that will each bar filtering boundary of filtered macroblock; Second level streamline will be to carrying out vertical filtering and horizontal filtering by each bar filtering boundary of filtered macroblock; Third level streamline outputs to external memory storage to the macro block data of finishing filtering.By the three class pipeline operation, each process of loop filtering operation is assigned to different pipeline step, promptly reduced the complexity of every level production line operation, improved the concurrency of whole loop filtering operation again.
The present invention realizes the loop filtering algorithm of AVS standard through the following steps:
The boundary filtering strength of 8x8 blocks of data and boundary threshold in step 1, the computing macro block;
Step 2, from external memory, read in the data of the left side, top and the current block that need filtering simultaneously, these data are put into the intermediate data buffer;
After the blocks of data of step 3, current macro, boundary filtering strength and boundary threshold are ready to and left side piece treat filtering data through the intermediate data buffer, send into the data arrangement device simultaneously, send into successively in the vertical/horizontal filter according to the row order then;
By pipeline organization the vertical boundary data are carried out filtering in step 4, the vertical/horizontal filter, filtered data write back to the intermediate data buffer successively simultaneously;
Step 5, finish the vertical boundary filtering of a blocks of data of current macro after, the data of the left side macro block that can export are write the dateout buffer, the notice output interface is write the external memory operation, begins the next block boundary vertical filtering of current macro simultaneously;
Step 6, the operation of execution in step three, step 4 or step 5 repeatedly are up to the vertical filtering of finishing all block boundaries;
Step 7, the data of taking out wait horizontal filtering in top and the current macro border from middle buffer are sent into the data arrangement device;
The blocks of data process intermediate data buffer of filtering is treated in the blocks of data of step 8, current macro and top, sends into the data arrangement device simultaneously, sends into the vertical/horizontal filter successively according to the row order then;
By pipeline organization the horizontal boundary data are carried out filtering in step 9, the vertical/horizontal filter, filtered data write back to the intermediate data buffer successively simultaneously;
Step 10, finish the horizontal boundary filtering of a piece of current macro after, the data that can export in the macro block of top are write the dateout buffer, the notice output interface is write the external memory operation, begins the next block boundary horizontal filtering of current macro simultaneously;
Step 11, the operation of execution in step eight, step 9 or step 10 repeatedly are up to the horizontal filtering of finishing all block boundaries;
Step 12, according to finishing the loop filtering of each macro block in the frame with upper type and outputing to external memory.
Embodiment two:
A kind of based on multistage parallel pipeline mode loop filter and realize the step of the loop filtering algorithm of MPEG4-part10/h.264 standard:
As shown in Figure 3, a kind of loop filter based on multistage parallel pipeline mode, it comprises the three class pipeline module: macroblock boundaries computing module, vertical/horizontal filtration module and output module; The three class pipeline module is moved simultaneously by the flowing water order;
Described macroblock boundaries computing module comprises filtering boundary strength calculator, filtering boundary threshold calculations device and FIFO (first in first out) data buffer; Described filtering boundary strength calculator and filtering boundary threshold calculations device extract the data boundary that needs filtered macroblock from external memory storage respectively, calculate the boundary intensity and the threshold value of each piece in the whole macro block, deposit the data fifo buffer in; Described data fifo buffer is input to the vertical/horizontal filtration module by the order of first in first out with the boundary intensity and the threshold value of macro block filtering;
Described vertical/horizontal filtration module comprises vertical/horizontal filter, arrangement machine, intermediate data buffer, selector and loop filtering controller; Described selector connects external memory storage, and under the control of loop filtering controller, described selector extracts the macroblock boundaries data that need filtering in the external memory storage, deposits the intermediate data buffer in; Described intermediate data buffer is connected with arrangement machine, and this arrangement machine also is input to the vertical/horizontal filter with the macroblock boundaries data successively by the ranks sequence arrangement; The raw column data that described vertical/horizontal filter transmits arrangement machine under the control of loop filtering controller is carried out the vertical/horizontal boundary filtering, with needing the data of filtering once more to write back to the intermediate data buffer among the filtered result, the data of finishing filtering are write output module.
Described output module comprises the dateout buffer and writes external memory interface; The data of finishing filtering that the storage of described dateout buffer is transmitted from the vertical/horizontal boundary filtering, and with transfer of data to writing external memory interface; The described external memory interface of writing will be finished the data of filtering and write external memory storage under the control of loop filtering controller.
Whole device is divided into three class pipeline and finishes loop filtering operation: first order streamline calculates boundary intensity and boundary threshold that will each bar filtering boundary of filtered macroblock; Second level streamline will be to carrying out vertical filtering and horizontal filtering by each bar filtering boundary of filtered macroblock; Third level streamline outputs to external memory storage to the macro block data of finishing filtering.By the three class pipeline operation, each process of loop filtering operation is assigned to different pipeline step, promptly reduced the complexity of every level production line operation, improved the concurrency of whole loop filtering operation again.
As shown in Figure 4, in whole loop filter, horizontal boundary and vertical boundary filtering also are designed to the multi-stage pipeline mode in the pile line operation of the second level, utilize two parallel pipeline organizations like this, can satisfy the requirement of in the high definition video real time codec process loop filtering being operated fully.
Wherein, the vertical/horizontal filter comprises filtering condition decision device module and filtering calculator modules; Described filtering condition decision device module comprises filtering condition decision device and data buffer, the boundary intensity and the threshold value of the raw column data that described filtering condition decision device reception arrangement machine transmits, the macro block filtering that the first in first out data buffer transmits, calculate the boundary filtering judgment condition, decision will be carried out the edge pixel point of filtering operation, and edge pixel point is input to down level production line by data buffer will carry out filtering; Described filtering calculator modules comprises the filtering calculator, and it carries out filtering calculating to each picture element, and with the picture element output after the filtering calculating.
The filtering condition decision device can be divided into two-stage or the above pipeline module of two-stage, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.The filtering calculator can be divided into two-stage or the above pipeline module of two-stage, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.
The present invention realizes the loop filtering algorithm of MPEG4-part 10/h.264 standard through the following steps:
The boundary filtering strength of 4x4 blocks of data and boundary threshold in step 1, the computing macro block; Compare with the AVS standard, need the piece number of filtering many, but the size of the intermediate buffer that needs can reduce;
Step 2, from external memory, read in the data of the left side, top and the current block that need filtering simultaneously, these data are put into the intermediate data buffer;
After the blocks of data of step 3, current macro, boundary filtering strength and boundary threshold are ready to and left side piece treat filtering data through the intermediate data buffer, send into the data arrangement device simultaneously, send into successively in the vertical/horizontal filter according to the row order then;
By pipeline organization the vertical boundary data are carried out filtering in step 4, the vertical/horizontal filter, filtered data write back to the intermediate data buffer successively simultaneously;
Step 5, finish the vertical boundary filtering of a blocks of data of current macro after, the data of the left side macro block that can export are write the dateout buffer, the notice output interface is write the external memory operation, begins the next block boundary vertical filtering of current macro simultaneously;
Step 6, the operation of execution in step three, step 4 or step 5 repeatedly are up to the vertical filtering of finishing all block boundaries;
Step 7, the data of taking out wait horizontal filtering in top and the current macro border from middle buffer are sent into the data arrangement device;
The blocks of data process intermediate data buffer of filtering is treated in the blocks of data of step 8, current macro and top, sends into the data arrangement device simultaneously, sends into the vertical/horizontal filter successively according to the row order then;
By pipeline organization the horizontal boundary data are carried out filtering in step 9, the vertical/horizontal filter, filtered data write back to the intermediate data buffer successively simultaneously;
Step 10, finish the horizontal boundary filtering of a piece of current macro after, the data that can export in the macro block of top are write the dateout buffer, the notice output interface is write the external memory operation, begins the next block boundary horizontal filtering of current macro simultaneously;
Step 11, the operation of execution in step eight, step 9 or step 10 repeatedly are up to the horizontal filtering of finishing all block boundaries;
Step 12, according to finishing the loop filtering of each macro block in the frame with upper type and outputing to external memory.
The present invention utilizes the multistage parallel pipeline structure to finish the loop filtering of each macroblock boundaries of video image, guaranteed the real-time of image loop filtering operation in the image coding and decoding process, reduced the pressure of access external memory, and controlled the complexity of whole hardware configuration, thereby helped design and realization.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (8)
1, a kind of loop filter based on multistage parallel pipeline mode, it comprises macroblock boundaries computing module, vertical/horizontal filtration module and output module, it is characterized in that, described macroblock boundaries computing module and vertical/horizontal filtration module are parallel pipeline structure, move simultaneously by the flowing water order;
Described macroblock boundaries computing module extracts the data boundary that needs filtered macroblock from external memory storage, calculates the boundary intensity and the threshold value of each piece in the whole macro block, and is input to the vertical/horizontal filtration module;
Described vertical/horizontal filtration module comprises vertical/horizontal filter, arrangement machine, intermediate data buffer, selector and loop filtering controller; Described selector connects external memory storage, under the control of loop filtering controller, this selector extracts the macroblock boundaries data that need filtering in the external memory storage, deposit the intermediate data buffer in, by arrangement machine the macroblock boundaries data are pressed the ranks sequence arrangement again, and be input to the vertical/horizontal filter successively; Described vertical/horizontal filter utilizes the boundary intensity and the threshold value of the macro block filtering that the macroblock boundaries computing module transmits under the control of loop filtering controller, raw column data is carried out the vertical/horizontal boundary filtering, with needing the data of filtering once more to write back to the intermediate data buffer among the filtered result, the data of finishing filtering are write output module;
Described output module will be finished the data of filtering and write external memory storage.
2, the loop filter based on multistage parallel pipeline mode according to claim 1, it is characterized in that: described macroblock boundaries computing module comprises filtering boundary strength calculator and filtering boundary threshold calculations device, described filtering boundary strength calculator and filtering boundary threshold calculations device calculate the boundary intensity and the threshold value of each piece in the whole macro block respectively, and are input to the vertical/horizontal filter.
3, the loop filter based on multistage parallel pipeline mode according to claim 2, it is characterized in that: described macroblock boundaries computing module also comprises a data buffer, the boundary intensity and the threshold value of the macro block filtering that described data buffer reception and buffer memory filtering boundary strength calculator and filtering boundary threshold calculations device transmit, and be entered into the vertical/horizontal filter.
4, the loop filter based on multistage parallel pipeline mode according to claim 3 is characterized in that: described data buffer is the first in first out data buffer; Described first in first out data buffer is input to the vertical/horizontal filtration module by the order of first in first out with the boundary intensity and the threshold value of macro block filtering.
5, according to the arbitrary described loop filter based on multistage parallel pipeline mode of claim 1～4, it is characterized in that: described output module comprises the dateout buffer and writes external memory interface; The data of finishing filtering that the storage of described dateout buffer is transmitted from the vertical/horizontal filter, and with transfer of data to writing external memory interface; The described external memory interface of writing will be finished the data of filtering and write external memory storage under the control of loop filtering controller.
6, according to the arbitrary described loop filter based on multistage parallel pipeline mode of claim 1～4, it is characterized in that: described vertical/horizontal filter comprises filtering condition decision device module and filtering calculator modules;
Described filtering condition decision device module comprises filtering condition decision device and data buffer, the boundary intensity and the threshold value of the raw column data that described filtering condition decision device reception arrangement machine transmits, the macro block filtering that the first in first out data buffer transmits, calculate the boundary filtering judgment condition, decision will be carried out the edge pixel point of filtering operation, and edge pixel point is input to down level production line by data buffer will carry out filtering;
Described filtering calculator modules comprises the filtering calculator, and it carries out filtering calculating to each picture element, and with the picture element output after the filtering calculating.
7, the loop filter based on multistage parallel pipeline mode according to claim 6, it is characterized in that: described filtering condition decision device is divided into two-stage or the above pipeline module of two-stage again, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.
8, the loop filter based on multistage parallel pipeline mode according to claim 6, it is characterized in that: described filtering calculator is divided into two-stage or the above pipeline module of two-stage again, and the above pipeline module of two-stage or two-stage moves simultaneously by the flowing water order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100702068A CN1306826C (en) | 2004-07-30 | 2004-07-30 | Loop filter based on multistage parallel pipeline mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100702068A CN1306826C (en) | 2004-07-30 | 2004-07-30 | Loop filter based on multistage parallel pipeline mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1589032A CN1589032A (en) | 2005-03-02 |
| CN1306826C true CN1306826C (en) | 2007-03-21 |
Family
ID=34604436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100702068A Active CN1306826C (en) | 2004-07-30 | 2004-07-30 | Loop filter based on multistage parallel pipeline mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1306826C (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438630C (en) * | 2006-03-31 | 2008-11-26 | 清华大学 | Multi-pipeline phase information sharing method based on data buffer storage |
| CN100446573C (en) * | 2006-06-22 | 2008-12-24 | 上海交通大学 | Implementation device in VLSI of filter for removing blocking effect based on AVS |
| CN101115195B (en) * | 2006-07-24 | 2010-08-18 | 同济大学 | Macroblock grade coupled decoding and loop filtering method and apparatus for video code stream |
| JP4712642B2 (en) * | 2006-08-17 | 2011-06-29 | 富士通セミコンダクター株式会社 | Deblocking filter, image encoding device, and image decoding device |
| CN101193305B (en) * | 2006-11-21 | 2010-05-12 | 安凯(广州)微电子技术有限公司 | Inter-frame prediction data storage and exchange method for video coding and decoding chip |
| CN101005619B (en) * | 2006-12-25 | 2010-09-01 | 海信集团有限公司 | Loop circuit filtering method |
| CN101212665B (en) * | 2007-12-25 | 2012-01-25 | 海信集团有限公司 | Loop circuit filtering method |
| CN101841722B (en) * | 2010-06-08 | 2011-08-31 | 上海交通大学 | Detection method of detection device of filtering boundary strength |
| CN102572416B (en) * | 2010-12-22 | 2014-11-05 | 中兴通讯股份有限公司 | Video filtering method and device |
| CN102098515B (en) * | 2011-02-18 | 2012-12-12 | 杭州海康威视数字技术股份有限公司 | Realizing method of loop filtering parallel |
| CN102223538A (en) * | 2011-06-17 | 2011-10-19 | 中兴通讯股份有限公司 | Parallel filtering method and device |
| CN103731674B (en) * | 2014-01-17 | 2017-02-01 | 合肥工业大学 | H.264 two-dimensional parallel post-processing block removing filter hardware achieving method |
| CN105791865B (en) * | 2014-12-22 | 2020-01-17 | 江苏省电力公司南京供电公司 | Intra-frame prediction and deblocking filtering method |
| CN107392838B (en) * | 2017-07-27 | 2020-11-27 | 苏州浪潮智能科技有限公司 | WebP compression parallel acceleration method and device based on OpenCL |
| US10939102B2 (en) * | 2018-11-01 | 2021-03-02 | Mediatek Inc. | Post processing apparatus with super-resolution filter and loop restoration filter in block-level pipeline and associated post processing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1170318A (en) * | 1996-07-06 | 1998-01-14 | 三星电子株式会社 | Loop filtering method for reducing group effect of moving compensation image and ringing noise |
| CN1189652A (en) * | 1997-01-29 | 1998-08-05 | 三星电子株式会社 | Loop filter and loop filtering method |
| US20030026337A1 (en) * | 2001-06-15 | 2003-02-06 | Lg Electronics Inc. | Loop filtering method in video coder |
-
2004
- 2004-07-30 CN CNB2004100702068A patent/CN1306826C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1170318A (en) * | 1996-07-06 | 1998-01-14 | 三星电子株式会社 | Loop filtering method for reducing group effect of moving compensation image and ringing noise |
| JPH1066090A (en) * | 1996-07-06 | 1998-03-06 | Samsung Electron Co Ltd | Block processing effect of video image subject to motion compensation and loop filtering method to reduce ringing noise |
| CN1189652A (en) * | 1997-01-29 | 1998-08-05 | 三星电子株式会社 | Loop filter and loop filtering method |
| US20030026337A1 (en) * | 2001-06-15 | 2003-02-06 | Lg Electronics Inc. | Loop filtering method in video coder |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1589032A (en) | 2005-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1306826C (en) | Loop filter based on multistage parallel pipeline mode | |
| CN1812576A (en) | Deblocking filters for performing horizontal and vertical filtering of video data simultaneously and methods of operating the same | |
| CN1794814A (en) | Pipelined deblocking filter | |
| CN101170701B (en) | Block elimination filtering method and device for video encoding and decoding system | |
| CN1874516A (en) | Implementation device in VLSI of filter for removing blocking effect based on AVS | |
| CN101583041A (en) | Image filtering method of multi-core image encoding processing equipment and equipment | |
| CN110337002B (en) | HEVC (high efficiency video coding) multi-level parallel decoding method on multi-core processor platform | |
| CN101707716B (en) | Video coder and coding method | |
| CN101115207B (en) | Method and device for implementing interframe forecast based on relativity between future positions | |
| CN107231558A (en) | A kind of implementation method of the H.264 parallel encoder based on CUDA | |
| CN101409833B (en) | De-block effect filtering device and method | |
| CN108540797A (en) | HEVC based on multi-core platform combines WPP coding methods within the frame/frames | |
| CN1905677A (en) | Data buffer storage method of variable size block motion compensation and implementing apparatus thereof | |
| CN1852442A (en) | Layering motion estimation method and super farge scale integrated circuit | |
| CN1266942C (en) | Image processor | |
| CN102137257B (en) | Embedded H.264 coding method based on TMS320DM642 chip | |
| CN1112654C (en) | Image processor | |
| CN102801973B (en) | Video image deblocking filter method and device | |
| CN1874512A (en) | High performance pipeline system in use for AVS video decoder | |
| CN106210727B (en) | Video hierarchical code stream coding method and system based on neural network processor array | |
| CN101459839A (en) | Deblocking effect filtering method and apparatus for implementing the method | |
| CN102075753B (en) | Method for deblocking filtration in video coding and decoding | |
| CN104602026B (en) | A kind of reconstruction loop structure being multiplexed entirely encoder under HEVC standard | |
| CN1825960A (en) | Multi-pipeline phase information sharing method based on data buffer storage | |
| CN107454406A (en) | The live high-speed decoding method of VR panoramic videos and system based on AVS+ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ZHANXUN COMMUNICATIONS (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: UNITED XINYUAN DIGITAL AUDIO-VIDEO TECHNOLOGY (BEIJING) CO., LTD. Effective date: 20070608 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20070608 Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park Lane 2288 newshow Center Building No. 1 Patentee after: Spreadtrum Communications (Shanghai) Inc. Address before: 100080 North building, room 6, 140 South Road, Haidian District Academy of Sciences, Beijing Patentee before: UNITED XINYUAN DIGITAL AUDIO V |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190314 Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd. Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park Lane 2288 newshow Center Building No. 1 Patentee before: Spreadtrum Communications (Shanghai) Inc. |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20050302 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd. Contract record no.: X2021110000008 Denomination of invention: Loop filter based on multistage parallel pipeline Granted publication date: 20070321 License type: Exclusive License Record date: 20210317 |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221018 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd. |