CN1577771A - Method for forming Low-temperature polysilicon thin film transistor - Google Patents
Method for forming Low-temperature polysilicon thin film transistor Download PDFInfo
- Publication number
- CN1577771A CN1577771A CN 03143668 CN03143668A CN1577771A CN 1577771 A CN1577771 A CN 1577771A CN 03143668 CN03143668 CN 03143668 CN 03143668 A CN03143668 A CN 03143668A CN 1577771 A CN1577771 A CN 1577771A
- Authority
- CN
- China
- Prior art keywords
- grid
- npn
- layer
- electrode
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The method of forming low temperature polysilicon film transistor includes the following steps: forming one polysilicon layer on the substrate; forming one grid oxide layer on the polysilicon layer, making pattern in the grid oxide layer and the polysilicon layer via photoetching and etching; forming one grid no the grid oxide layer; and injecting dopant with the grid as mask to form source and drain.
Description
Technical field
The relevant a kind of process that forms low-temperature polysilicon film transistor of the present invention, and form the process that no photic resist and chemical solvent residue in the low-temperature polysilicon film transistor on the polysilicon about a kind of especially.
Background technology
Thin-film transistor in the flat-panel screens is how made with amorphous silicon (amorphous silicon) now, and minority high-order product is then made with the high polysilicon of electron mobility (mobility) (poly silicon).The integrated more electronic circuit of polysilicon technology tolerable, thereby can reduce the complexity and the weight of integral product.In the polysilicon process, maximum temperature is about more than 500 ℃, the temperature that begins to soften near glass substrate.
Please refer to Figure 1A～1J, it shows the making flow process of a traditional low-temperature polysilicon film transistor.At first, in Figure 1A, a resilient coating 102, a polysilicon layer 104 are formed on the substrate 100 in regular turn, and wherein, polysilicon layer 104 utilizes excimer laser one amorphous silicon layer is carried out the crystallization tempering and to form; Then, form a photoresist layer 105 with pattern again on polysilicon layer 104, and be mask with photoresist layer 105, etching polysilicon layer 104, remove residual photoresist with chemical solvent again after, its structure is shown in Figure 1B.
Then, with reference to figure 1C, deposition one deck grid oxic horizon 108 and forms a conductive layer on grid oxic horizon 108 on resilient coating 102 and polysilicon layer 104, utilize photoetching and etch process after, formation one has the grid 110 of pattern.Then, in Fig. 1 D, form a photoresist layer 112 on grid 110 and grid oxic horizon 108, and be mask with photoresist layer 112, substrate 100 is injected the phosphorus dopant of heavy concentration, and form the transistorized source/drain regions 104a of NMOS (N type metal oxide semiconductor), 104b, 104c and 104d.
Afterwards, in Fig. 1 E, remove residual photoresist layer 112, and be mask, substrate 100 is injected the phosphorus dopant of light concentration, and form slight doped region 104m, 104n, 104x and the 104y of nmos pass transistor with grid layer 110.Then, in Fig. 1 F, form a photoresist layer 114 once more on grid 110 and grid oxic horizon 108, and be mask with photoresist layer 114, substrate 100 is injected the boron dope agent of heavy concentration, and form the source/drain regions 104i and the 104j of P transistor npn npn.
In Fig. 1 G, remove photoresist layer 114 earlier, form an inner layer dielectric layer 116 again on grid layer 110 and grid oxic horizon 108, and form several openings, among inner layer dielectric layer 116 and grid oxic horizon 108.Then, in Fig. 1 H, the electrode 118 that formation can be electrically connected with 104j with source/ drain regions 104a, 104b, 104c, 104d, 104i.
Then, in Fig. 1 I, form a protective layer 120 on electrode layer 118 and inner layer dielectric layer 116, and formation is opened in the protective layer 120 of pixel region.At last, in Fig. 1 J, the transparency electrode 122 that formation can be electrically connected with the electrode 118 of pixel region is to finish the technology with low-temperature polysilicon film transistor.
Yet, the application of the polysilicon of high electron mobility, but because among Figure 1B, it is residual that chemical solvent is failed the photoresist removed fully on the polysilicon layer 104, and the chemical solvent on the polysilicon layer 104 is residual, causes the decline of its mobility on the contrary, and the residual phenomena of photoresist and chemical solvent, more cause other characterisitic parameter to fall within outside the desired value, for example: critical voltage (thresholdvoltage) and subcritical voltage increasing degree (sub-threshold swing).
Therefore, be necessary that problem proposes a method that solves for this reason.
Summary of the invention
In view of this, purpose of the present invention is exactly to be to provide a kind of process that photic resist and chemical solvent residue in the low-temperature polysilicon film transistor on the grid of not having.
According to purpose of the present invention, a kind of formation one nmos pass transistor and the method for a PMOS transistor on a substrate are proposed, this method comprises at least: form a resilient coating on substrate; Form a thickness and be about the polysilicon layer of 200～1000 dusts on resilient coating; Form a thickness and be about the grid oxic horizon of 500～1500 dusts on polysilicon layer; Patterning grid oxide layer and polysilicon layer are to form corresponding to first stacked structure of nmos pass transistor and corresponding to transistorized second stacked structure of PMOS; Form one by one of them grid of forming of molybdenum, chromium or titanium/aluminium/titanium on grid oxic horizon; Form the source electrode and the drain electrode of nmos pass transistor, it utilizes whole second stacked structures of a covering to be mask with the photoresist layer that covers the slight doped region of nmos pass transistor at least, and implantation dosage is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2Phosphorus dopant and form; Form the slight doped region of nmos pass transistor, it utilizes grid to be mask, and implantation dosage is about 8 * 10
12Dose/cm
2～5 * 10
13Dose/cm
2Phosphorus dopant and form; And forming transistorized source electrode of PMOS (P-type mos) and drain electrode, it utilizes a photoresist layer that covers whole these first stacked structures to be mask, and implantation dosage is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2Boron dope agent and form.
Formation method of the present invention more comprises: form a thickness and be about the inner layer dielectric layer of 2000～7000 dusts on grid oxic horizon, grid layer and substrate; Optionally expose the transistorized source electrode of nmos pass transistor and PMOS, drain electrode and grid; Formation is by one of them electrode of forming of molybdenum, chromium or titanium/aluminium/titanium, the nmos pass transistor and the transistorized source electrode of PMOS, drain electrode and the grid that are exposed with electrical connection; Form a protective layer with pattern on inner layer dielectric layer and electrode, the protective layer exposure one with pattern is positioned at the partial electrode of the nmos pass transistor of pixel region; And form the transparency electrode of forming by indium tin oxide, to be electrically connected the partial electrode that is exposed of nmos pass transistor.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below, wherein:
Figure 1A～1J, it shows the making flow process of a traditional low-temperature polysilicon film transistor; And
Fig. 2 A～2J, it shows the making flow process of low-temperature polysilicon film transistor of the present invention.
Description of reference numerals in the accompanying drawing is as follows:
100: substrate 102: resilient coating
104: polysilicon layer
104a, 104b, 104c, 104d, 104i, 104j: source/drain regions
104m, 104n, 104x, 104y: slight doped region
105: photoresist layer 108: grid oxic horizon
110: grid 112: the photoresist layer
114: photoresist layer 116: inner layer dielectric layer
118: electrode 120: protective layer
122: transparency electrode 200: substrate
202: resilient coating 204: polysilicon layer
204a, 204b, 204c, 204d, 204i, 204j: source/drain regions
204m, 204n, 204x, 204y: slight doped region
205: photoresist layer 208: grid oxic horizon
210: grid 212: the photoresist layer
214: photoresist layer 216: inner layer dielectric layer
218: electrode 220: protective layer
222: transparency electrode
Embodiment
The invention provides one and solve problem residual because of photoresist and deterioration in quality that chemical residual causes.
Please refer to Fig. 2 A～2J, it shows the making flow process of low-temperature polysilicon film transistor of the present invention.At first, in Fig. 2 A, one resilient coating 202, a polysilicon layer 204, be formed in regular turn on the substrate 200, wherein, substrate 200 can be glass or plastic material, and the thickness of polysilicon layer 204 is about 200～1000 dusts, and utilize excimer laser, be formed at amorphous silicon layer on the resilient coating 202 to one and carry out the crystallization tempering and form.Resilient coating 202 can be silica or silicon nitride constitutes.
Then, before also polysilicon layer 204 not being carried out patterning, a grid oxic horizon 208 directly is formed on the polysilicon layer 204, and the thickness of grid oxic horizon 208 is about between 500～1500 dusts, and its material can be silicon dioxide.Then, utilize photoetching process, form one and have the photoresist layer 205 of pattern on polysilicon layer 204, and be mask with photoresist layer 205, etching grid oxide layer 208 and polysilicon layer 204 in regular turn, after removing the photoresist that remains on the grid oxic horizon 208 with chemical solvent again, obtain the structure shown in Fig. 2 B.Wherein, two stacked structures of left are in order to forming a CMOS transistor, and right-hand stacked structure is in order to form the nmos pass transistor in the pixel region.
It should be noted that, owing to form between grid oxic horizon 208 and the formation polysilicon layer 204, there is no other processing step, for example: the formation of photoresist layer, or utilize removing of photoresist layer that chemical solvent carries out, therefore, between grid oxic horizon 208 and the polysilicon layer 204, neither have the residual of photoresist layer, also do not have the residual of chemical solvent, this kind improvement to the quality of the follow-up low-temperature polysilicon film transistor of finishing, will have very big benefiting.
Then, with reference to figure 2C, deposit a conductive layer on entire substrate 200, and utilize photoetching and etch process, form grid 210, grid 210 can be made up of with titanium/aluminium/titanium molybdenum (Mo), chromium (Cr).Then, in Fig. 2 D, by photoetching process, form one and have the photoresist layer 212 of pattern on substrate 210, the drain/source zone of the exposed transistorized nmos transistor regions of CMOS of photoresist layer 212, with the drain/source zone of the nmos transistor region of pixel region, and cover other zone.Afterwards, be mask then with photoresist layer 212, substrate 200 is injected the phosphorus dopant that weighs concentration, its dosage is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2, to form source/ drain regions 204a, 204b, 204c and the 204d of nmos pass transistor.
Afterwards, in Fig. 2 E, remove residual photoresist layer 212, and be mask with grid 210 directly, to the phosphorus dopant of the light concentration of substrate 200 injections, its dosage is about 8 * 10
12Dose/cm
2～5 * 10
13Dose/cm
2, and slight doped region 204m, 204n, 204x and the 204y of formation N transistor npn npn.Then, in Fig. 2 F, once more by photoetching process, form one and have the photoresist layer 214 of pattern on substrate 210, photoresist layer 214 covers the transistorized nmos transistor region of CMOS fully, and the nmos transistor region of pixel region, and do not cover the transistorized PMOS transistor area of CMOS.And be mask with photoresist layer 214, substrate 200 is injected the boron dope agent of heavy concentration, its dosage is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2, to form transistorized source/drain regions 204i of PMOS and 204j.
Then, in Fig. 2 G, remove photoresist layer 214 earlier, form an inner layer dielectric layer 216 again on entire substrate 200, and utilize photoetching and etch process, form several openings, among inner layer dielectric layer 216 and grid oxic horizon 208, inner layer dielectric layer 216 can be made up of silicon dioxide, and its thickness is about 2000～7000 dusts.Then, in Fig. 2 H, form a conductive layer on inner layer dielectric layer 216, and fill up the opening that is positioned among inner layer dielectric layer 216 and the grid oxic horizon 208, utilize photoetching and etch process again, formation can with the part of grid 210 and source/ drain regions 204a, 204b, 204c, 204d, 204i and 204j, the electrode 218 of electrical connection.Situation that to be electrode 218 be electrically connected with 204j with source/ drain regions 204a, 204b, 204c, 204d, 204i that this embodiment is shown.
Then, in Fig. 2 I, form a protective layer 220 on electrode 218 and inner layer dielectric layer 216, and utilize photoetching and etch process, formation is opened in the protective layer 220 of pixel region.At last; in Fig. 2 J; the conductive layer that formation is made up of indium tin oxide (ITO) is on protective layer 220; and fill up opening among the protective layer 220; utilize photoetching and etch process again; the transparency electrode 222 that formation can be electrically connected with the electrode 218 of pixel region is to finish the technology with low-temperature polysilicon film transistor.
The disclosed process of the above embodiment of the present invention, can avoid because of the photoresist on the polysilicon layer 204 residual, and the chemical solvent on the polysilicon layer 204 is residual, the decline of the transistorized mobility of the low temperature polycrystalline silicon that causes (mobility), and cause transistorized critical voltage of low temperature polycrystalline silicon (threshold voltage) and subcritical voltage increasing degree characterisitic parameters such as (sub-threshold swing), fall within outside the desired value.Therefore, process provided by the present invention can improve the quality of flat-panel screens product.
In sum; though the present invention with a preferred embodiment openly as above; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be as the criterion so that claim is determined.
Claims (20)
1. method that forms low-temperature polysilicon film transistor, this method comprises at least:
Form a polysilicon layer on this substrate;
Form a grid oxic horizon on this polysilicon layer;
This grid oxic horizon of patterning and this polysilicon layer, it utilizes photoetching and etch process to finish;
Form a grid on this grid oxic horizon; And
Inject dopant, it is a mask with this grid, to form source electrode and drain electrode.
2. the method for claim 1 wherein should form before the polysilicon step, also comprised forming the step of a resilient coating on this substrate.
3. the method for claim 1, wherein the thickness of this polysilicon layer is about 200～1000 dusts.
4. the method for claim 1, wherein the thickness of this grid oxic horizon is about 500～1500 dusts.
5. the method for claim 1, wherein this grid is formed by molybdenum, chromium or titanium/aluminium/titanium one of them.
6. the method for claim 1, wherein the dosage of this injection dopant is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2
7. one kind forms one first transistor npn npn and the method for one second transistor npn npn on a substrate, and this method comprises at least:
Form a polysilicon layer on this substrate;
Form a grid oxic horizon on this polysilicon layer;
This grid oxic horizon of patterning and this polysilicon layer are to form corresponding to first stacked structure of this first transistor npn npn and second stacked structure corresponding to this second transistor npn npn;
Form a grid on this grid oxic horizon, this grid is less than this grid oxic horizon;
Form the source electrode and the drain electrode of this first transistor npn npn, it utilizes a photoresist layer that covers whole these second stacked structures and cover the slight doped region of this first transistor npn npn at least to be mask, and injects the first severe dopant and form;
Form the slight doping of this first transistor npn npn, it utilizes this grid to be mask, and injects the first slight dopant and form; And
Form the source electrode and the drain electrode of this second transistor npn npn, it utilizes one to cover all that the photoresist layer of these first stacked structures is mask, and injects the second severe dopant and form.
8. method as claimed in claim 7 wherein should form before the polysilicon step, also comprised forming the step of a resilient coating on this substrate.
9. method as claimed in claim 7 after this forms the source electrode and drain electrode step of second transistor npn npn, also comprises:
Form an inner layer dielectric layer on this grid oxic horizon, this grid and this substrate;
Optionally expose source electrode, drain electrode and the grid of this first transistor npn npn and this second transistor npn npn; And
Form this first transistor npn npn that electrode is exposed with electrical connection and source electrode, drain electrode and the grid of this second transistor npn npn.
10. method as claimed in claim 9, wherein the thickness of this inner layer dielectric layer is about 2000～7000 dusts.
11. method as claimed in claim 9, wherein this electrode is formed by molybdenum, chromium or titanium/aluminium/titanium one of them.
12. method as claimed in claim 9 after this forms the electrode step, also comprises:
Form a protective layer with pattern on this inner layer dielectric layer and this electrode, this protective layer exposure one with pattern is positioned at the partial electrode of first transistor npn npn of pixel region; And
Form transparency electrode to be electrically connected the partial electrode that is exposed of first transistor npn npn.
13. method as claimed in claim 12, wherein this transparency electrode is formed by indium tin oxide.
14. method as claimed in claim 7, wherein the thickness of this polysilicon layer is about 200～1000 dusts.
15. method as claimed in claim 7, wherein the thickness of this grid oxic horizon is about 500～1500 dusts.
16. method as claimed in claim 7, wherein this grid is formed by molybdenum, chromium or titanium/aluminium/titanium one of them.
17. method as claimed in claim 7, wherein the dosage of this first severe dopant is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2
18. method as claimed in claim 7, wherein the dosage of this first slight dopant is about 8 * 10
12Dose/cm
2～5 * 10
13Dose/cm
2
19. method as claimed in claim 7, wherein the dosage of this second severe dopant is about 1 * 10
14Dose/cm
2～5 * 10
15Dose/cm
2
20. method as claimed in claim 7, wherein this first transistor npn npn is a nmos pass transistor, and this second transistor npn npn is the PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031436684A CN1301539C (en) | 2003-07-28 | 2003-07-28 | Method for forming Low-temperature polysilicon thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031436684A CN1301539C (en) | 2003-07-28 | 2003-07-28 | Method for forming Low-temperature polysilicon thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1577771A true CN1577771A (en) | 2005-02-09 |
| CN1301539C CN1301539C (en) | 2007-02-21 |
Family
ID=34579474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031436684A Expired - Lifetime CN1301539C (en) | 2003-07-28 | 2003-07-28 | Method for forming Low-temperature polysilicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1301539C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437119A (en) * | 2011-08-15 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving effect of stress memory technology |
| CN102738002A (en) * | 2011-04-06 | 2012-10-17 | 株式会社半导体能源研究所 | Manufacturing method of semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3377853B2 (en) * | 1994-03-23 | 2003-02-17 | ティーディーケイ株式会社 | Method for manufacturing thin film transistor |
| KR100218500B1 (en) * | 1995-05-17 | 1999-09-01 | 윤종용 | Silicone film and manufacturing method thereof, and thin-film transistor and manufacturing method thereof |
| JP3514912B2 (en) * | 1995-08-31 | 2004-04-05 | 東芝電子エンジニアリング株式会社 | Method for manufacturing thin film transistor |
| US5943560A (en) * | 1996-04-19 | 1999-08-24 | National Science Council | Method to fabricate the thin film transistor |
| EP0844670B1 (en) * | 1996-06-06 | 2004-01-02 | Seiko Epson Corporation | Method for manufacturing thin film transistor, liquid crystal display and electronic device both produced by the method |
| JPH11111998A (en) * | 1997-10-06 | 1999-04-23 | Sanyo Electric Co Ltd | Manufacture of thin-film transistor |
-
2003
- 2003-07-28 CN CNB031436684A patent/CN1301539C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738002A (en) * | 2011-04-06 | 2012-10-17 | 株式会社半导体能源研究所 | Manufacturing method of semiconductor device |
| CN102738002B (en) * | 2011-04-06 | 2017-05-31 | 株式会社半导体能源研究所 | The manufacture method of semiconductor device |
| US9960278B2 (en) | 2011-04-06 | 2018-05-01 | Yuhei Sato | Manufacturing method of semiconductor device |
| CN102437119A (en) * | 2011-08-15 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving effect of stress memory technology |
| CN102437119B (en) * | 2011-08-15 | 2014-08-06 | 上海华力微电子有限公司 | Method for improving effect of stress memory technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1301539C (en) | 2007-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6924874B2 (en) | Method of forming a liquid crystal display | |
| CN100339964C (en) | Method for making MOS having light doped drain electrode | |
| CN1855393A (en) | Thin film transistor and method of fabricating the same | |
| US7061019B2 (en) | Semiconductor circuit array substrate with a photo-electric sensor portion | |
| CN108447822A (en) | The production method of LTPS TFT substrates | |
| CN1287468C (en) | Thin film transistor and method for producing thin film transistor | |
| CN1196173C (en) | Device and method for manufacture of liquid crystal display | |
| CN108511464B (en) | Manufacturing method of CMOS L TPS TFT substrate | |
| CN1564313A (en) | Thin film transistor and its mfg. method | |
| CN1301539C (en) | Method for forming Low-temperature polysilicon thin film transistor | |
| US11469329B2 (en) | Active switch, manufacturing method thereof and display device | |
| CN1652349A (en) | Thin film transistor, method of fabricating the same and flat panel display using thin film transistor | |
| US6773467B2 (en) | Storage capacitor of planar display and process for fabricating same | |
| CN1297008C (en) | CMOS thin film transistor and display device using the same | |
| CN1542948A (en) | Method for forming CMOS transistor | |
| CN1265446C (en) | Method for making film transistor | |
| CN1222022C (en) | Process for preparing thin film transistor and its structure | |
| CN1230891C (en) | Manufacture method of CMOS film transistor module | |
| CN1324388C (en) | Manufacture of low temperature polycrystal silicon film electric crystal LCD device | |
| CN1624931A (en) | Thin film transistor of multi-grid structure and manufacturing method thereof | |
| CN1309031C (en) | Method of inhibiting short channel effect in semiconductor device | |
| CN1165076C (en) | Transistor with anti-breakover regino generated by ion implantation and its preparing process | |
| CN1779929A (en) | Production of thin-film transistor | |
| CN1301550C (en) | Method of mfg complementary thin film transister | |
| US7064017B2 (en) | Method of forming a CMOS transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070221 |