Embodiment
Further specify the specific embodiment of the present invention below in conjunction with drawings and Examples.
Voltage draws partially and the test platform of environmental testing is that the present invention will be described for example to carry out at the DDR internal memory in the present embodiment.
At first introduce the requirement of DDR internal memory to power supply, DDR internal memory need of work mainboard provides two kinds of power supplys: 1) reference voltage VREF, 2) operating voltage VDIMM.It is 1.25V that design specifications requires reference voltage VREF, and operating voltage VDIMM is 2.50V, the variation range of permission is+and-5%.
Present embodiment is exactly the performance change of coming test memory (to comprise temperature, voltage, load) partially under various environment by to drawing of VDIMM and VREF, and the concrete folk prescription formula of drawing has following two kinds:
1) VDIMM and VREF draw partially simultaneously jointly
Draw the folk prescription formula to guarantee that VDIMM and VREF change synchronously simultaneously, fundamental purpose is the truth for the operation of emulation main board system, can verify that on this platform mainboard voltage changes the influence to the internal memory operation.
2) VDIMM and VREF independently draw respectively partially
Independently draw the folk prescription formula mainly to investigate the influence of noise margin respectively to internal memory work.
In addition, the test platform operating temperature range of present embodiment is 0 ℃---55 ℃.
Be illustrated in figure 1 as present embodiment test macro The general frame, system mainly forms by controlling platform 101 and test platform 102 and warm and humid control box 103 3 parts, test platform 102 is placed within the described warm and humid control case 103, passes through I between control platform 101 and the test platform 102
2The C bus realizes the communication of data, realizes data communication by the R-232 interface between control platform 101 and the warm and humid control box 103.
The composition frame chart of control platform 101 and test platform 102 is seen shown in Figure 2, control platform 101 is personal computers (PC), adopt INTEL845GE+ICH4 mainboard north and south bridge chip group platform, mainly comprise: Control Software 201, control platform Basic Input or Output System (BIOS) (BIOS) 202, control platform I
2A C communication interface circuit 203 and a special-purpose pci card 204 that on peripheral element extension interface (PCI) slot of this PC mainboard, increases, comprise electrical isolation circuit 211 on this special use pci card 204, wherein, being necessary for test on the BIOS (202) of this PC need and increase the control corresponding code, and special-purpose pci card 204 major functions are to utilize I
2C bus and test platform 102 mainboards carry out data transmission, realize electrical isolation simultaneously.
Control platform 101 passes through I by the setting that operation Control Software 201 thereon realizes internal memory voltage-regulation mode
2The C bus sends the actual voltage value that memory voltage is regulated information and read internal memory from test platform 102 to test platform 102, write down all test datas and generate test report, control the temperature and humidity and the retention time of warm and humid control case 103 simultaneously by the R-232 interface.
Test platform 102 adopts INTEL845GE+ICH4 mainboard north and south bridge chip group platform, mainly comprises: mainboard parallel port 205, test platform electrical isolation circuit 212, test platform I
2C communication interface circuit 206, signaling conversion circuit 207, observation circuit (SUPER I/O) 208, voltage draws inclined to one side circuit 209, background test software 210, wire jumper circuit 213 and overvoltage crowbar 214.Wherein, on the mainboard of test platform 102 with I
2The C bus is connected on this mainboard parallel port 205, and this mainboard parallel port 205 only is a data-interface, does not possess former mainboard parallel port function; The mainboard of control platform 101 is realized the transmission of data and control signal by the mainboard parallel port 205 of pci card 204 and test platform 102; Background test software 210 is used for the performance test to the DDR memory bar.
Test platform 102 is as the carrier of tested DDR memory bar; the control information of response control platform 101; draw inclined to one side circuit 209 to regulate DDR internal memory supply voltage automatically by voltage; by the overvoltage protection of overvoltage crowbar 214 realizations to memory power supply; utilize observation circuit (SUPER I/O) 208 to gather internal memories and draw bias-voltage and draw test macro running state information such as inclined to one side mainboard surface temperature, and the control platform is given in passback.
The hardware platform that the present embodiment test platform is adopted is an INTEL845GE+ICH4 mainboard north and south bridge chip group platform, and it supports the DDR internal memory.The operating voltage VDIMM of DDR internal memory is 2.5V, test request VDIMM can realize the variation (the every variation of voltage variable quantity once is 40mV) of at least 16 steps in the scope of 2.2V-2.8V, so, used voltage to draw inclined to one side circuit that the operating voltage VDIMM of DDR internal memory is carried out high low bias test.
Voltage draws inclined to one side circuit as shown in Figure 3, it is MOSFET field effect transistor 1 that this voltage draws the control end of inclined to one side circuit, 2,3,4 input end a, b, c, d receives control signal, MOSFET field effect transistor 1,2,3,4 respectively with regulating resistor R1, R2, R3, the polyphone of R4, these four regulating resistor R1, R2, R3, R4 respectively with MOSFET field effect transistor 1,2,3,4 form 4 pressure regulation branch roads 301, the output terminal of these 4 pressure regulation branch roads also connects, and contact e is connected on again on the dividing point f of dividing potential drop branch road 303 in the voltage stabilizing branch road 302, this dividing point f links to each other with the output of voltage-stabilizing device 304, the output voltage of this voltage-stabilizing device is Vr, dividing point f is by divider resistance R1 ' ground connection, meet output terminal g by divider resistance R2 ', this output terminal g draws inclined to one side operating voltage VDIMM for the DDR internal memory provides, do not inserting before the regulating circuit, output voltage V DIMM is:
VDIMM=Vr+I*R2’
Wherein, R2 ' difference according to actual needs can be chosen different resistances.
In Fig. 3, because Vr fixes, therefore, the value that changes electric current I just can change the size of output voltage.Various combination by regulating resistor R1, R2, R3, R4 obtains different resistance values, thereby the electric current I value in the change following formula, 4 grades of regulating resistors have been adopted in the present embodiment, and the resistance of each regulating resistor has nothing in common with each other, can make conducting of 4 MOSFET field effect transistor or shutoff by the state that changes control end a, b, c, d, thereby make these 4 regulating resistors add or not add circuit, promptly can obtain 16 kinds of different magnitudes of voltage at the VDIMM end.
Because I
2The C bus control signal is a serial signal, so needing a signaling conversion circuit 307 is 4 parallel control signals with this serial bus control conversion of signals, signaling conversion circuit 307 in the present embodiment comprises a serial/parallel signaling conversion circuit and a level driving circuit, and adopted Philips PCA9560 integrated circuit 305 as serial/parallel signaling conversion circuit, as shown in Figure 3, the serial bus control signal can be exported 4 parallel control signal D0 by PCA9560, D1, D2, D3, in the present embodiment, because control end a, b, c, the level of the needed control signal of d requires high, 4 control signal D0 of PCA9560 output, D1, D2, D3 may not reach control end a, b, c, the level requirement of d, so, in order to guarantee the reliability of logic control signal, these 4 logic control signal D0, D1, D2, D3 also will be transformed into 4 level signal A by a level driving circuit 306, B, C, D, these 4 level signals are controlled control end a respectively, b, c, d, thus realize by the bus signal control memory voltage.
Control the turn-on and turn-off of MOSFET
field effect transistor 1,2,3,4 in the present embodiment by control signal A, B, C, D, thereby make the pressure regulation branch road join or isolate voltage and draw inclined to one side circuit, further change electric current I, finally realize the memory voltage value of 2.2V-2.8V at output terminal g, as shown in table 1 is control signal A, B, C, D corresponding voltage value, A wherein, B, C, D represent the level state of control signal A, B, C, D respectively, " 1 " expression high level, " 0 " expression low level.
?VDI ?MM | ?2.20 | ?2.24 | ?2.28 | ?2.32 | ?2.36 | ?2.40 | ?2.44 | ?2.48 | ?2.52 | ?2.56 | ?2.60 | ?2.64 | ?2.68 | ?2.72 | ?2.76 | ?2.80 |
?A | ?1 | ?1 | ?1 | ?1 | ?1 | ?1 | ?1 | ?1 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 |
?B | ?0 | ?0 | ?0 | ?0 | ?1 | ?1 | ?1 | ?1 | ?0 | ?0 | ?0 | ?0 | ?1 | ?1 | ?1 | ?1 |
?C | ?0 | ?0 | ?1 | ?1 | ?0 | ?0 | ?1 | ?1 | ?0 | ?0 | ?1 | ?1 | ?0 | ?0 | ?1 | ?1 |
?D | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 | ?0 | ?1 |
Table 1
In the present embodiment, as long as because voltage has the variation of 16 steps just can satisfy design requirement, so only adopted 4 pressure regulation branch roads in the present embodiment.If change in voltage has more high-precision requirement, then can increase corresponding pressure regulation branch road, such as, adopt 5 pressure regulation branch roads can obtain the variation of 32 steps, adopt 6 pressure regulation branch roads can obtain the variation of 64 steps, the rest may be inferred.
It is that operating voltage VDIMM to the DDR internal memory draws partially that above-described voltage draws inclined to one side circuit, reference voltage VERF to the DDR internal memory draws inclined to one side voltage to draw inclined to one side circuit and this voltage to draw inclined to one side circuit identical, and only its output terminal g draws inclined to one side reference voltage VERF for the DDR internal memory provides.
Because the folk prescription formula of drawing to the DDR internal memory has two kinds: draw partially in the time of operating voltage and reference voltage and draw respectively partially, so the present invention realizes this two kinds of transformations of drawing the folk prescription formula with a wire jumper circuit, as shown in Figure 4, the wire jumper circuit is made of bleeder circuit 401 tie jumper switches 402; The hot end h of bleeder circuit 401 connects and draws bias-voltage output terminal g to what operating voltage drew that inclined to one side voltage draws inclined to one side circuit 403, and connects the input end of internal memory operating voltage; One stiff end j of the branch pressure side i tie jumper switch 402 of bleeder circuit 401, another stiff end 1 of jumper switch 402 connects and draws bias-voltage output terminal g ' to what reference voltage drew that inclined to one side voltage draws inclined to one side circuit 404, and the movable end k of jumper switch 402 connects the input end of internal memory reference voltage.The ratio of the divider resistance R5 of bleeder circuit 401 and divider resistance R6 resistance can be selected according to the ratio of VDIMM and VERF, in the present embodiment because the value of VERF is 1/2VDIMM, so divider resistance R5 and divider resistance R6 resistance equate.When the movable end k of jumper switch 402 links to each other with the j end, because divider resistance R5 and divider resistance R6 resistance equate, no matter,, thereby draw partially when realizing operating voltage and reference voltage always reference voltage VERF equals 1/2VDIMM so why operating voltage VDIMM is worth; When the movable end k of jumper switch 402 linked to each other with 1 end, operating voltage and reference voltage drew inclined to one side circuit to draw partially by separately voltage respectively on the internal memory, thereby realized drawing respectively partially.
In order to realize controlling the communication between platform and the test platform, the present invention has selected for use simple in structure, and traffic rate meets design needs and and the I of the original internal signal bus of mainboard (SMBUS) interface compatibility
2The C bus is as the means of communication.The transmission of the collection of all data and all control signals all is to pass through I among the present invention
2The C bus realizes.As shown in Figure 5, three I have been used among the present invention
2C equipment: the South Bridge chip group ICH4 (501) in the computer motherboard chipset of control platform, voltage draws the integrated circuit PCA9560 (305) in the inclined to one side circuit 209 on (SUPERI/O) 208 of the observation circuit on the test platform and the test platform.Wherein having only the ICH4 (501) of control platform is main equipment, the Control Software PCA9560 (305) of SMBUS on test platform by ICH4 (501) is on the one hand sent the control signal of regulating memory voltage and from the read back power state information of system of PCA9560 (305), on the other hand, because the present invention utilizes SUPERI/O (208) module to realize that internal memory draws bias-voltage and the data acquisition of drawing inclined to one side mainboard surface temperature, so Control Software can read the magnitude of voltage of internal memory and the temperature value of test macro from the SUPER I/O (208) on the test platform.The I of this master-slave mode
2The design of C bus structure can be so that I
2The total line traffic control of C is simple and be not easy to make mistakes.These I among the present invention
2The function that the mutual relationship of C equipment and each equipment are realized as shown in Figure 5.ICH4 among the figure (501) is I
2Unique main equipment on the C bus can write data from the miscellaneous equipment reading of data or to miscellaneous equipment on one's own initiative.When Control Software need change the memory voltage value, only need write Regulation Control information to PCA9560 (305) and just can by the SMBUS interface of ICH4 (501); When Control Software need read memory voltage and system temperature, can read from SUPER I/O (208), acquisition function by SUPER I/O (208) chip internal, the actual voltage value collection that internal memory after the pressure regulation can be obtained also sends to main control end, in addition, change by the variation of thermistor resistance intrinsic on the mainboard with the mainboard surface temperature, SUPER I/O (208) is with the change in voltage collection and the analysis of this resistance, temperature information is fed back to main control end, thereby realized the close-loop feedback control of voltage and temperature; The power supply of test platform draws inclined to one side status information then can read from PCA9560 (305).
Because control platform and test platform potential range are distant in the practical application, and may there be earthy difference in two power supplys that platform adopted, if adopt I
2The C bus directly couples together two platforms may cause many beyond thought problems, thus specialized designs of the present invention I as shown in Figure 6
2C bus electrical isolation circuit realizes adopting I
2Electric isolation between two platforms of C bus communication.Its basic circuit diagram as shown in Figure 6.Because I
2The C bus is made up of one group of data (DATA) signal wire and one group of clock signal (CLOCK) line, so the signal that needs to isolate mainly is these two kinds of signals.I has only been described among Fig. 6
2The CLOCK line is realized the method for electrical isolation in the C bus, but this circuit is equally applicable to the electrical isolation of DATA line.Since among the present invention to I
2The processing of two groups of signal wires of the DATA of C bus and CLOCK is the same, so following only with a kind of signal wire (for example CLOCK) wherein or be referred to as the implementation method of bus explanation whole isolated circuit.The connection situation of this circuit is seen the electrical isolation circuit 211 of control platform earlier as shown in Figure 6, and it is main resistor network that interface circuit 601 has adopted a resistance bridge that is made of R1~R8, makes the level of bus signals access point can satisfy I
2The requirement of C standard, and the level state of this bus signals can be passed through two output terminals A of resistor network, it is to go in the comparer 602 that B is transferred to the bus logic judging unit effectively, the output terminal C of comparer 602 is connected on the input end that bus driver is one two input or door 603, another input end D of two inputs or door 603 then connects the output of the redundant circuit 604 of comparer 602, this redundant circuit 604 inserts by a zero resistance R9 from the signal access point, the logical relation of the output signal of this redundant circuit 604 and the output signal of comparer 602 is identical, but the mechanism that produces is different, in the time of so just can guaranteeing that any one output signal in comparer 602 or the redundant circuit 604 is made mistakes, also can access correct output signal by two inputs or door 603, thereby guarantee the reliability of circuit.The excitation end that the signal of the output terminal E of this two input or door 603 is used for driving in the test platform end photoelectrical coupler 605 is a light emitting diode 606, and the responder of test platform end photoelectrical coupler 605 is interface circuit 608 outputs of the signal of phototriode 607 outputs by test platform electrical isolation circuit 212.Because electrical isolation circuit of the present invention is symmetrical,, no longer describe in detail here so electrical isolation circuit 211 symmetries of the electrical isolation circuit 212 of test platform and control platform are identical.Because the Primary Component of electrical isolation is a photoelectrical coupler between the control platform of realization interconnection and the test platform, so excitation end in the same photoelectrical coupler and responder must adopt control platform and test platform to power respectively, the excitation end of photoelectrical coupler and the power supply of responder separate, be that its light emitting diode is to be powered by the opposite end, its phototriode is then powered by local terminal, excitation end as test platform end photoelectrical coupler 605 among Fig. 6 is that light emitting diode 606 links to each other with control platform end, by the power supply of control platform end; The responder of test platform end photoelectrical coupler 605 is that phototriode 607 links to each other with the electric power network 610 of test platform end, by electric power network 610 power supplies of test platform end.Though the excitation end 606 of test platform end photoelectrical coupler 605 is by the power supply of control platform end, but owing to realize getting in touch by light between the excitation end 606 of test platform end photoelectrical coupler 605 and the responder 607, so they are not get in touch, thereby just realized the electrical isolation of control platform end and test platform end on electric.
Specifying this electrical isolation circuit below is how to realize I
2The transmission of C bus data.With the CLOCK signal is example, if sense is from the control platform to test platform: when the input CLOCK signal of control platform is high level, the A level point is higher than the B point, the C point is output as high level, this moment redundant resistance R 9 two ends, be that F point and D point are high level, so the E point is a high level, test platform end photoelectrical coupler 605 nothing responses this moment, the output terminal g point of test platform end photoelectrical coupler 605 is a high level, so the output CLOCK signal of test platform is a high level also, thereby realized the transmission of high level CLOCK signal; When CLOCK is low level, the B level point is higher than the A point, the C point is output as low level, this moment, F point and D point were low level, so the E point is a low level, test platform end photoelectrical coupler 605 responses this moment, test platform end photoelectrical coupler 605 output terminal g points are low level, so the output CLOCK signal of test platform is a low level also, thereby realized the transmission of low level CLOCK signal.Because circuit of the present invention is symmetrical, thus when data flow conversely the time principle of work of signal be the same, repeat no more here.
Because memory voltage is adjustable in the native system, so just in case voltage draws inclined to one side circuit malfunction, then may make the internal memory feed circuit too high voltage of output and damage memory bar, so present embodiment has designed the memory voltage overvoltage crowbar, as shown in Figure 7, the input end 3 of comparer 701 meets the operating voltage VDIMM of DDR internal memory, the input end 2 of comparer 701 meets the reference voltage REF of setting, when VDIMM is lower than REF, be that the voltage of the input end 3 of comparer 701 is when being lower than the voltage of input end 2, comparer 701 output terminals 1 output low level, this low level is oppositely exported high level in the back through triode Q1, make triode Q2 be in conducting state, this moment, the control signal PS-ON# of host power supply was identical with the level of the power control signal PWRCTL# that is exported by SUPER I/O, so the switch of computer power supply is by the decision of the state of PWRCTL#, promptly under normal circumstances overvoltage crowbar can not influence the normal operation of computer system; When VDIMM surpasses REF, comparer 701 output terminals 1 output high level, through the reverse back of triode Q1 output low level, make triode Q2 be in nonconducting state, because the existence of voltage VCC, the PS-ON# of computer power supply is in high level, and power supply is closed automatically, thereby has avoided internal memory to damage because of overtension.Simultaneously; between the input end 2 of comparer 701 and output terminal 1, added one-level MOSFET field effect transistor 702 as positive feedback; when VDIMM just surpasses REF; the output terminal 1 of comparer 701 is a high level; 702 conductings of MOSFET field effect transistor; reference voltage REF is 0; at this moment; the level value of comparer 701 output terminals 1 rises to the value of VDIMM at once; so just accelerated the anti-phase speed of triode Q1; thereby realize just carrying out circuit protection when VDIMM has just surpassed REF, accelerated the protection speed of circuit.
Above-mentioned overvoltage crowbar is that the operating voltage of DDR internal memory is carried out overvoltage protection, and the overvoltage crowbar of DDR internal memory reference voltage is the same with this circuit structure, and only the input end 3 of comparer 701 meets the reference voltage VREF of DDR internal memory.
Be illustrated in figure 8 as the process flow diagram that the present invention controls the Control Software of moving on the platform, this Control Software adopts the VC language development, and its main flow process may further comprise the steps:
A, open Control Software, select test operation, promptly be draw simultaneously partially or independently draw inclined to one side.Set test curve;
Whether b, selection call original parameter setting, if, then call in existing parameter setting file, and execution in step e, otherwise, execution in step c;
Described parameter is meant type, magnitude of voltage, temperature value and the corresponding retention time of test curve;
C, selection test curve type.In the present embodiment, this test curve has six types, is respectively:
1. temperature adjustment degree only;
2. only transfer operating voltage VDIMM;
3. only transfer reference voltage VREF;
4. not only temperature adjustment degree but also transfer voltage, but be benchmark with the temperature adjustment degree;
5. not only temperature adjustment degree but also transfer voltage, but be benchmark to transfer operating voltage VDIMM;
6. not only temperature adjustment degree but also transfer voltage, but be benchmark to transfer reference voltage VREF;
D, the voltage of setting adjusting, temperature value and corresponding retention time;
E, according to the parameter value or the parameter setting file setup parameter of above setting, display setting curve;
Whether f, selection preserve the parameter setting, if, then earlier the parameter of setting is saved in the parameter setting file, carry out next step again; Otherwise, directly carry out next step;
G, operation test window;
H, appointment temperature control box control documents;
I, startup temperature control box control program;
J, begin to carry out temperature-adjustment pressure-adjustment test;
K, temperature-adjustment pressure-adjustment end of test (EOT);
L, preservation test result curve;
M, fill in test report.
Because stability and reliability are key points for a real-time control system, in order to guarantee the correctness of reading of data, Control Software all adopts secondary filtering to all data that read, guarantee the accuracy and the stability of data, and all control informations of sending have all been adopted: sent the reliability that control information-retaking of a year or grade control result-comparative result and mode that whether desired value conforms to guarantee the control information of sending.
The above is the composition of whole test platform, and its testing process is as follows:
1. that determine to adopt draws the folk prescription formula, and selects corresponding wire jumper setting on the high low bias test mainboard;
2. the high low bias test mainboard is put into warm and humid control case;
3. the startup main control computer is opened memory environment test software, selects to draw the folk prescription formula accordingly, enters main interface;
4. enter the parameter setting that can directly call behind the main interface in the past, also can carry out the parameter setting voluntarily, content is set comprises that voltage is curve over time, temperature, the time dependent curve of humidity etc., these parameters can be by control platform I
2The C bus transfer is given test platform mainboard I
2The C bus is by this mainboard I
2The C bus offers the PCA9560 chip with parameter, and at this moment corresponding M OSFET field effect transistor will be opened or turn-off accordingly, and the realization correspondent voltage is drawn partially;
5. preserve the parameter setting, enter the test report User Interface, dependence test information is noted;
6. start test, total system will be provided with state by aforementioned parameters and move, and the high low bias test system can move special-purpose memory test program simultaneously, detects whether operate as normal of internal memory, meanwhile, can pass through I between control platform and test platform mainboard
2The C bus is carried out the data feedback, promptly at set time inner control platform motherboard I
2The C bus can be visited test platform I
2C bus (test platform mainboard South Bridge chip), the timely feedback that platform can not get test platform is then controlled in the deadlock if test platform breaks down, and just judges that test macro makes mistakes, and keeps existing state, and record standing state parameter; Perhaps system is turned off.
Whole memory environment test system can be implemented in the operation continuously down of unmanned environment, and after the time of setting finished, system can provide test report automatically, the record whole test process.