CN112068469A - Universal embedded main control board based on DSP28379 - Google Patents
Universal embedded main control board based on DSP28379 Download PDFInfo
- Publication number
- CN112068469A CN112068469A CN202010909161.8A CN202010909161A CN112068469A CN 112068469 A CN112068469 A CN 112068469A CN 202010909161 A CN202010909161 A CN 202010909161A CN 112068469 A CN112068469 A CN 112068469A
- Authority
- CN
- China
- Prior art keywords
- chip
- interface
- pin
- main control
- control board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a general embedded main control board based on a DSP28379, which comprises a DSP28379 chip and an FPGA chip; the DSP28379 chip and the peripheral circuit thereof, and the FPGA chip and the peripheral circuit thereof are integrated on the printed board; the printed board is also provided with a CAN bus interface, an SPI bus interface, an SCI bus interface, a 16-bit differential input A/D interface, a PWM interface, a USB interface and a general I/O module; the DSP chip is electrically connected with the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface and the USB interface, and is electrically connected with the FPGA chip through the EMF bus and the uPP interface; the general I/O module is electrically connected with the FPGA chip; the printed board is also provided with an FPGA configuration chip and an emmc chip, and the FPGA configuration chip and the emmc chip are electrically connected with the FPGA chip; the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface, the USB interface and the general I/O module are respectively and electrically connected with the connector.
Description
Technical Field
The invention relates to the technical field of industrial control, in particular to a universal embedded main control board based on a DSP 28379.
Background
With the development of technology, DSP digital signal processors are more and more widely used, and more attention is paid. The DSP is a common processor in the field of industrial control and information processing, and a variety of minimum application systems are derived along with the diversity of application systems. The DSP is redesigned as a nonstandard module according to different DSP series or when being matched with different coprocessors, thereby increasing the development difficulty and the time cost.
The currently commonly used single-controller processors are mainly DSP and ARM series controllers of TI company, wherein the DSP series includes C3x, C2000 and C6000 series, and the ARM series is mainly Hercules series controllers based on ARM7 kernel. Selected, according to the principle, mainly in the above series. Wherein C3x is the first floating point DSP of TI company, the performance is lower, and no new product is launched at present. The C6000 series DSP has high performance and high running speed, is suitable for occasions with large calculation amount, such as broadband networks, image processing, radars, navigation operation and the like, but has no relevant peripheral interfaces and memories, needs hardware for external expansion, is relatively complex to realize a single computer, and has high cost.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a universal embedded main control board based on a DSP28379, and aims to solve the problems of single application, inconvenience in secondary development and the like of a diversified design based on a DSP28FXX series.
The invention provides a general embedded main control board based on a DSP28379, which is characterized by comprising a DSP28379 chip and an FPGA chip; the DSP28379 chip and the peripheral circuit thereof, and the FPGA chip and the peripheral circuit thereof are integrated on the printed board; the printed board is also provided with a CAN bus interface, an SPI bus interface, an SCI bus interface, a 16-bit differential input A/D interface, a PWM interface, a USB interface and a general I/O module; the DSP chip is electrically connected with the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface and the USB interface, and is electrically connected with the FPGA chip through the EMF bus and the uPP interface; the general I/O module is electrically connected with the FPGA chip; the printed board is also provided with an FPGA configuration chip and an emmc chip, and the FPGA configuration chip and the emmc chip are electrically connected with the FPGA chip; the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface, the USB interface and the general I/O module are respectively and electrically connected with the connector.
In the above technical solution, the peripheral circuit of the DSP28379 chip includes a BOOT selection circuit, a clock circuit, a JTAG interface circuit, an a/D interface circuit, a reset circuit, and a bypass capacitor.
In the above technical solution, the peripheral circuit of the FPGA chip includes a configuration dedicated pin circuit, a multifunctional configurable pin circuit, and a power supply pin circuit.
In the technical scheme, the power supply management module comprises an LTM chip and a TPS chip; the power output end of the connector is respectively and electrically connected with the power input ends of the LTM chip and the TPS chip, the power output end of the LTM chip is output in four ways and respectively supplies power to a core chip of the DSP chip, a driving I/O circuit, a core chip of the FPGA chip, an auxiliary circuit, an RAM, the driving I/O circuit and a peripheral circuit of the FPGA chip; and the power output end of the TPS chip outputs in a single way to supply power to a peripheral circuit of the FPGA chip.
In the technical scheme, the CAN bus interface is directly led to the connector and is used for realizing the expansion of the CAN communication interface by matching with the CAN isolation driver during secondary development; the SPI interface is directly led to the connector and is used for matching corresponding contents of the memory, the CAN controller and the A/D controller of the SPI interface during secondary development; the SCI interface is directly led to the connector and is used for matching with corresponding contents of extension of the RS422 isolation driver and the RS485 isolation driver during secondary development; the I2C interface leads directly to the connector; the USB interface is directly led to the connector and is used for being matched with the USB controller to expand the USB2.0 interface during secondary development; the PWM interface leads directly to the connector; the 16-bit A/D acquisition channel is directly led to the connector and is used for directly accessing the analog signal after voltage division during secondary development; the EMIF1 bus leads to connectors for additional expansion through the EMIF bus at second development.
In the technical scheme, in the JTAG interface circuit, a TRST pin is used as a test restart pin and is connected with a pull-down resistor and a filter capacitor; pins of EMUO and EMU1 are used as simulation pins and connected with a pull-up resistor and a filter capacitor; the TMS pin is a test mode selection pin, the TDI pin is a test data input pin, the TCK pin and the TCKRET pin are test clock pins, and the TMS pin, the TDI pin and the TCKRET pin are connected with an output level of the LTM chip through pull-up resistors; the PD pin is a detection pin and is connected with the output level of the LTM chip through a resistor so as to check whether the simulator is connected or not.
In the technical scheme, the power-on time sequence of the LTM chip is controlled by the cooperation of the RUN pin and the PGOOD pin; an external resistor of a FB4 pin of the LTM chip obtains a 1V level, an external resistor of a FB3 pin obtains a 1.2V level, an external resistor of a FB2 pin obtains a 1.8V level, and an external resistor of a FB1 pin obtains a 3.3V level; the LTM chip controls the output of each path through the RUN pins and realizes the time sequence output of various levels through the PGOOD pins; the first output of the 4 paths of outputs of the LTM chip is 1V, the second output of the LTM chip is 1.8V, the third output of the LTM chip is 1.2V, and the fourth output of the LTM chip is 3.3V.
In the technical scheme, the power-on sequence of the TPS chip is controlled by the slow start pin SS, and the output voltage of the TPS chip is 2.5V.
Peripheral circuits of the DSP28379 and peripheral circuits of the FPGA are integrated on a 84mm multiplied by 54mm printed board, mounting holes of 2.5mm are arranged at four corners, and functional pins of the peripheral circuits are led out of a main control board through a board-level connector; having rich peripherals: 2 CAN bus interface, 3 SPI interface, 4 SCI interface, 12A/D interface with 16 bits difference input, 24 PWM interface, 200I/O interface for use, and large capacity storage. The universal embedded main control board provided by the invention has smaller volume and is convenient to install, and can be fixed by a stud when the bottom plate is installed. The embedded main control board has abundant peripheral communication interfaces, is applied to different communication systems, and has a wide application range. The embedded main control board provided by the invention is provided with a 16-bit differential input A/D interface, a 24-path PWM interface and a 200-path general I/O, comprises an EMIF bus and a network port reserved level interface, and has infinite possibility of function expansion. The embedded main control board of the invention has 32Gb data storage space, considerable storage capacity and convenient storage of key parameters.
In summary, the invention can be applied to various industrial control single machines or systems, and has the characteristics of more communication types, more A/D acquisition channels, more PWM interfaces, more general I/O, considerable storage capacity, small volume, convenience in expanding functions and the like.
Drawings
FIG. 1 is a block diagram of the system of the present invention
FIG. 2 is a circuit diagram of the JTAG interface of the present invention
FIG. 3 is a diagram of a power network of the present invention
FIG. 4 is a circuit diagram of the LTM4644 of the present invention
FIG. 5 is a circuit diagram of the TPS74401 of the present invention;
FIG. 6 is a BOOT mode setting circuit diagram of the present invention;
FIG. 7 is a clock setting circuit diagram of the present invention;
FIG. 8 is a circuit diagram of the A/D interface of the present invention;
FIG. 9 is a reset circuit of the present invention;
FIG. 10 is a circuit diagram of the peripheral design of the configuration specific pin according to the present invention;
FIG. 11 is a circuit diagram of the multi-function configurable pin peripheral design of the present invention;
FIG. 12 is a circuit diagram of the FPGA configuration of the present invention;
FIG. 13 is a circuit diagram of the DSP power supply design of the present invention;
FIG. 14 is a circuit diagram of the FPGA power supply design of the present invention.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
As shown in fig. 1, the present invention provides a general embedded main control board based on DSP28379, which is characterized in that it includes a DSP28379 chip and an FPGA chip; the DSP28379 chip and the peripheral circuit thereof, and the FPGA chip and the peripheral circuit thereof are integrated on the printed board; the printed board is also provided with 2 paths of CAN bus interfaces, 3 paths of SPI bus interfaces, 4 paths of SCI bus interfaces, 12 paths of 16-bit differential input A/D interfaces, 24 paths of PWM interfaces, a USB interface and 200 paths of general I/O modules; the DSP chip is electrically connected with the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface and the USB interface, and is electrically connected with the FPGA chip through the EMF bus and the uPP interface; the general I/O module is electrically connected with the FPGA chip; the printed board is also provided with an FPGA configuration chip and an emmc chip, and the FPGA configuration chip and the emmc chip are electrically connected with the FPGA chip; the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface, the USB interface and the general I/O module are respectively and electrically connected with the connector.
The TMS320F28379D is selected by a DSP chip which is a powerful 32-bit floating point microcontroller unit (MCU) and supports a novel dual-core C28x architecture. TMS320F28379D supports up to 1MB (512KW) of on-board flash memory (including Error Correction Codes (ECC)), up to 204KB (102KW) of SRAM, and also provides two 128-bit secure areas on each CPU for code protection. Four independent 16-bit ADCs are integrated on the MCU, so that a plurality of analog signals can be accurately and efficiently managed, and the system throughput is finally improved. The use of a novel sigma-delta filter module (SDFM) in conjunction with a sigma-delta modulator can enable isolated shunt measurements. Other peripherals include DAC, PWM, eCAPs, eQEP, SCI/UART, I2C, SPI, McBSP, EMIF, CAN, USB2.0, etc. peripherals and a novel uPP interface. uPP interface is C2000TMA new feature of the MCU supports high speed parallel connections with FPGAs or other processors with similar uPP interfaces. The USB2.0 port with MAC and PHY enables users to easily add Universal Serial Bus (USB) connectivity functionality to their applications.
In order to reduce the volume of the embedded main control board, a TMS320F28379DZWTS label device is selected as a DSP chip, the main peripheral design of a DSP processor comprises BOOT selection, clock design, JTAG port design, A/D interface design, reset circuit design, bypass capacitor and the like, and the peripheral design influences the normal operation of the DSP.
BOOT selection: as shown in fig. 6, the BOOT pin setting affects the software loading mode of the DSP, the GPIO84 pin needs to be pulled up by a 4.7k Ω resistor for the BOOT mode selection pin 0, the GPIO72 pin needs to be pulled up by a 4.7k Ω resistor for the BOOT mode selection pin 1, and the program loading is in a BOOT mode and is loaded from the internal FLASH; besides, pins of GPIO85, GPIO86 and GPIO87 need to be pulled up by 4.7k omega resistors.
Clock design: as shown in fig. 7, the GPIO133 pin is an AUXCLKIN clock input pin, and CAN be externally connected with a 32MHz active crystal oscillator, and is used for a USB module or a CAN module; the pins X1 and X2 are clock input pins of the CPU, the embedded main control board does not use an internal clock, the pin X1 is externally connected with a 20MHz active crystal oscillator, and the pin X2 is suspended.
JTAG design: the JTAG port design adopts a 14-pin simulation interface design, a JTAG interface circuit of the DSP is shown in figure 2, wherein a TRST pin is a test restart pin, and is required to be connected with 2.2k omega resistor pull-down and 1uF capacitor filtering, so that the TRST pin is prevented from receiving interference under high noise; pins EMUO and EMU1 are simulation pins, and are required to be connected with 4.7k omega resistor pull-up and 1uF capacitor filtering; the TMS pin is a test mode selection pin, the TDI pin is a test data input pin, the TCK pin and the TCKRET pin are test clock pins, and a 4.7k omega resistor is required to be connected for pulling up; the PD pin is a detection pin and needs to be connected with a 100 omega resistor to be connected with a 3.3V level, and whether the simulator is connected or not is checked.
Designing an A/D interface: as shown in FIG. 8, the A/D of the embedded main control board adopts 16-bit mode, so VREFHIA、VREFHIB、VREFHIC、VREFHIDThe analog power supply input needs an external 22uF capacitor, and the PCB is arranged as close to the pin position as possible.
Designing a reset circuit: as shown in fig. 9, the XRS pin is a reset pin of the DSP, the embedded main control board pulls up the XRS pin with a 10k Ω resistor, and the 0.1uF capacitor is grounded, thereby implementing the function of the reset circuit.
A bypass capacitor: as shown in fig. 13, the VDD pin is a 1.2V core voltage power interface, each pin needs to be connected to a 0.1uF capacitor, and every six pins are grouped to be connected to a 10uF capacitor; VDDIO pins are 3.3V and are IO voltage power interfaces, and each pin needs to be connected with a 0.1uF capacitor; VDDA is the A/D power interface, and each pin needs to be connected with a 2.2uF capacitor. In addition to the above contents, the interface of the embedded main control board EMIF1, the interface of the EMIF2 and the interface of the embedded main control board uPP are all led to the FPGA for information interaction between the DSP and the FPGA.
2-channel CAN bus interfaces of the embedded main control board DSP are directly led to the embedded main control board connector, and CAN be matched with a CAN isolation driver to realize the expansion of a CAN communication interface during secondary development; the 3-path SPI interface is directly led to the embedded main control board connector, and corresponding contents CAN be expanded by matching with a memory, a CAN controller, an A/D controller and the like of the SPI interface during secondary development; the 4 paths of SCI interfaces are directly led to the embedded main control board connector, and corresponding contents can be expanded by matching with RS422 isolation drive, RS485 isolation drive and the like during secondary development; the 2-path I2C interface is directly led to the embedded main control board connector, so that secondary development is facilitated; the 1-channel USB interface is directly led to the embedded main control board connector, and can be matched with a USB controller to expand a USB2.0 interface during secondary development; the 24 paths of PWM interfaces are directly led to the embedded main control board connector, so that secondary development is facilitated; the 24 paths of 16-bit A/D acquisition channels are directly led to the embedded main control board connector, and analog signals after voltage division are directly accessed during secondary development; in addition to the above, the EMIF1 bus is also introduced to the embedded main control board connector, and other contents are extended through the EMIF bus during secondary development, so that the application of the embedded main control board is wider and has infinite possibility.
FPGA chip selection Kintex of embedded main control board
And the 7-series XC7K325T-2FBG676 serves as an FPGA chip of the embedded main control board. XC7K325T-2FBG676 is a programmable logic device, has abundant internal programming resources, comprises 840 digital signal processors, 445 BRAMs with 36Kb, 326080 logic units, 10 CMTs, 1 PCIE2.1, 16 GTX and other programmable resources, can realize the applications of high-performance digital signal processing, large-capacity logic operation and the like, and has high-bandwidth data throughput capability.
The peripheral circuit outside the special pin peripheral design of FPGA, FPGA configuration circuit design, multi-functional multiplexing configurable pin mainly includes: configuration design, power supply pin peripheral design and the like, and the pin design influences the function and normal operation of the FPGA.
Configuring a special pin periphery design: as shown in fig. 10, CCLK _0 is a configuration clock pin, which is pulled up by a 330 Ω resistor and pulled down by a 1k Ω resistor as an output clock in the main mode in the embedded main control board, and the clock signal is led to the CLK pin of the SPI FLASH of the FPGA configuration chip; the CFGBVS _0 pin selects a pre-configured I/O standard type for the special and multifunctional configuration groups 0, 14 and 15, and is pulled up by a 4.7k omega resistor due to the 3.3V level when the voltage of the bank0, 14 and 15 of the embedded main control board is applied; the DXP _0 and DXN _0 pins are temperature detection diode pins, and because the embedded main control board does not need to access a thermal diode, the pins are pulled down by a 2.2k omega resistor; when the DONE _ O pin is at a high level, the configuration is successfully completed, and the pin in the embedded main control board is pulled up by a 330 omega resistor; when the INT _ B _0 pin is at a low level, the initialization of a configuration memory is represented, and the pin in the embedded main control board is pulled up by adopting a 4.7k omega resistor; when the PROGRAM _ B _0 pin is at low level, the asynchronous reset is represented to configuration logic, and the pin in the embedded main control board is pulled up by adopting a 4.7k omega resistor; the VP _0 pin and the VN _0 pin are XADC special differential analog inputs, and the embedded main control board is connected with a 33 omega matching resistor and then suspended; TCK _0(JTAG clock), TDI _0(JTAG data input), TDO (JTAG data output) and TMS _0(JTAG mode selection) are JTAG simulation interfaces, the embedded main control board adopts 14-pin simulation interface design, and pins TCK _0, TDI _0 and TMS _0 are pulled up by 10k omega resistors; the pins M0_0, M1_0, and M2_0 are configuration mode selection pins, and the embedded main control board loads software in a main mode, so the pins M1_0 and M2_0 are pulled down by 1k Ω resistors, and the pin M0_0 is pulled up by 1k Ω resistors.
And (3) designing the periphery of the multifunctional configurable pin: as shown in fig. 11, ADV _ B (BPI FLASH address valid output (active low)), FOE _ B (BPI FLASH output enable (active low)), FWE _ B (BPI FLASH write enable (active low)), DOUT _ CSO _ B (through daisy chain configuration data output), RS0, RS1 (modify select output) pins are all pulled up with 4.7k Ω resistors in the embedded main control board; pins of PUDC _ B, CSI _ B (select MAP chip select input (active low)), RDWR _ B (select MAP data bus direction control signal for reading or writing) are pulled down by 2.2k omega resistance in the embedded main control board; an EMCCLK (external main configuration clock) pin, and the embedded main control board adopts an external 50MHz active crystal oscillator as an input clock of the FPGA. FCS _ B (SPI FLASH chip selection (low level is effective)), MOSI (SPI bus output), DIN _14(SPI bus input), D02_14 and D03_14 pins are connected to control pins of an embedded main control board FPGA configuration chip SPI FLASH after passing through 33 omega matching resistors.
And (3) peripheral design of a power supply pin: as shown in fig. 14, VCCINT pins of the FPGA chip are 1.0V power pins of the internal core logic, a bypass capacitor of each VCCINT pin in the embedded main control board is 0.1uF, and every four VCCINT pins are 1 to be connected with 10uF capacitors; the VCCAUX pins are 1.8V auxiliary circuit power supplies, the bypass capacitance of each VCCAUX pin in the embedded main control board is 0.1uF, and every four VCCAUX pins are 1 to be connected with 10uF capacitance; VCCO _ # is a power supply pin of a single bank output driver, 3.3V power supplies are adopted for bank0, bank13, bank14, bank15 and bank16 in the embedded main control board, 2.5V power supplies are adopted for bank12, 1.8V power supplies are adopted for bank32, bank33 and bank34, and each VCCO _ # in the embedded main control board needs to be connected with a 0.1uF capacitor.
The FPGA configuration circuit: as shown in fig. 12, the FPGA configuration chip adopts a 128M SPI FLASH, and when designed, a bus configuration mode, a data bus loading mode, or a serial bus loading mode may be selected, the embedded main control board adopts a serial bus loading mode, and all pins except a power supply are pulled up by using a 4.7k Ω resistor.
As shown in fig. 14, the embedded main control board guides I/O interfaces of bank12, bank13, bank14, bank15, and bank16 to the embedded main control board connector, wherein the I/O level of bank12 is 2.5V, and is reserved for subsequent port expansion; the I/O level of the bank13, the bank14, the bank15 and the bank16 is 3.3V and can be used as general I/O; and FPGA is not led out from the I/O of other banks.
The embedded main control board expands a 32Gb data storage space through an eMMC chip MTFC32GAKAEDQ-AIT, the working voltage is 3.3V, the working voltage is 1.8V, 8-bit buses read and write, the write rate is 20MB/s, and the read rate is 44 MB/s.
The input voltage of the embedded main control board is 5V. The power network diagram of the embedded main control board is shown in fig. 3, the main voltages of the power network diagram are 1V, 1.2V, 1.8V, 2.5V and 3.3V, and the power network diagram mainly supplies power to the DSP and the FGPA; the main TMS320F28379DPTPT core voltage is 1.2VDC, and the IO voltage is 3.3 VDC. The core voltage of the circuit is 1.2VDC maximum current 495mA, and the IO voltage is 3.3VDC maximum current (30+20+40) mA. XC7K325T-2FBG676 core voltage 1.0VDC, auxiliary voltage and RAM voltage 1.8VDC, IO voltage 3.3 VDC. The core voltage is 1.0VDC maximum current 1593mA, the auxiliary voltage is 1.8VDC maximum current 195mA, the RAM voltage is 1.8VDC typical current 71mA, and the IO voltage is 3.3VDC maximum current 600 mA. The embedded main control board adopts LTM4644MPY and TPS 74401.
LTM4644MPY has an input voltage range of 4V to 14V and an output voltage range of 0.6V to 5.5V. Four paths of outputs respectively outputting 1.0V, 1.2V, 1.8V and 3.3V and a single-path load current 4A, and the power-on sequence can be controlled by matching the RUN pin and the PGOOD pin, and a circuit diagram is shown in FIG. 4. The FB4 pin of the LTM4644MPY is externally connected with a 90.9k omega resistor to obtain a 1V level, the FB3 pin is externally connected with a 60.4k omega resistor to obtain a 1.2V level, the FB2 pin is externally connected with a 30.1k omega resistor to obtain a 1.8V level, and the FB1 pin is externally connected with a 13.3k omega resistor to obtain a 3.3V level; the output of each path is controlled through the RUN pin, and the time sequence output of various levels is realized through the PGOOD pin; the first output of 1V, the second output of 1.8V, the third output of 1.2V and the fourth output of 3.3V are set in the embedded main control board.
The TPS74401 has an input voltage range of 1.1VDA to 5.5VDC, single output, an output voltage range of 0.8VDC to 3.6VDC and a load current of 3A. The output voltage is set to 2.5V, the power-on sequence is controlled by the slow start pin SS, and the circuit diagram is shown in fig. 5.
The embedded main control board adopts an industrial grade B2B connector for the external connector, and the signal integrity is ensured. The connector is 3mm in height, 22.7mm multiplied by 5.20mm in length multiplied by width, 80 pins are provided, the embedded main control board is used for 4 pins, and 2 male seats are arranged side by side and 2 female seats are arranged side by side for improving the fault tolerance rate of assembly.
The universal embedded main control board based on the DSP28379 has the characteristics of more communication types, more A/D acquisition channels, more PWM interfaces, more universal I/O, considerable storage capacity, small size, convenience in function expansion and the like.
Details not described in this specification are within the skill of the art that are well known to those skilled in the art.
Claims (8)
1. A general embedded main control board based on DSP28379 is characterized by comprising a DSP28379 chip and an FPGA chip; the DSP28379 chip and the peripheral circuit thereof, and the FPGA chip and the peripheral circuit thereof are integrated on the printed board; the printed board is also provided with a CAN bus interface, an SPI bus interface, an SCI bus interface, a 16-bit differential input A/D interface, a PWM interface, a USB interface and a general I/O module; the DSP chip is electrically connected with the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface and the USB interface, and is electrically connected with the FPGA chip through the EMF bus and the uPP interface; the general I/O module is electrically connected with the FPGA chip; the printed board is also provided with an FPGA configuration chip and an emmc chip, and the FPGA configuration chip and the emmc chip are electrically connected with the FPGA chip; the CAN bus interface, the SPI bus interface, the SCI bus interface, the 16-bit differential input A/D interface, the PWM interface, the USB interface and the general I/O module are respectively and electrically connected with the connector.
2. The DSP 28379-based universal embedded main control board according to claim 1, wherein the peripheral circuits of the DSP28379 chip include a BOOT selection circuit, a clock circuit, a JTAG interface circuit, an A/D interface circuit, a reset circuit, and a bypass capacitor.
3. The DSP 28379-based universal embedded main control board of claim 2, wherein peripheral circuits of the FPGA chip include configuration dedicated pin circuits, multi-function configurable pin circuits, and power supply pin circuits.
4. The DSP 28379-based universal embedded main control board according to claim 3, further comprising a power management module, wherein the power management module comprises an LTM chip and a TPS chip; the power output end of the connector is respectively and electrically connected with the power input ends of the LTM chip and the TPS chip, the power output end of the LTM chip is output in four ways and respectively supplies power to a core chip of the DSP chip, a driving I/O circuit, a core chip of the FPGA chip, an auxiliary circuit, an RAM, the driving I/O circuit and a peripheral circuit of the FPGA chip; and the power output end of the TPS chip outputs in a single way to supply power to a peripheral circuit of the FPGA chip.
5. The DSP 28379-based universal embedded main control board according to claim 4, wherein the CAN bus interface is directly led to the connector, and is used for realizing the expansion of a CAN communication interface by matching with a CAN isolation driver during secondary development; the SPI interface is directly led to the connector and is used for matching corresponding contents of the memory, the CAN controller and the A/D controller of the SPI interface during secondary development; the SCI interface is directly led to the connector and is used for matching with corresponding contents of extension of the RS422 isolation driver and the RS485 isolation driver during secondary development; the I2C interface leads directly to the connector; the USB interface is directly led to the connector and is used for being matched with the USB controller to expand the USB2.0 interface during secondary development; the PWM interface leads directly to the connector; the 16-bit A/D acquisition channel is directly led to the connector and is used for directly accessing the analog signal after voltage division during secondary development; the EMIF1 bus leads to connectors for additional expansion through the EMIF bus at second development.
6. The universal embedded main control board based on DSP28379 of claim 5, wherein in said JTAG interface circuit, TRST pin is used as test restart pin, and pull-down resistor and filter capacitor are connected; pins of EMUO and EMU1 are used as simulation pins and connected with a pull-up resistor and a filter capacitor; the TMS pin is a test mode selection pin, the TDI pin is a test data input pin, the TCK pin and the TCKRET pin are test clock pins, and the TMS pin, the TDI pin and the TCKRET pin are connected with an output level of the LTM chip through pull-up resistors; the PD pin is a detection pin and is connected with the output level of the LTM chip through a resistor so as to check whether the simulator is connected or not.
7. The DSP 28379-based universal embedded main control board according to claim 6, wherein the power-on timing of the LTM chip is controlled by cooperation of its RUN pin and PGOOD pin; an external resistor of a FB4 pin of the LTM chip obtains a 1V level, an external resistor of a FB3 pin obtains a 1.2V level, an external resistor of a FB2 pin obtains a 1.8V level, and an external resistor of a FB1 pin obtains a 3.3V level; the LTM chip controls the output of each path through the RUN pins and realizes the time sequence output of various levels through the PGOOD pins; the first output of the 4 paths of outputs of the LTM chip is 1V, the second output of the LTM chip is 1.8V, the third output of the LTM chip is 1.2V, and the fourth output of the LTM chip is 3.3V.
8. The DSP 28379-based universal embedded main control board according to claim 7, wherein the power-on timing sequence of the TPS chip is controlled by a slow start pin SS, and the output voltage is 2.5V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010909161.8A CN112068469A (en) | 2020-09-02 | 2020-09-02 | Universal embedded main control board based on DSP28379 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010909161.8A CN112068469A (en) | 2020-09-02 | 2020-09-02 | Universal embedded main control board based on DSP28379 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112068469A true CN112068469A (en) | 2020-12-11 |
Family
ID=73666235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010909161.8A Pending CN112068469A (en) | 2020-09-02 | 2020-09-02 | Universal embedded main control board based on DSP28379 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112068469A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112988271A (en) * | 2021-03-19 | 2021-06-18 | 四川航天神坤科技有限公司 | System and method for dynamically configuring FPGA (field programmable Gate array) in passive SelectMAP (selectable MAP) mode |
| CN113760363A (en) * | 2021-08-18 | 2021-12-07 | 珠海妙存科技有限公司 | PAD multiplexing circuit, MCU and control method |
| CN114077217A (en) * | 2021-11-30 | 2022-02-22 | 重庆华渝电气集团有限公司 | Navigation computer board based on FPGA and DSP |
| CN114120741A (en) * | 2021-11-25 | 2022-03-01 | 安徽芒课教育科技有限公司 | Embedded real device of instructing of three cores |
| CN114137307A (en) * | 2021-09-30 | 2022-03-04 | 湖北三江航天万峰科技发展有限公司 | TMS320F 28335-based insulation resistance detection board |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100759108B1 (en) * | 2006-07-10 | 2007-09-19 | 송암시스콤 주식회사 | System and method for management of measuring instrument based on rfid |
| GB2439579A (en) * | 2006-06-30 | 2008-01-02 | Advanced Risc Mach Ltd | Target device programmer |
| CN103178695A (en) * | 2013-03-14 | 2013-06-26 | 华北电力大学 | Universal variable current control platform based on DSP plus FPGA (digital signal processor plus filed programmable gate array) |
| CN203135699U (en) * | 2013-03-14 | 2013-08-14 | 华北电力大学 | Universal variable flow control platform based on DSP+FPGA |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN204667393U (en) * | 2015-05-18 | 2015-09-23 | 南车株洲电力机车研究所有限公司 | A kind of multi-chip data interaction device based on FPGA and Upp interface |
| CN204926079U (en) * | 2015-08-03 | 2015-12-30 | 中国计量学院 | Control integrated circuit board based on DSP and FPGA |
| CN205193522U (en) * | 2015-12-12 | 2016-04-27 | 中国电子科技集团公司第二十七研究所 | Can cascaded ripples accuse machine and quick -witted system of ripples accuse |
| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
| CN110794234A (en) * | 2019-10-31 | 2020-02-14 | 北京交通大学 | PWM converter direct current support capacitor residual life online monitoring system and method |
| CN210694078U (en) * | 2019-09-04 | 2020-06-05 | 四川赛狄信息技术股份公司 | Information processing circuit based on FPGA and DSP |
| CN211293103U (en) * | 2019-10-31 | 2020-08-18 | 北京交通大学 | PWM converter direct current supports electric capacity remaining life on-line monitoring system |
-
2020
- 2020-09-02 CN CN202010909161.8A patent/CN112068469A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2439579A (en) * | 2006-06-30 | 2008-01-02 | Advanced Risc Mach Ltd | Target device programmer |
| KR100759108B1 (en) * | 2006-07-10 | 2007-09-19 | 송암시스콤 주식회사 | System and method for management of measuring instrument based on rfid |
| CN103178695A (en) * | 2013-03-14 | 2013-06-26 | 华北电力大学 | Universal variable current control platform based on DSP plus FPGA (digital signal processor plus filed programmable gate array) |
| CN203135699U (en) * | 2013-03-14 | 2013-08-14 | 华北电力大学 | Universal variable flow control platform based on DSP+FPGA |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN204667393U (en) * | 2015-05-18 | 2015-09-23 | 南车株洲电力机车研究所有限公司 | A kind of multi-chip data interaction device based on FPGA and Upp interface |
| CN204926079U (en) * | 2015-08-03 | 2015-12-30 | 中国计量学院 | Control integrated circuit board based on DSP and FPGA |
| CN205193522U (en) * | 2015-12-12 | 2016-04-27 | 中国电子科技集团公司第二十七研究所 | Can cascaded ripples accuse machine and quick -witted system of ripples accuse |
| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
| CN210694078U (en) * | 2019-09-04 | 2020-06-05 | 四川赛狄信息技术股份公司 | Information processing circuit based on FPGA and DSP |
| CN110794234A (en) * | 2019-10-31 | 2020-02-14 | 北京交通大学 | PWM converter direct current support capacitor residual life online monitoring system and method |
| CN211293103U (en) * | 2019-10-31 | 2020-08-18 | 北京交通大学 | PWM converter direct current supports electric capacity remaining life on-line monitoring system |
Non-Patent Citations (1)
| Title |
|---|
| ANALOG-DEVICES-LINEAR-TECHNOLOGY: "Regulator with Configurable 4A Output Array Quad DC/DC μModule", 《电子工程世界》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112988271A (en) * | 2021-03-19 | 2021-06-18 | 四川航天神坤科技有限公司 | System and method for dynamically configuring FPGA (field programmable Gate array) in passive SelectMAP (selectable MAP) mode |
| CN113760363A (en) * | 2021-08-18 | 2021-12-07 | 珠海妙存科技有限公司 | PAD multiplexing circuit, MCU and control method |
| CN113760363B (en) * | 2021-08-18 | 2022-09-30 | 珠海妙存科技有限公司 | PAD multiplexing circuit, MCU and control method |
| CN114137307A (en) * | 2021-09-30 | 2022-03-04 | 湖北三江航天万峰科技发展有限公司 | TMS320F 28335-based insulation resistance detection board |
| CN114120741A (en) * | 2021-11-25 | 2022-03-01 | 安徽芒课教育科技有限公司 | Embedded real device of instructing of three cores |
| CN114077217A (en) * | 2021-11-30 | 2022-02-22 | 重庆华渝电气集团有限公司 | Navigation computer board based on FPGA and DSP |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112068469A (en) | Universal embedded main control board based on DSP28379 | |
| EP2472409B1 (en) | Input-output module, and method for extending a memory interface for input-output operations | |
| US7762818B2 (en) | Multi-function module | |
| US8572297B2 (en) | Programmable system-on-chip hub | |
| US9058257B2 (en) | Persistent block storage attached to memory bus | |
| CN113341814B (en) | Unmanned aerial vehicle flight control computer evaluation system | |
| US20140304445A1 (en) | Memory bus loading and conditioning module | |
| CN102650975A (en) | Realization method of I2C bus for multi-hardware platform FT server | |
| EP0880142B1 (en) | Dynamic random access memory (DRAM) having variable configuration for data processing system and corresponding expansion support for the interleaved-block configuration thereof | |
| CN114564428A (en) | Airborne electronic equipment I/O port expansion system | |
| CN105045335A (en) | FPGA information processing system with embedded 8051IP core | |
| CN208907999U (en) | A kind of novel Raid buckle | |
| US8009475B2 (en) | Device selection circuit and method | |
| US10831963B1 (en) | Apparatus and method of parallel architecture for NVDIMM | |
| CN116502594A (en) | Server safety management module and server | |
| CN110647481A (en) | Conversion board card and hard disk interface device | |
| CN114416455A (en) | Novel CPU detection device of multi-functional application | |
| CN211604095U (en) | SATA raid card | |
| CN104965468B (en) | A kind of common interface module suitable for the multi-functional acquisition control devices of CPCI | |
| CN102446132B (en) | Method and device for performing board-level management by simulating local bus | |
| US7707350B2 (en) | Bus interconnect switching mechanism | |
| CN115081568B (en) | Server firmware storage system and method based on RFID | |
| Doering et al. | Monitoring and controlling system for microservers | |
| CN221650930U (en) | Mainboard and computer based on Loongson 3A6000 processor | |
| CN221056926U (en) | A serial port conversion module for self-powered USB equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201211 |