CN1570894A - Data isolation switching transmission method based on extended data bus of embedded system - Google Patents
Data isolation switching transmission method based on extended data bus of embedded system Download PDFInfo
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- CN1570894A CN1570894A CNA2004100180180A CN200410018018A CN1570894A CN 1570894 A CN1570894 A CN 1570894A CN A2004100180180 A CNA2004100180180 A CN A2004100180180A CN 200410018018 A CN200410018018 A CN 200410018018A CN 1570894 A CN1570894 A CN 1570894A
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Abstract
It's a kind of data isolation switch transmission method based on embedded system expansion data bus. Two 32-bit expansion data bus of embedded host connect to the isolation switch unit after LVDS signal switch. The isolation switch unit comprises LVDS signal switch circuit, isolation switch controller and SRAM. After LVDS signal switch, a expansion data bus of host connects to isolation switch hardware unit, then resumes the expansion data bus signal through the LVDS signal switch circuit, and connects with the SRAM of isolation storage. The transmission channel is controlled by the isolation switch controller, which's CPLD can trigger the embedded host system by sending the interruption responding signal, and write and read the SRAM storage real-time. There is only one host system to read and write the SRAM storage at any time. And by managing and organizing SRAM storage, it can realize high speed, real time, bi-directional data switch transmission in embedded bi-hosts system that equipped with expansion data bus interface.
Description
Technical field
The present invention relates to a kind of data isolation switched transmission method, specifically is a kind of data isolation switched transmission method based on embedded system growth data bus, is used for network data exchange, field of information security technology.
Background technology
Current method of carrying out security protection at network boundary mainly is to adopt firewall technology.Fire wall monitors the flow of turnover network by software and network is connected and controls.Because the firewall hardware system has adopted the mode of single Bastion Host, in case therefore software systems are captured by the hacker, then firewall system just performs practically no function.Nineteen ninety-five has proposed a kind of inter-network data by people such as Russian Ry Jones isolates and the technology that exchanges, and is called " Airgap ", and its English original meaning is meant the slit that is used to isolate that air forms.When the state that is used to describe between the network, be meant the disconnection of network link layer.After this, people generally use network that English " GAP " (former meaning " gap ") refers to make two or more by specialized hardware carrying out the secure data transmission between the network and the technology of resource sharing under the disconnected situation.Its basic demand is: the Internet Protocol of cutting off between the network (TCP/IP) connects, and decomposition or reorganization TCP/IP packet also carry out safe examination, then destination host are on one side produced effectively connection, and exchanges data is gone out.Therefore, the hardware platform of realizing this technology needs and can realize between two host computer systems that the data isolation that directly connects under the link disconnection switches transmission.Present technology implementation method all adopts an electronic switching device that has storer, and the external data transmission bus that connects two main frames is carried out switching controls, and the method for ferrying with data exchanges.The external data transmission bus packet that adopts is drawn together serial ports, parallel port, IDE, SCSI and USB etc.
The storer that prior art adopts is generally the magnetic store that has certain bus interface, as hard disk.For example, the U.S. Whale company that is found in 1998, the major product of the said firm comprises the SSLVPN of e-Gap series and application firewall (Application Firewall) etc., these products all based on the unified switching hardware platform of isolating that is called the Airgap technology, mainly be made up of switch and storer based on SCSI bus by this hardware platform.Adopt the method major defect that above-mentioned these external data transmission buses are switched to have: 1) external data transmission bus is used for the peripheral hardware of host computer system, will take the processor time in hand-off process.Therefore, data transmission and processing can be restricted, and influence throughput of system when switching transmission at a high speed.2) be subjected to the restriction of specific bus technology, a little less than the control ability of electronic switch, the mode that can not initiatively adopt hardware interrupts at a high speed and the real-time informing host computer system switch transmission.3) adopt magnetic store, as hard disk, as sequestering memory, its read or write speed is limited, influences system data exchange throughput.
Summary of the invention
The objective of the invention is to above-mentioned deficiency and defective, a kind of data isolation switched transmission method based on embedded system growth data bus is provided at prior art.Make it utilize the growth data bus of embedded system can obtain the transfer rate suitable with system bus, far above general external data transmission bus, and can control switching as electronic switch with the high-speed programmable device, switch transmission with the hardware interrupts real time notification system, in addition, replace magnetic store will obtain higher data with static memory and switch the transmission throughput as sequestering memory.The present invention will obtain higher data switching transmission performance than switch transmission technology based on the isolation of external data transmission bus.
The present invention is achieved by the following technical solutions.The growth data bus of two 32 embedded hosts is isolated switch unit by connecting after level difference parallel circuit (LVDS) conversion of signals, realizes that by isolating switch unit the growth data bus that connects two embedded host systems is carried out time slot in turn to be switched.Isolate switch unit comprise be used for the LVDS signal revert to the growth data bus signals the LVDS signaling conversion circuit, adopt isolation switch controller that CPLD (CPLD) realizes and as the static memory (SRAM) of sequestering memory.After the growth data bus process LVDS conversion of signals of a main frame, be connected to isolation by cable and switch hardware cell, link to each other with the SRAM of sequestering memory after reverting to the growth data bus signals through the LVDS signaling conversion circuit again, this transmission channel is isolated switch controller and is controlled, and has only when isolating switch controller switching gate main frame growth data bus and could be read and write the SRAM as sequestering memory by this main frame.The CPLD that isolates switch controller reads and writes the SRAM storer in real time by sending interrupt response signal triggering embedded host system, any time can only have a host computer system that SRAM is read and write, and, can be implemented in and carry out high-speed real-time bi-directional data switching transmission in the embedded two-computer system that is equipped with the growth data bus interface by organization and management to the SRAM storer.
Below the present invention is further illustrated, particular content is as follows:
1) LVDS conversion of signals
Because the growth data bus of embedded system, the address bus equisignal line all is a HW High Way, therefore its transmission is restricted apart from height, in order to carry out the signal transmission of certain distance between dual systems, the present invention has adopted the method that high speed signal is converted to LVDS (level difference parallel circuit) signal.Growth data bus, the address bus of embedded host system, read (READ) and write (WRITE) signal wire, sheet choosing (CS) signal wire to be converted to the LVDS differential signal by LVDS conversion of signals chip, differential signal is connected to the isolation switch unit by transmission cable, the LVDS conversion of signals chip of isolating on the switch unit is converted to the high speed signal of original system again to low level differential signal, is connected on the SRAM sequestering memory.Signal on high-speed line good transmission in than long distance can be convenient to and isolate switch being connected of hardware system by this method.Growth data bus and LVDS transmission line are diconnected, and address bus is to isolating the unidirectional output of switch unit.
2) adopt CPLD as isolating switch controller
Switch and need carry out under very high frequency owing to isolate, common electronic switch can't reach requirement, and the present invention has adopted the high speed complex programmable logic device (CPLD) as isolating switch controller.The look-at-me (IRQ) of the general input/output port (GPIO) of two main frames, busy (BUSY) signal of read-write and highest addresses signal wire are connected to the CPLD that isolates in the switch unit by LVDS conversion of signals chip isolates on the switch controller, and CPLD isolates the Enable Pin (EN) that switch controller is also connecting LVDS conversion of signals chip.CPLD isolates enable the switch control that EN signal carry out transmission line of switch controller by gating host side LVDS chip periodically, behind gating and the access limit of notifying host computer system that the SRAM sequestering memory is carried out with look-at-me before disconnecting.
3) tissue of SRAM sequestering memory
Because host computer system is to switch read-write at a high speed to the storer that isolate to switch in the hardware, therefore common storer all can not meet the demands as flash memory (FLASH) and Dram (SDRAM) etc., more need not carry magnetic store such as hard disk.Therefore the sequestering memory of isolating in the switch unit among the present invention has been selected static memory SRAM.The SRAM that switching controls software in the host computer system connects the growth data bus regards the storage area of a linearity as, adopts physical address to carry out addressing and read-write.Direction difference according to transmission is independently two sections of addresses with the memory block spatial division, can only write last sector address one side's main frame, and the opposing party's main frame can only be read, and the operation of following sector address is just in time opposite.By transmission direction being stored on the physical space of information separated and to carry out better security control.CPLD isolates switch controller and distinguishes sector address or time sector address by the selection to the signal of the highest addresses bus that connected.
4) host computer system is to the read-write of SRAM sequestering memory
When the switching controls software in the main frame carries out read-write operation in preparation to the SRAM storer, must understand the break-make situation of current transmission line.Isolate the mode of depositing switch controller employing interruption and notify main frame, after switching connection sequestering memory connected last side's main frame, the isolation switch controller sent hardware interrupts to this main frame and notifies the read-write of main frame to sequestering memory.When read data, for guaranteeing that main frame intactly reads the data in the SRAM sequestering memory, CPLD isolates switch controller the BUSY signal wire that is connecting is provided high level always, after CPLD isolation switch controller is received the read signal of SRAM sequestering memory, just provide the BUSY low level, main frame just can read data bus like this.
Major advantage of the present invention has: adopt the processing power that can make full use of host cpu based on the data isolation switched transmission method of growth data bus, obtain transmission and the readwrite performance suitable with system bus, than based on external data transmission bus, can obtain higher transfer efficiency as buses such as SCSI, IDE.Employing the inventive method can not be subjected to the performance limitations of external data transmission bus, and transmission line is carried out the high speed switching and adopts the corresponding mode of hard interruption to notify main frame to read and write in real time.In addition, the present invention adopts static memory to make sequestering memory, switches the transmission throughput with can only adopting the method for magnetic store to compare based on external data transmission bus can to obtain higher data.
Description of drawings
The functional block diagram of Fig. 1 the inventive method implementation system
Fig. 2 the present invention isolates the fundamental diagram of switch controller
Embodiment
Technical solution of the present invention will be further described below in conjunction with accompanying drawing.
As shown in Figure 1, the functional block diagram of the inventive method implementation system comprises: two embedded host systems (as, can select Intel Xscal embedded processor system for use), CPLD isolates switch controller, SRAM sequestering memory.Two host computer systems link to each other with the SRAM sequestering memory by the growth data bus, CPLD isolates switch controller the growth data bus is carried out switching controls, and control makes any time have only a host computer system to read and write the SRAM sequestering memory to the read-write operation of SRAM sequestering memory.
As shown in Figure 2, CPLD of the present invention isolates the fundamental diagram of switch controller.CPLD isolates the look-at-me IRQ line that switch controller is connecting two host computer systems, and the EN that enables of BUSY line and LVDS chip holds.CPLD exports the waveform of periodic transformation, alternately controls the EN that enables of two ends LVDS conversion chip, changes its on off operating mode.Make that at any time, CPLD isolates the growth data bus that switch controller can only trigger a host computer system, is connected with the SRAM sequestering memory by the LVDS conversion of signals.In the overall process, CPLD isolates switch controller and just is responsible for providing cycle control signal, and the sheet of control SRAM sequestering memory selects the CS signal, and data, address bus need not to isolate switch controller through CPLD.Every a switching cycle, isolate switch controller by CPLD and provide the IRQ look-at-me earlier, notify the read-write of the main frame cut-out of an end to the SRAM sequestering memory, provide the EN signal again, the sequestering memory LVDS signaling conversion circuit that this end leads to SRAM is led in cut-out, opens the LVDS signaling conversion circuit of the other end subsequently with the EN signal, provides the IRQ look-at-me again, the main frame of the notice other end begins reading writing working, replaces so repeatedly.CPLD isolates switch controller and at ordinary times the BUSY line is provided high level, when main frame can be read, CPLD isolated switch controller and provides the BUSY low level, and the expression main frame is read data bus correctly.
The inventive method is through the concrete enforcement of system prototype, but is proved to be line stabilization.It has made full use of the processing power of host-processor, can obtain the maximum high speed data transfer ability suitable with system bus; Avoided being subject to the shortcoming of concrete bussing technique like the method switching controls, can switch and adopt hard interrupt mode real-time informing main frame to transmit at a high speed, improved the utilization factor of transmission line based on external data transmission bus type; And adopt the static memory that to read and write at a high speed to adopt the mode of magnetic store to have higher system-through-up capability than adopting like method based on external data transmission bus type as sequestering memory.
Claims (5)
1, a kind of data isolation switched transmission method based on embedded system growth data bus, it is characterized in that, the growth data bus of two 32 embedded hosts is isolated switch unit by connecting after the LVDS conversion of signals, realize that by isolating switch unit the growth data bus that connects two embedded host systems is carried out time slot in turn to be switched, isolate switch unit and comprise the LVDS signaling conversion circuit that is used for the LVDS signal is reverted to the growth data bus signals, adopt isolation switch controller that CPLD realizes and as the SRAM of sequestering memory, after the growth data bus process LVDS conversion of signals of a main frame, be connected to isolation by cable and switch hardware cell, link to each other with the SRAM of sequestering memory after reverting to the growth data bus signals through the LVDS signaling conversion circuit again, this transmission channel is isolated switch controller and is controlled, and has only when isolating switch controller switching gate main frame growth data bus and could be read and write the SRAM as sequestering memory by this main frame.The CPLD that isolates switch controller reads and writes the SRAM storer in real time by sending interrupt response signal triggering embedded host system, any time can only have a host computer system that SRAM is read and write, and, be implemented in and carry out high-speed real-time bi-directional data switching transmission in the embedded two-computer system that is equipped with the growth data bus interface by organization and management to the SRAM storer.
2, the data isolation switched transmission method based on embedded system growth data bus according to claim 1 is characterized in that, described LVDS conversion of signals is specific as follows:
The growth data bus of embedded host system, address bus, read and write signal line, chip selection signal line are converted to the LVDS differential signal by LVDS conversion of signals chip, differential signal is connected to the isolation switch unit by transmission cable, LVDS conversion of signals chip on the isolation switch unit is converted to low level differential signal the high speed signal of original system again, be connected on the SRAM sequestering memory, growth data bus and LVDS transmission line are diconnected, and address bus is to isolating the unidirectional output of switch unit.
3, the data isolation switched transmission method based on embedded system growth data bus according to claim 1 is characterized in that, described employing CPLD is as the isolation switch controller, and is specific as follows:
The look-at-me of the general input/output port of two main frames, read-write busy signal and highest addresses signal wire are connected to the CPLD that isolates in the switch unit by LVDS conversion of signals chip isolates on the switch controller, CPLD isolates the Enable Pin that switch controller is also connecting LVDS conversion of signals chip, CPLD isolates switch controller and carries out the switch control of transmission line by the Enable Pin signal of gating host side LVDS chip periodically, behind gating and the access limit of notifying host computer system that the SRAM sequestering memory is carried out with look-at-me before disconnecting.
4, the data isolation switched transmission method based on embedded system growth data bus according to claim 1 is characterized in that, the tissue of described SRAM sequestering memory is specific as follows:
The sequestering memory of isolating in the switch unit has been selected static memory SRAM, the SRAM that switching controls software in the host computer system connects the growth data bus regards the storage area of a linearity as, adopt physical address to carry out addressing and read-write, direction according to transmission is independently two sections of addresses with the memory block spatial division, CPLD isolates switch controller and distinguishes sector address or time sector address by the selection to the signal of the highest addresses bus that connected, can only write last sector address one side's main frame, the opposing party's main frame can only be read, and the operation of following sector address is just in time opposite.
5, the data isolation switched transmission method based on embedded system growth data bus according to claim 1 is characterized in that host computer system is to the read-write of SRAM sequestering memory, and is specific as follows:
Isolate the mode of depositing switch controller employing interruption and notify main frame, after switching the last side's main frame of connection sequestering memory connection, isolate switch controller this main frame is sent the read-write of hardware interrupts notice main frame to sequestering memory, when read data, for guaranteeing that main frame intactly reads the data in the SRAM sequestering memory, CPLD isolates switch controller the BUSY signal wire that is connecting is provided high level always, after CPLD isolation switch controller is received the read signal of SRAM sequestering memory, just provide the BUSY low level, main frame could read data bus like this.
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| CNB2004100180180A CN1278248C (en) | 2004-04-29 | 2004-04-29 | Data isolation switching transmission method based on extended data bus of embedded system |
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| CNB2004100180180A CN1278248C (en) | 2004-04-29 | 2004-04-29 | Data isolation switching transmission method based on extended data bus of embedded system |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368223A (en) * | 2011-10-08 | 2012-03-07 | 深圳和而泰智能控制股份有限公司 | Dual-core embedded system and control method |
| CN104734358A (en) * | 2015-03-20 | 2015-06-24 | 南京国电南自电网自动化有限公司 | Intelligent switch controller with fast outlet loop |
| CN105631364A (en) * | 2015-05-20 | 2016-06-01 | 宇龙计算机通信科技(深圳)有限公司 | Security property switching method, security property switching apparatus and terminal |
| CN104460482B (en) * | 2014-12-18 | 2017-01-25 | 中国电子科技集团公司第三十九研究所 | CPLD-based double-computer thermal-switching controller |
| CN107612530A (en) * | 2017-09-14 | 2018-01-19 | 博为科技有限公司 | A kind of high-speed differential signal switching switch |
| WO2022166426A1 (en) * | 2021-02-05 | 2022-08-11 | 中国电子科技集团公司第五十八研究所 | Inter-die high-speed expansion system and method |
| CN117013996A (en) * | 2023-09-27 | 2023-11-07 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
-
2004
- 2004-04-29 CN CNB2004100180180A patent/CN1278248C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368223A (en) * | 2011-10-08 | 2012-03-07 | 深圳和而泰智能控制股份有限公司 | Dual-core embedded system and control method |
| CN104460482B (en) * | 2014-12-18 | 2017-01-25 | 中国电子科技集团公司第三十九研究所 | CPLD-based double-computer thermal-switching controller |
| CN104734358A (en) * | 2015-03-20 | 2015-06-24 | 南京国电南自电网自动化有限公司 | Intelligent switch controller with fast outlet loop |
| CN105631364A (en) * | 2015-05-20 | 2016-06-01 | 宇龙计算机通信科技(深圳)有限公司 | Security property switching method, security property switching apparatus and terminal |
| CN107612530A (en) * | 2017-09-14 | 2018-01-19 | 博为科技有限公司 | A kind of high-speed differential signal switching switch |
| CN107612530B (en) * | 2017-09-14 | 2023-11-28 | 博为科技有限公司 | High-speed differential signal change-over switch |
| WO2022166426A1 (en) * | 2021-02-05 | 2022-08-11 | 中国电子科技集团公司第五十八研究所 | Inter-die high-speed expansion system and method |
| CN117013996A (en) * | 2023-09-27 | 2023-11-07 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
| CN117013996B (en) * | 2023-09-27 | 2023-12-01 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
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| CN1278248C (en) | 2006-10-04 |
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