CN102368223A - Dual-core embedded system and control method - Google Patents
Dual-core embedded system and control method Download PDFInfo
- Publication number
- CN102368223A CN102368223A CN2011103016864A CN201110301686A CN102368223A CN 102368223 A CN102368223 A CN 102368223A CN 2011103016864 A CN2011103016864 A CN 2011103016864A CN 201110301686 A CN201110301686 A CN 201110301686A CN 102368223 A CN102368223 A CN 102368223A
- Authority
- CN
- China
- Prior art keywords
- processor
- primary processor
- primary
- embedded system
- core embedded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
The invention provides a dual-core embedded system and a control method. The system comprises a master processor, a slave processor and a bus isolator, wherein the slave processor carries out real-time data interaction with the master processor by a serial communication interface, and takes over the operation of the master processor when the master processor runs abnormally; and the bus isolator is electrically connected with the master processor and the slave processor, and isolated from the master processor and communicated with the slave processor when the master processor runs abnormally. By using the system provided by the invention, when the master processor runs normally, the slave processor carries out back-up on the system; and when the master processor runs abnormally, the slave processor takes over the running mode of the master processor, thereby avoiding the paralysis of the system because of the abnormality of the master processor, improving the performance of the system and the reliability of products, and then prolonging the service life of products.
Description
Technical field
The present invention relates to areas of information technology, specially refer to a kind of dual core embedded system and control method.
Background technology
Along with science and technology is constantly progressive; The function of each product is also more and more; In order to realize that the components and parts that these functions are used also get more and more; So just caused system performance and product reliability to reduce, how to have guaranteed product under multi-functional situation, improved system performance and product reliability and more and more received people's attention.Have and adopt to reduce components and parts in order to improve system performance and product reliability in the prior art, but this mode there is limitation improving on system performance and the product reliability very much.
Summary of the invention
The invention provides a kind of dual core embedded system and control method, be intended to improve system performance and product reliability.
The embodiment of the invention provides a kind of dual core embedded system, comprises primary processor, also comprises:
From processor, mutual through serial communication interface and primary processor real time data, when the primary processor operation irregularity, take over primary processor work;
Buses isolator is electrically connected with primary processor with from processor, when the primary processor operation irregularity, isolates primary processor, is communicated with from processor.
Preferably, controlling said buses isolator from processor described in the present technique scheme isolates said primary processor and simultaneously said buses isolator is communicated to said from processor.
Preferably, serial communication interface described in the present technique scheme is the SPI communication interface.
Preferably, buses isolator described in the present technique scheme is a MUX.
Preferably, primary processor described in the present technique scheme or said be MCU, DSP and the ARM any from processor.
The embodiment of the invention also provides a kind of control method of dual core embedded system, may further comprise the steps:
Judge whether primary processor work is normal;
In proper working order when primary processor, back up from the data of processor the primary processor real-time, interactive;
When the primary processor operation irregularity, buses isolator is isolated primary processor, is communicated with from processor, takes over primary processor work from processor.
Preferably, judge described in the present technique scheme whether normal concrete steps are in primary processor work:
When receiving the data of primary processor real-time, interactive, judge that from processor primary processor is in proper working order from processor;
When not receiving the data of primary processor real-time, interactive, judge the primary processor operation irregularity from processor from processor.
Preferably, in proper working order described in the present technique scheme when primary processor, from processor to the concrete steps that the data of primary processor real-time, interactive back up be:
When said primary processor in proper working order; Saidly be communicated with primary processor from processor control bus isolator; Primary processor is realized this systemic-function, and primary processor to from the processor interaction data, backs up from the data of processor to the primary processor real-time, interactive in real time.
When the present invention adopts primary processor in proper working order, system is backed up from processor; During the primary processor operation irregularity, take over the mode of the work of primary processor, avoided system to paralyse, improved system performance and product reliability, and then prolonged product serviceable life because of the unusual of primary processor from processor.
Description of drawings
Fig. 1 is the structured flowchart of one embodiment of the invention;
Fig. 2 is the schematic flow sheet of one embodiment of the invention.
The realization of the object of the invention, functional characteristics and advantage will combine embodiment, further specify with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
One embodiment of the invention provides a kind of dual core embedded system, and with reference to Fig. 1, said dual core embedded system comprises: primary processor 1, from processor 2, serial communication interface 3 and buses isolator 4;
From processor 2, when said primary processor 1 is in proper working order, be used for this system backup, when said primary processor 1 operation irregularity, take over the work of primary processor 1, realize this systemic-function;
Buses isolator 4 is electrically connected with primary processor 1 with from processor 2, when said primary processor 1 operation irregularity, isolates said primary processor 1, is communicated with said from processor 2.
Simultaneously buses isolator 4 is being communicated with from processor 2 with said from the said primary processor 1 of said buses isolator 4 isolation of processor 2 controls described in the specific embodiment.
In the present embodiment, said this systemic-function comprises control, protection, detection and function such as communicate by letter at least.Carry out data interaction through serial communication interface 3 and primary processor 1 in real time from processor 2, and equally with primary processor 1 make the action that realizes this systemic-function.But because buses isolator 4 is when primary processor 1 operate as normal, only connect with primary processor 1, so even make the action that realizes this systemic-function from processor 2, but can not be with realizing that this systemic-function output to peripheral interface circuit; Again owing to carrying out data interaction through serial communication interface 3 and primary processor 1 in real time, so play the real-time effect that this system data is backed up from processor 2 from processor 2.When primary processor 1 occurs unusual; This can be the problems such as program fleet that primary processor 1 damages or primary processor 1 moves unusually; Can't receive the data of primary processor 1 in real time through serial communication interface 3 from processor 2; Judge primary processor 1 operation irregularity from processor 2, control bus isolator 4 is isolated primary processor 1 and simultaneously buses isolator 4 is switched to from processor 2, and can export realization this systemic-function from the action of this systemic-function of realization that processor 2 is made this moment.
When in proper working order, 2 pairs of these systems back up this embodiment from processor through primary processor 1; During primary processor 1 operation irregularity; Take over the processing mode of this systemic-function of work continuation realization of primary processor 1 from processor 2; Avoided system to paralyse, improved system performance and product reliability, and then prolonged product serviceable life because of the unusual of primary processor 1.
In specific embodiment for satisfy primary processor 1 and from processor 2 synchronously, need to adopt the high serial communication interface of traffic rate guarantee real time of data transmission and reliability.Preferably, said serial communication interface 3 is the SPI communication interface.
In specific embodiment, preferably, buses isolator 4 is a MUX.
In specific embodiment, primary processor 1 is any among MCU, DSP and the ARM.Certainly according to the application need of this dual core embedded system, primary processor 1 is not limited to MCU, DSP, and ARM can be any other microprocessor.
In specific embodiment, be MCU, DSP and the ARM any from processor 2.Certainly according to the application need of this dual core embedded system, be not limited to MCU, DSP and ARM, can be any other processor from processor 2.
One embodiment of the invention provides a kind of control method of dual core embedded system, and with reference to Fig. 2, the control method of said dual core embedded system may further comprise the steps:
S01 judges whether primary processor work is normal;
S02, in proper working order when said primary processor, back up from the data of processor said primary processor real-time, interactive;
S03, when said primary processor operation irregularity, buses isolator is isolated said primary processor, is communicated with saidly from processor, takes over primary processor work from processor.
In specific embodiment, for judging among the step S01 whether normal concrete steps are in primary processor work:
When receiving the data of said primary processor real-time, interactive, judge that from processor said primary processor is in proper working order from processor;
When not receiving the data of said primary processor real-time, interactive, judge said primary processor operation irregularity from processor from processor.
In specific embodiment,, to the concrete steps that the data of said primary processor real-time, interactive back up be from processor in proper working order among the step S02 when said primary processor:
When said primary processor in proper working order; Saidly be communicated with said primary processor from processor control bus isolator; Said primary processor is realized this systemic-function; Said this systemic-function comprises control, protection, detection and function such as communicate by letter at least, said primary processor in real time to said from the processor interaction data, saidly back up from the data of processor to said primary processor real-time, interactive.
In specific embodiment, for working as said primary processor operation irregularity among the step S03, buses isolator is isolated said primary processor, is communicated with from processor, and the concrete steps of taking over primary processor work from processor are:
When said primary processor operation irregularity; This can be the problems such as program fleet that primary processor damages or primary processor moves unusually; Saidly isolate said primary processor from processor control bus isolator; Simultaneously said buses isolator is communicated to saidly from processor, the said work of taking over primary processor from processor realizes this systemic-function.
The above is merely the preferred embodiments of the present invention; Be not so limit claim of the present invention; Every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (8)
1. a dual core embedded system comprises primary processor, it is characterized in that, also comprises:
From processor, mutual through serial communication interface and primary processor real time data, when the primary processor operation irregularity, take over primary processor work;
Buses isolator is electrically connected with primary processor with from processor, when the primary processor operation irregularity, isolates primary processor, is communicated with from processor.
2. dual core embedded system according to claim 1 is characterized in that, saidly controls said buses isolator from processor and isolates said primary processor and simultaneously said buses isolator is communicated to said from processor.
3. dual core embedded system according to claim 1 and 2 is characterized in that, said serial communication interface is the SPI communication interface.
4. dual core embedded system according to claim 1 and 2 is characterized in that, said buses isolator is a MUX.
5. dual core embedded system according to claim 1 and 2 is characterized in that, said primary processor or said be MCU, DSP and the ARM any from processor.
6. the control method of a dual core embedded system is characterized in that, may further comprise the steps:
Judge whether primary processor work is normal;
In proper working order when primary processor, back up from the data of processor the primary processor real-time, interactive;
When the primary processor operation irregularity, buses isolator is isolated primary processor, is communicated with from processor, takes over primary processor work from processor.
7. the control method of dual core embedded system according to claim 6 is characterized in that, saidly judges that whether normal primary processor work concrete steps be:
When receiving the data of primary processor real-time, interactive, judge that from processor primary processor is in proper working order from processor;
When not receiving the data of primary processor real-time, interactive, judge the primary processor operation irregularity from processor from processor.
8. the control method of dual core embedded system according to claim 6 is characterized in that, and is said in proper working order when primary processor, from processor to the concrete steps that the data of primary processor real-time, interactive back up is:
When said primary processor in proper working order; Saidly be communicated with primary processor from processor control bus isolator; Primary processor is realized this systemic-function, and primary processor to from the processor interaction data, backs up from the data of processor to the primary processor real-time, interactive in real time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103016864A CN102368223A (en) | 2011-10-08 | 2011-10-08 | Dual-core embedded system and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103016864A CN102368223A (en) | 2011-10-08 | 2011-10-08 | Dual-core embedded system and control method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102368223A true CN102368223A (en) | 2012-03-07 |
Family
ID=45760788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103016864A Pending CN102368223A (en) | 2011-10-08 | 2011-10-08 | Dual-core embedded system and control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102368223A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104424053A (en) * | 2013-08-27 | 2015-03-18 | 上海机电工程研究所 | ARM embedded type control system and control method based on redundancy architecture |
| CN104735298A (en) * | 2013-12-24 | 2015-06-24 | 中国科学院沈阳自动化研究所 | Video target tracking master-slave standby system and method |
| WO2015135100A1 (en) * | 2014-03-10 | 2015-09-17 | 华为技术有限公司 | Method for switching processors, computer, and switching apparatus |
| CN106597941A (en) * | 2016-12-15 | 2017-04-26 | 哈尔滨工业大学 | Dual-processor redundant data acquisition and control system with self-detection function |
| CN111427821A (en) * | 2020-03-19 | 2020-07-17 | 深圳震有科技股份有限公司 | Method, system and storage medium for sharing SPI interface by dual-core AMP system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434998A (en) * | 1988-04-13 | 1995-07-18 | Yokogawa Electric Corporation | Dual computer system |
| CN1570894A (en) * | 2004-04-29 | 2005-01-26 | 上海交通大学 | Data isolation switching transmission method based on extended data bus of embedded system |
| CN101625568A (en) * | 2009-08-14 | 2010-01-13 | 江西联创通信有限公司 | Synchronous data controller based hot standby system of main control unit and method thereof |
| CN101799776A (en) * | 2010-02-25 | 2010-08-11 | 上海华为技术有限公司 | Fault processing method of multi-core processor, multi-core processor and communication device |
-
2011
- 2011-10-08 CN CN2011103016864A patent/CN102368223A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434998A (en) * | 1988-04-13 | 1995-07-18 | Yokogawa Electric Corporation | Dual computer system |
| CN1570894A (en) * | 2004-04-29 | 2005-01-26 | 上海交通大学 | Data isolation switching transmission method based on extended data bus of embedded system |
| CN101625568A (en) * | 2009-08-14 | 2010-01-13 | 江西联创通信有限公司 | Synchronous data controller based hot standby system of main control unit and method thereof |
| CN101799776A (en) * | 2010-02-25 | 2010-08-11 | 上海华为技术有限公司 | Fault processing method of multi-core processor, multi-core processor and communication device |
Non-Patent Citations (2)
| Title |
|---|
| 《高技术通讯2008年12月》 20081231 谢宗武、魏然、金明河、夏进军 基于商用现成器件设计星载计算机关键模块的研究 1285-1290 1-8 第18卷, 第12期 * |
| 谢宗武、魏然、金明河、夏进军: "基于商用现成器件设计星载计算机关键模块的研究", 《高技术通讯2008年12月》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104424053A (en) * | 2013-08-27 | 2015-03-18 | 上海机电工程研究所 | ARM embedded type control system and control method based on redundancy architecture |
| CN104735298A (en) * | 2013-12-24 | 2015-06-24 | 中国科学院沈阳自动化研究所 | Video target tracking master-slave standby system and method |
| WO2015135100A1 (en) * | 2014-03-10 | 2015-09-17 | 华为技术有限公司 | Method for switching processors, computer, and switching apparatus |
| CN106597941A (en) * | 2016-12-15 | 2017-04-26 | 哈尔滨工业大学 | Dual-processor redundant data acquisition and control system with self-detection function |
| CN111427821A (en) * | 2020-03-19 | 2020-07-17 | 深圳震有科技股份有限公司 | Method, system and storage medium for sharing SPI interface by dual-core AMP system |
| CN111427821B (en) * | 2020-03-19 | 2021-10-01 | 深圳震有科技股份有限公司 | Method, system and storage medium for sharing SPI interface by dual-core AMP system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102368223A (en) | Dual-core embedded system and control method | |
| CN103809476A (en) | Dynamic management method for IDs of module control units of distributed battery management system | |
| EP3407566A1 (en) | Automobile electrical system and isolation system for automobile electrical system | |
| ATE508560T1 (en) | METHOD AND COMMUNICATION SYSTEM FOR TRANSMITTING INFORMATION IN A MOTOR VEHICLE | |
| CN101513887A (en) | Method for competition type hot standby switching of intelligent automatic train monitoring system | |
| WO2009146224A8 (en) | System, method, and computer software code for linking a plurality of powered systems having different linking protocols to operate as a single powered system | |
| CN104842903A (en) | Electric control system of electric vehicle, electric vehicle and fault information transfer method | |
| CN104753749A (en) | Multi-host communication method and multi-host communication system | |
| CN101281511A (en) | On-chip bus system | |
| CN101847107B (en) | External data receiving method based on message queue | |
| CN102343897B (en) | Braking control system of rail transit vehicle and anti-skidding control plate for braking control system of rail transit vehicle | |
| CN103910256B (en) | Interconnected elevator device and progress control method thereof | |
| ATE417316T1 (en) | INTERRUPTION SCHEME FOR BUS CONTROLLER | |
| WO2013053643A3 (en) | Method for operating a control network, and control network | |
| CN104637293A (en) | Bus dispatching system | |
| CN104599518A (en) | Bus stop waiting system | |
| EP1669881A3 (en) | Computer system, fault tolerant system using the same and operation control method and program thereof | |
| CN107861494B (en) | The real-time detection and Synchronization of multi_motor control device | |
| CN101866174A (en) | Electronic communication control system for anti-lock braking system in automobile vacuum booster fatigue test | |
| CN204291010U (en) | For the vehicle power carrier module of CAN Bus in Electric backup communication | |
| CN102050363B (en) | High-rise elevator control master command board and control method thereof | |
| WO2009158263A3 (en) | Communication system and a method and call processor for use in the system | |
| CN201270521Y (en) | Data collection apparatus using dual backup links | |
| CN103049420A (en) | Internal memory multiplexing method and portable terminal | |
| CN205405146U (en) | Control system of robot |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120307 |