CN1556469A - Digital signal processor having fast digit extraction and digit insertion units - Google Patents
Digital signal processor having fast digit extraction and digit insertion units Download PDFInfo
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- CN1556469A CN1556469A CNA2004100157381A CN200410015738A CN1556469A CN 1556469 A CN1556469 A CN 1556469A CN A2004100157381 A CNA2004100157381 A CN A2004100157381A CN 200410015738 A CN200410015738 A CN 200410015738A CN 1556469 A CN1556469 A CN 1556469A
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Abstract
The invention relates to a DSP with a fast bit extracting and inserting unit, integrating a bit extracting and inserting unit into an arithmetic operation unit of the DSP kernel, where the bit extracting and inserting unit is composed of adders, shifters and source and object registers, replacing existing 'multiple select one' logic with an AND-XOR logic to reduce time delay, as carrying on bit extracting operation, shifting and making addition operation at the same time and replacing longer-bit addition method with very short-bit addition method, as making bit-inserting operation, making an AND-XOR logic operation on the middle result, and obtaining the needed result. It uses the simplified structure to reduce the execution time of bit -extracting and -inserting instructions, and heightens area utilization ratio by multiplexing devices, thus increasing cost/performance trade-off of the whole chip.
Description
Technical field
What the present invention relates to is a kind of digital signal processor, and particularly a kind of digital signal processor that has extraction of quick position and bit inserting unit belongs to digital signal processing technique field.
Background technology
In high-end DSP chip design, it is a lot of as EXTRACT, INSERT application that instruction is inserted in position extraction and position.In the DSP56300 series handbook-24 bit digital signal processor third edition (DSP56300Family Manual-24-bit Digital SignalProcessor Revision 3.0) of company of U.S. Motorola (Motorola), introduce the way of realization of these two instructions, represented the main flow implementation method of current these two instructions.Yet, realize that this type of instruction need carry out repeatedly shifting function and multi channel selecting logical operation, the realization of inserting instruction such as the position needs tri-level logic, one deck is shifting function, other two-layer intermediate results that all need deposit multiselect one operation with 1 temporary register, thereby compare with other instructions and to need the more execution time.If the monocycle is carried out this class instruction, they often become the critical path of chip, have determined the maximum clock frequency of chip.In addition, repeatedly using shift unit and depositing long numeric data needs bigger chip area, thereby causes the increase of chip cost.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of digital signal processor that has extraction of quick position and bit inserting unit is proposed, use fast with or logical circuit rather than slower multiselect one circuit reduce time delay, thereby use the repeated use of device technology to reduce area and reduce power consumption, when carrying out the position extraction, can carry out additive operation in the time of displacement, and substitute the addition of longer figure place with the addition of very short figure place.
The digital signal processor that the present invention relates to mainly comprises: address-generation unit, instruction decoding unit, procedure control unit, arithmetic operation unit.Procedure control unit provides instruction address by instruction bus to command memory, and the reception instruction is delivered to instruction decoding unit with it from command memory.Instruction decoding unit will be deciphered later data and send to the two-way parallel data channel, i.e. arithmetic operation unit and address-generation unit.Arithmetic operation unit is passed to procedure control unit with its status information, and operation result is given data-carrier store or received data from data-carrier store.Address-generation unit is given data-carrier store with address value, specifies the position of corresponding storage and read-write.The present invention described arithmetic operation unit inner integrated a position extract and bit inserting unit.
Position of the present invention is extracted and bit inserting unit mainly comprises: totalizer, shift unit and source-register and destination register.When extract the position, the value input summer or the shift unit of source-register, the output of totalizer or shift unit outputs in the destination register through after some logical operations.When inserted the position, bit wide and offset value were input to a totalizer, and it is exported as first intermediate result; The value of source-register and offset value are input to a shift unit, and it is exported as second intermediate result; Directly obtain the 3rd intermediate result according to side-play amount.These three intermediate results be input to respectively with or arithmetic logic unit, generates two interim numbers as or the inputs of door, its output promptly obtain need the result.
When the simple bit manipulation of operation, call general shift unit, traditional multilayer tandem type structure is simplified as far as possible, reduced the execution time; Carrying out the position when extracting operation, 6 additive operations and shifting function are carried out simultaneously, thus with obtain and reach the related symbol position and saved one operation of one deck multiselect, and the addition of two 6 figure places only needs one 7 register to deposit the result, thereby has saved area.Position insertion operation needed for two steps finished, 3 interim operands of the parallel generation of the first step; Second step to three intermediate results that generate carry out with or logical operation, generates two and counts temporarily; At last these two interim numbers are carried out exclusive disjunction, obtain the result who needs.
The present invention has substantive distinguishing features and marked improvement.Classic method needs three layers when realizing that instruction is inserted in the position, the present invention is reduced to it two-layer, has almost reduced by 1/3rd time delay; Adopt time delay less with or logic substitute slower multiselect one logic and also can reduce time delay; With the position extract class instruction and position insert that class instruction realizes in same unit can multiplexing many intermediate results or same shift unit, thereby reduce chip area, reduce chip power-consumption.The present invention utilize simplification structure decrease the position extract and execution time of instruction is inserted in the position, improved area utilization by repeated use of device, thereby improved the cost performance of entire chip.
Description of drawings
Fig. 1 is the one-piece construction block diagram of digital signal processor of the present invention.
As shown in Figure 1, processor of the present invention is by digital signal processor kernel and command memory, data-carrier store is formed by connecting, wherein kernel comprises procedure control unit, instruction decoding unit, arithmetic operation unit and address-generation unit extract and bit inserting unit in the inner integrated position of arithmetic operation unit.
Fig. 2 extracts class command function synoptic diagram for position of the present invention.
Fig. 3 inserts class command function synoptic diagram for position of the present invention.
Fig. 4 extracts the realization flow figure of class instruction for position of the present invention.
Fig. 5 inserts the realization flow figure of class instruction for position of the present invention.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is further described.
Relation between each composition module in the digital signal processor of the present invention has been described among Fig. 1.As shown in Figure 1, digital signal processor of the present invention is by digital signal processor kernel and command memory, data-carrier store is formed by connecting, and wherein the digital signal processor kernel comprises: address-generation unit, instruction decoding unit, procedure control unit, arithmetic operation unit.The instruction decoding unit of digital signal processor kernel connects arithmetic operation unit and address-generation unit, and the two-way procedure control unit that is connected to, and procedure control unit is connected to command memory, and obtains instruction from command memory; Arithmetic operation unit links to each other with procedure control unit is unidirectional; The two-way data-carrier store that is connected to of arithmetic operation unit, the address generator unit is connected to data-carrier store and can be carried out bidirectional data exchange with arithmetic operation unit by address bus.Extract the position and bit inserting unit is positioned at arithmetic operation unit.
Procedure control unit provides instruction address by instruction bus to command memory, and the reception instruction is delivered to instruction decoding unit with it from command memory.Instruction decoding unit will be deciphered later data and send to the two-way parallel data channel, i.e. arithmetic operation unit and address-generation unit.Arithmetic operation unit is passed to procedure control unit with its status information, and operation result is given data-carrier store or received data from data-carrier store.Address-generation unit is given data-carrier store with address value, specifies the position of corresponding storage and read-write.The present invention described arithmetic operation unit inner integrated a position extract and bit inserting unit.
As shown in Figure 2, extraction class in position of the present invention instruction is realized by 2 source-registers and 1 destination register.Source-register and destination register are 72.Low 6 representatives of source-register 1 will be extracted the value (width) of the bit wide of operation, the side-play amount (offset) of the reference position that high 6 representatives of source-register 1 are extracted from source-register 2.[offset+width-1:offset] in the source-register 2 moves to [width-1:0] of destination register.Other of destination register are done the sign bit expansion according to (offset+width-1) position of source-register 2.
As shown in Figure 3, insertion class in position of the present invention instruction is realized by 2 source-registers and 1 destination register.Low 6 representatives of source-register 1 will be carried out the value (width) that the bit wide of operation is extracted in the position, and the value (offset) of the reference position of destination register is inserted in high 6 representatives of source-register 1.[width-1:0] in the source-register 2 moves to [offset+width-1:offset] of destination register, and other positions of destination register keep initial value constant.
As shown in Figure 4, the present invention carries out 6 additive operations that bit wide adds side-play amount when source-register 2 is carried out shifting function, with the related symbol position that obtains and reach source-register 2.Carry out additive operation in the time of displacement, but only need the time delay call instruction execution result of first level logical.The more important thing is that the present invention saves one operation of one deck multiselect, saves the execution time greatly.The addition of two 6 figure places only needs one 7 register to deposit the result, thereby saves chip area.
Quick bit inserting unit involved in the present invention needed for 2 steps finished.As shown in Figure 5,3 interim operands of the parallel generation of the first step: bit wide and offset value are input to a totalizer, thereby obtain insertion value 1; The value of source-register and offset value are input to a shift unit, obtain the move to left insertion value 2 of side-play amount position of value with source-register 2; The insertion value 3 that directly obtains according to side-play amount.Insertion value 1 and insertion value 2 are linked and door A, and its output obtains interim several 1; Insertion value 3 is through a reverser and insertion value 1 is input to together or door C, or the value of the output of door C and destination register is input to together and a door B obtains interim several 2; Two interim numbers are linked again or the input end of door D, should or the output terminal of door obtains is exactly end product.
Claims (1)
1, a kind of digital signal processor that has extraction of quick position and bit inserting unit, comprise address-generation unit, instruction decoding unit, procedure control unit, arithmetic operation unit, it is characterized in that extracting and bit inserting unit in the inner integrated position of arithmetic operation unit, comprise and realize that extract the position and this two classes instruction is inserted in the position, the class instruction is extracted in the position two source-registers and a destination register, low 6 representatives of first source-register will be extracted the value of the bit wide of operation, the value of the reference position that high 6 representatives are extracted from second source-register, [offset+width-1:offset] in second source-register moves to [width-1:0] of destination register, and other of destination register are done the sign bit expansion according to (offset+width-1) position of second source-register; The class instruction is inserted in the position two source-registers and a destination register, low 6 representatives of first source-register will be carried out the value that the bit wide of operation is extracted in the position, the value of the reference position of destination register is inserted in high 6 representatives, [width-1:0] in second source-register moves to [offset+width-1:offset] of destination register, and other positions of destination register keep initial values constant; When extract the position, the value input summer or the shift unit of source-register, the output of totalizer or shift unit outputs in the destination register through after the logical operation, when insert the position, bit wide and offset value are input to a totalizer, its output is as first intermediate result, the value of source-register and offset value are input to a shift unit, its output is as second intermediate result, directly obtain the 3rd intermediate result according to side-play amount, these three intermediate results be input to respectively with or arithmetic logic unit, generates two interim numbers as or the inputs of door, its output promptly obtain need the result.
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| CN 200410015738 CN1259620C (en) | 2004-01-09 | 2004-01-09 | Digital signal processor having fast digit extraction and digit insertion units |
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| CN 200410015738 CN1259620C (en) | 2004-01-09 | 2004-01-09 | Digital signal processor having fast digit extraction and digit insertion units |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102884505A (en) * | 2011-04-08 | 2013-01-16 | 松下电器产业株式会社 | Data processing device and data processing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102884505A (en) * | 2011-04-08 | 2013-01-16 | 松下电器产业株式会社 | Data processing device and data processing method |
| CN102884505B (en) * | 2011-04-08 | 2016-01-20 | 松下电器产业株式会社 | Data processing equipment and data processing method |
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