CN1553301A - Network information collector for ultrasonic radio frequency signal analysis under PC machine control - Google Patents

Abstract

A collector is composed of PC computer four circuits of A/D conversion circuit, SDRAM buffer control circuit, network control circuit and configuration regulation circuit as well as self-defined bus for communicating to each other with four circuits. The self-defined busis realized through STD bus plate and the four circuit are all ste in cage ofindustrial controller with STD bus plate. The Ethernet is used as media of data and command communication between the collector and PC computer so data collection and loading is easy to realize and easy to manage.

Description

The network information gathering device that under PC control, is used for ultrasonic rf signal analysis

Technical field

The network information gathering device that is used for ultrasonic rf signal analysis under PC control belongs to ultrasonic radiofrequency signal and calculates the acquisition technique field.

Background technology

The collection of ultrasonic radiofrequency signal is based on one of the important component part of the tissue characterization of ultrasonic radiofrequency signal.Designing requirement for the collector of ultrasonic radiofrequency signal is: high sampling rate (10M～20MHz) and big buffer memory (＞=128M).Present most of radiofrequency signal collector is not the A/D card that adopts more existing industrial uses, adopts independently high speed data acquisition system exactly.The regulation of pci bus agreement wherein adopt collector that the A/D card of industrial use realizes because can only be gathered the data of 64M byte at most.And when gathering the perfected monopoly pci bus of PC of this capture card, interrupted normal communication between other PCI plug-in card and CPU.And existing independently high speed data acquisition system is all realized buffer memory by static memory, causes buffer memory too small and cost is too high.Simultaneously, how the instruction and data communication between existing independently high speed data acquisition system and PC under different operating system all needs different driver be installed by special purpose interface, has limited its versatility.

Summary of the invention

The objective of the invention is to overcome the weak point of prior art, design a kind of network information gathering device that is used for ultrasonic rf signal analysis, it is based on a self-defining internal bus, by the A/D change-over circuit, the SDRAM cache control circuit, network control circuit and four plug-in cards of configuration debug circuit are implemented in the ultrasonic radiofrequency signal of continuous acquisition 128M byte under the 20MHz sampling rate, and by realizing network communication between ICP/IP protocol and the PC.

A kind of network information gathering device that is used for ultrasonic rf signal analysis, by PC, A/D change-over circuit, SDRAM cache control circuit, network control circuit and configuration debug circuit four partial circuits and the self-defined bus composition that makes the mutual communication of four partial circuits.Said PC is for having installed the PC of network interface card arbitrarily, and operating system can be selected any operating system of support network operations, and using system is Windows2000 in one embodiment of the invention, and the software that cooperates with this information acquisition device is installed.Said self-defining internal bus has been realized the data between each circuit and the communication of instruction.Said A/D change-over circuit comprises the preposition amplification and the adjustment of ultrasonic radiofrequency signal, frame synchronizing signal is adjusted, the A/D conversion chip, realize the A/D conversion and control and the A/D translation data is delivered to CPLD (CPLD on the self-defined bus, what use among a kind of embodiment of the present invention is the ACEX family chip of the field programmable logic matrix-FPGA of ALTERA company, but the said firm claims that its product all is CPLD, so be also referred to as CPLD here) chip, the CPLD that is attached thereto configuration and system logic debugging are with single-chip microcomputer and be solidificated in control program in the Single Chip Microcomputer (SCM) program storer, and are used for providing for CPLD 4 frequency multiplier circuits of system clock.Said SDRAM cache control circuit comprises the DIMM interface socket that inserts the sdram memory bar, for CPLD provides 6 frequency multiplier circuits of system clock, realize being sent to the CPLD chip of self-defined bus to the CPLD of SDRAM read-write control and SDRAM refresh control and with the data among the SDRAM and the CPLD configuration that is attached thereto and system logic debugging with single-chip microcomputer be solidificated in control program in the Single Chip Microcomputer (SCM) program storer.Network control circuit comprises network interface card interface ISA socket, network control single-chip microcomputer and the data latches that is attached thereto, data-carrier store and be solidificated in control program in the Single Chip Microcomputer (SCM) program storer, be used for the CPLD of network control single-chip microcomputer and self-defined internal bus communication and the CPLD configuration that is attached thereto and system logic debugging with single-chip microcomputer be solidificated in the control program of Single Chip Microcomputer (SCM) program storer.Said configuration debug circuit comprises the ATX power interface that power supply is provided to system, configuration and serial ports and the serial ports level transferring chip of debugging with single-chip microcomputer and PC communication, be used for storing FLASH storer and the FLASH read-write single-chip microcomputer and the control program that is solidificated in the Single Chip Microcomputer (SCM) program storer of each circuit CPLD logic, the resistor chain that draws on the realization bus signals, with the CPLD chip that is used for debugging and the CPLD that is attached thereto configuration and system logic debugging with single-chip microcomputer be solidificated in the control program of Single Chip Microcomputer (SCM) program storer, also promising self-defined bus provides the clock chip of clock.Said four partial circuits all are installed in the industrial computer cage that has a STD bus plate by slot.

Ultrasonic rf signal analysis system is by medical B ultrasonic instrument, and the network information gathering device is formed.Comprise medical B ultrasonic instrument, and from medical B ultrasonic instrument, draw ultrasonic radiofrequency signal and frame synchronizing signal is delivered to the network information gathering device.Also comprise the network information gathering device and an ATX power supply of power supply is provided for it.And PC and some input equipments (as keyboard, mouse etc.), output device (as display, printer etc.), ethernet communication interface and other equipment that are attached thereto (as disc driver etc.).Realize network information gathering device and the data of PC and the communication of instruction by network interface.Network information gathering device of the present invention has been realized the continuous acquisition of the ultrasonic radiofrequency signal of the high sampling rate under the PC control as high speed data acquisition system independently.By uploading of the control of the Control Network information acquisition device of the PC of realizing based on form 2000 (Windows2000) specific program and the data that collect.

The invention is characterized in:

The network information gathering device, it comprises following each circuit:

The A/D change-over circuit, it contains:

The simulation part:

B ultrasonic radiofrequency signal path: mainly be composed in series successively by the input impedance matching circuit that is input as the B ultrasonic radiofrequency signal, pre-amplification circuit and level adjusting circuit collection,

The frame synchronizing signal path: mainly adjust circuit by the signal waveform that is input as frame synchronizing signal and constitute, it is a comparer that is barricaded as with the general-purpose operation amplifier,

The A/D conversion portion, it is the A/D conversion chip that a TLC5540 constitutes,

A/D conversion and control part: it is a complex programmable logic device (CPLD) 1, its input end and above-mentioned A/D conversion chip, and each output terminal of Waveform adjusting circuit and system clock circuit links to each other; Its output terminal links to each other with the clock signal input terminal of A/D conversion chip; It and configuration, debugging interconnects with self-defined bus STD again with the single-chip microcomputer interconnection simultaneously; Its inside is by the A/D steering logic assembly of mutual interconnection, debug serial port logic module and three partly integrated compositions of self-defined bus interface logic assembly.Wherein, the input signal of A/D steering logic is from A/D conversion chip and frame synchronizing signal path, and the clock signal of output is delivered to the A/D conversion chip, and the debug serial port logical and disposes, debugging interconnects with single-chip microcomputer.

Single-chip microcomputer is used in configuration, debugging, and it links to each other with a latch, links to each other with STD bus by universal serial bus in addition;

Clock circuit, it is to CPLD1 output system clock signal;

The SDRAM cache control circuit, it contains:

Synchronous Dynamic Random Access Memory SDRAM,

Be used for realizing SDRAM read-write, refresh control also are sent to the data of SDRAM the complex programmable logic chip CPLD2 of self-defined bus plate STD, it is mainly by the steering logic assembly of the read-write of SDRAM being controlled by the DIMM socket, self-defined bus interface logic assembly, with the debug serial port logic module that disposes, debugging interconnects with single-chip microcomputer, and inner different in width bus interface conversion logic assembly, address accumulator logic module are formed

Be interconnected to SDRAM and to its read-write, refresh control is with the DIMM socket between the CPLD,

Configuration, the debugging single-chip microcomputer, it and above-mentioned CPLD2 interconnect, and link to each other with STD bus by universal serial bus in addition;

Clock circuit, it is to CPLD2 output system clock signal

Network control circuit, it contains:

Network interface, it is that single-chip microcomputer is used in the network interface card control that is connecting address latch and static RAM (SRAM) respectively, network interface card interface ISA socket will insert an ISA network interface card on it, links to each other with PC by netting twine,

The complex programmable logic chip CPLD3 of control network interface card and self-defined internal bus communication, it mainly by with the self-defined bus steering logic assembly of self-defined bus interconnection, with the debug serial port logic module that disposes, debugging interconnects with single-chip microcomputer, with the parallel port communication logic module of network interface card control with the single-chip microcomputer interconnection, and and the integrated composition of dma control logic assembly of network interface card (the ISA socket of network interface card) interconnection

Configuration, debugging single-chip microcomputer, it and CPLD3 interconnect, and link to each other with STD bus by universal serial bus in addition, and it also has a serial ports and the serial ports level transferring chip used with the communication of PC controller

Configuration and debug circuit, it contains:

Debugging is with complex programmable logic device (CPLD) 4, it be by with configuration and debugging with the debug serial port logic module of single-chip microcomputer interconnection and with integrated the forming of self-defined bus steering logic assembly of self-defined bus STD interconnection,

Configuration, debugging single-chip microcomputer, it and CPLD4 interconnect

The FLASH storer, the logic of wherein storing the CPLD1～CPLD4 of each part mentioned above,

FLASH reads and writes single-chip microcomputer, it and FLASH memory interconnect, and it is also through universal serial bus and self-defined bus plate STD interconnection (closure and each configuration, debug opposite with single-chip microcomputer),

Serial ports and serial ports are changed conversion chip, are connected in the serial port of PC controller, and are connected with single-chip microcomputer with each configuration, debugging by the universal serial bus of STD bus

Clock circuit is for self-defined bus provides 10M clock signal

Self-defined internal bus interface plate STD, it with above-mentioned A/D change-over circuit, SDRAM control circuit, network control circuit and configuration and debug circuit in separately CPLD definition bus steering logic assembly interconnect mutually, it contains following self-defined internal bus:

The bCLK clock signal,

The bRST# reset signal,

BAD[31::0] 32 bit address and data multiplex, definition is same with pci bus,

BC/BE[3::0] bus line command, be equivalent to the C/BE[3::0 of pci bus] bus line command,

BFRAME# frame period signal is equivalent to the definition of pci bus signal,

The bMRDY# main equipment is ready to, and is identical with the IRDY# definition of pci bus,

The bSRDY# slave unit is ready to, and is identical with the TRDY# definition of pci bus,

The bREQ# bus takies request signal,

The bLOCK# bus takies locking signal,

The signal wire bTXD and the bRXD that are used for serial communication.

Experimental results show that:

Use one embodiment of the invention, the 1MHz sinusoidal signal that signal generator provides is sampled, as can be seen from Figure 13, waveform is sinusoidal wave, does not have any distortion, and the number of data points of one-period is 20 points just.We gather the radiofrequency signal of drawing from B ultrasonic instrument (sea, Wuxi hawk HY3100), in acquired signal, scan with the heart of ultrasound wave sector probe the normal person, for carrying out the result that B ultrasonic figure rebuilds with the signal of gathering under storing, the cardiac structure figure that result and B ultrasonic display show fits like a glove from Figure 14.From Figure 13, Figure 14 as can be seen, our sampling is very accurately.

Description of drawings

Fig. 1. system construction drawing of the present invention.

Fig. 2. configuration debugging network figure.

Fig. 3 .A/D change-over circuit block diagram.

Fig. 4 .SDRAM cache control circuit block diagram.

Fig. 5. the network control circuit block diagram.

Fig. 6. configuration and debug circuit block diagram.

Fig. 7. the circuit block diagram of self-defined bus part.

Fig. 8. the self-defined bus burst transmits process flow diagram

Fig. 9. (a) one of A/D conversion control circuit schematic diagram;

(b) two of A/D conversion control circuit schematic diagram;

B1. clock circuit

B2. signal waveform is adjusted circuit

The b3.A/D change-over circuit

Figure 10. (a) one of SDRAM control circuit schematic diagram;

(b) two of SDRAM control circuit schematic diagram;

(c) three of SDRAM control circuit schematic diagram;

C1. clock part

C2. control section

Figure 11. (a) one of circuit theory diagrams of network interface card control section;

A1.ISA network interface card socket part

A2. network interface card drives single chip part

(b) circuit theory diagrams of network interface card control section two;

Figure 12. (a) one of configuration and debug circuit schematic diagram;

A1.CPLD and self-defined bus annexation

The a2.2.5V power supply

A3. bus clock part

The supply socket of a4.ATX PC

A5. pull-up resistor is arranged part

(b) two of configuration and debug circuit schematic diagram;

B1. serial ports level shifting circuit

B2. serial port socket

B3.FLASH reads and writes part

B4. dispose the CPLD single chip part

Figure 13. gather the result of 1M sinusoidal signal.

Figure 14. gather B ultrasonic radiofrequency signal reconstructed B-mode image.

Embodiment

Total system can be operated in configuration and debugging mode and data acquisition and upload two states.

At configuration and debugging mode, PC by in serial port and the configuration debug circuit in order to the single-chip microcomputer of read-write FLASH, and the single-chip microcomputer in order to the configuration of CPLD and system logic debugging links to each other in each circuit, forms and disposes debugging network.The workflow of this network is: FLASH read-write single-chip microcomputer is read the configuration information of CPLD in each circuit from the FLASH storer.And, these configuration informations are delivered to corresponding C PLD configuration and system logic debugging single-chip microcomputer by the configuration debugging network.Dispose corresponding CPLD with single-chip microcomputer by the configuration information of receiving by CPLD configuration and system logic debugging again.PC can monitor that by serial ports this layoutprocedure is up to finishing or ending this process.Afterwards, PC just can send the renewal that instruction realizes configuration information in the FLASH storer to FLASH read-write single-chip microcomputer by the configuration debugging network.Or by the configuration debugging network, PC can be debugged the logical design of each CPLD in the system.Configuration can be referring to accompanying drawing 2 with the workflow of debugging mode.When state was uploaded in data acquisition, the instruction and the data flow of system were as follows: at first have PC to send the data acquisition instruction by Ethernet interface to the network information gathering device.This instruction is accepted by network control circuit, and then network control circuit will be applied for the control of self-defining internal bus.After the control that obtains self-defining internal bus, network control circuit sends the data acquisition instruction to the A/D change-over circuit by this bus.The A/D change-over circuit is received the control of the self-defining internal bus of instruction back application.Negative edge or wait synchronizing signal in control that obtains self-defining internal bus and received frame synchronizing signal are overtime, the A/D change-over circuit starts the A/D conversion, and data converted is transferred to the SDRAM cache control circuit by self-defining internal bus, by SDRAM cache control circuit data storage in the sdram memory bar.The length of translation data is provided by conversion instruction.In transfer process, whether PC can finish by the Ethernet query conversion.PC provides data upload instruction and will be stored in the data cached of sdram memory bar and upload in the PC behind EOC.Uploading instruction is sent to the network information gathering device by Ethernet interface by PC.This instruction is accepted by network control circuit, and network control circuit is applied for the control of self-defining internal bus again.Then by internal bus, network control circuit reads and is stored in data cached in the SDRAM cache control circuit.And these data are uploaded in the PC by network interface too.Accepted up to PC that all are data cached, then finished once complete data acquisition upload operation.

A kind of network information gathering device embodiment that is used for ultrasonic rf signal analysis of the present invention, by the A/D change-over circuit, the SDRAM cache control circuit, network control circuit and configuration debug circuit four partial circuits are formed and PC, and four partial circuits are realized mutual communication by making bus by oneself.Below these several major parts are introduced respectively.

Self-defining internal bus is the definition realization on the isa bus plate that is defined in of reference PCI bus.It is made up of following signal: the bCLK clock signal; The bRST# reset signal; BAD[31::0] 32 bit address and data multiplex, definition and pci bus are together; BC/BE[3::0] bus line command, be equivalent to the C/BE[3::0 of pci bus] bus line command; BFRAME# frame period signal is equivalent to the definition of pci bus signal; The bMRDY# main equipment is ready to, and is identical with the IRDY# definition of pci bus; The bSRDY# slave unit is ready to, and is identical with the TRDY# definition of pci bus; The bREQ# bus takies request signal; The bLOCK# bus takies locking signal.Except above these signals, two signal wire bTXD and bRXD that are used for serial communication have also been defined on the bus.The workflow of relevant bus can be referring to accompanying drawing 7 and accompanying drawing 8.

The A/D change-over circuit is one of key Design of present networks information acquisition device.High speed data acquisition system is realized the sampling that synchronous triggering signal is arranged of 20MHz sampling rate, 8bit sampling precision by it.This realizes by selecting A/D conversion chip and circuit design.It is made up of simulation, A/D conversion and three parts of numeral.Wherein simulation part is divided into B ultrasonic radiofrequency signal and two paths of frame synchronization again.Wherein B ultrasonic radiofrequency signal path is mainly adjusted three parts by input impedance matching, preposition amplification and level again and is formed.The frame synchronizing signal path is mainly adjusted circuit by the comparer that the general-purpose operation amplifier is barricaded as signal waveform, removes and disturbs.What the A/D conversion chip was selected is the TLC5540 chip.It is 8 analog to digital converters of Texas Instruments company, and the input bandwidth is 75MHz, and maximum slew rate reaches 40MHz.The numerical portion of A/D change-over circuit is mainly realized A/D conversion and control and total line traffic control.Here mainly realize these control by using on the EP1K10TC100-3 of the ACEX of altera corp 1K series to programme by VHDL language.This VHDL code is made up of self-defined bus interface, A/D conversion and control logic and debug serial port logic.The block diagram of A/D change-over circuit is seen figure (3)

The circuit theory diagrams of A/D change-over circuit can be referring to Fig. 9 (a), Fig. 9 (b).Main element comprises, in Fig. 9 (a), UBF1 (EP1K10P100) for we use CPLD, realize control by its to the A/D conversion.U601 (RC1117) is the voltage transitions chip, in order to produce 2.5V voltage.U401 (MSC2051) promptly disposes and debugs the single-chip microcomputer of usefulness, and U402 (74HC244) is a latch.S1 (STD) is the self-defined bus plate, in order to circuit board is inserted into the STD bus slot.Among Fig. 9 (b), U9001 (ICS601) is a clock chip, is used for bus frequency 4 frequencys multiplication of 10M are arrived 40M, for CPLD provides frequency of operation.UADC002 (LT1225) is the preposition amplification chip of radiofrequency signal.UADC001 (TLC5540) is the chip of A/D conversion, and UADC004A (LF442) is for radiofrequency signal provides direct current biasing, is used for the voltage range of radiofrequency signal is transformed into the input voltage range of TLC5540.UADC004B (LF442) adjusts circuit for signal waveform, removes for synchronizing signal and disturbs.

Relevant pinout of CPLD and annexation are as follows: clk (UBF1-39) is a system clock in the chip, and frequency is 40MHz, and U9001 (ICS601) will output to CPLD from U9001-1 after 10M clock (U9001-8) 4 frequencys multiplication of bus input; ADCD[0..7] (corresponding to UBF1-34, UBF1-43, UBF1-45 is to UBF1-50) and be the input of A/D transformation result, TLC5540 outputs to CPLD with eight transformation results after finishing the AD conversion from UADC001-10 to UADC001-3; ADCCLK (UBF1-33 pin) is the output of CPLD clock, and frequency is 20MHz, is produced by the CPLD internal logic, outputs to UADC001-12 as the A/D change over clock; CSIGNAL (UBF1-29) is the frame synchronizing signal input, it is the frame synchronization regulating circuit at center that frame synchronizing signal is input to UADC004B (LF442) through CON2 (NADC002) from the outside, signal through a resistance R ADC009, outputs to UBF1-39 from output pin UADC004-7 after regulating; The P1.6 of single-chip microcomputer U401 (MSC2051), P1.5 and P1.4 are through latching the pin aCONFIG# (UBF1-51) that U402 (74HC244) is connected to CPLD, aDCLK (UBF1-75), aDATA0 (UBF1-76), in order to write configuration data to CPLD, the aCONFIG_DONE of CPLD (UBF1-1) and aSTATUS# (UBF1-25) give single-chip microcomputer by latching P1.3 and the P1.2 that is connected to single-chip microcomputer in order to return configuration status.Other pin of CPLD (pin name with b beginning) be used for STD bus be the S1 communication.Not drawing on figure individually in addition, all is power supply or ground connection.

In addition, after CON1 (NADC001) input, earlier through the preposition amplification of UADC002 (LT1225), export from UADC002-6 to the signal of-5V-+5V by the scope that obtains from the outside for radiofrequency signal.Because A/D conversion chip input range is that 0.6V is to 2.6V.Need level adjusting circuit the level of RF signals of the output of preposition amplification to be adjusted to the incoming level of A/D conversion.At first (RADC201 RADC202) takes out the intermediate level of A/D reference voltage to the resistance of the 50K by two series connection, and finely tunes by the potentiometer of 5K.The follow circuit that this intermediate level is barricaded as by general-purpose operation amplifier LF442 is with superimposed by the radiofrequency signal of the prime amplifier output of electric capacity after straight.Thereby realize required level conversion.Signal after the commentaries on classics is passed to A/D conversion chip TLC5540 signal input pin UADC001-19.

The SDRAM cache control circuit has been realized the buffer memory of data in the A/D gatherer process, and reads data in buffer by network control circuit from data caching circuit in the data upload process.For high frequency big data quantity acquisition system, the design of data caching circuit is very important.It has realized the read or write speed of storage space and the 160bps of 128Mbyte in the present embodiment.It is made up of the SDRAM cache control circuit the DIMM socket of configuration, debug circuit and the SDRAM of CPLD and CPLD, and is core with the CPLD as the bridge of SDRAM and self-defined bus.The VHDL programming code of this CPLD mainly is made up of self-defined bus interface logic, different in width bus interface conversion logic, address accumulator logic, SDRAM steering logic and debug serial port logic.Fig. 4 is the block diagram of SDRAM cache control circuit.

The schematic diagram of SDRAM cache control circuit can be referring to Figure 10 (a), Figure 10 (b) and Figure 10 (c).Main element has, and the DIMM socket S2 (SDRAM_DIMM) in the accompanying drawing 10 (a) is in order to plug a commercial 128M SDRAM.U101 (EP1K30QC208) among Figure 10 (b), for realizing that SDRAM read-write control reaches and the CPLD of bus communication, Figure 31 0b) S1 in, and the S1 (STD) among Figure 10 (c), U9001 (ICS601), U401 (MSC2051), U402, function is with element of the same name in the A/D conversion control circuit, and what difference was that ICS601 produces herein is the clock signal of 60MHz.

The signal wire of DIMM interface definition is basic identical with the pin of SDRAM.From Figure 10 (a), can see that pinout comprises: 1. address and data-signal: sBA[0,1] be page address (S2-122, S2-39), sA[0..11] be the address signal bus, sDQMB[0..7] be the data input/output port.2. system signal: the sCLK clock signal (S2-42, S2-125, S2-79, S2-163).3. control signal: sRAS# row address input (S2-115), sCAS# column address input (S2-111), sWE# write enable signal (S2-113).In addition, the DIMM interface expands to 64 to the width of the data signal bus of internal memory, corresponding to the sDQ[0..63 of S2].Simultaneously by 4 gating signal sS[0..3] and the extended address scope (S2-30, S2-114, S2-45, S2-129).A slice serial EEPROM is all arranged on the general memory bar, be used for the parameter information that stored memory transplants a cutting, so sSDA (S2-82) is arranged on the DIMM interface, sSDL (S2-83) is with visiting this EEPROM.

The access control of SDRAM is to be undertaken by CPLD.The CPLD that chooses is U101 (EP1K30QC208-2).Therefore pinout has comprised the pin that links to each other with the DIMM socket, promptly transmit the sDQ[0..63 of data], the sA[0..11 of transport address], in addition in order to control the sS[0..3 of SDRAM] (U101-100, U101-99, U101-73, U101-71), sCAS# (U101-112), sRAS# (U101-97), sWE# (U101-113), sCK (U101-111).Clock signal clk (U101-79).SSDA (U401-19) and sSDL (U401-11) in order to configuration EEPROM.ACONF_DONE (U101-2) in addition, aSTATUS# (U101-52), aCONFIG# (U101-105), aDCLK (U101-155), aDATA0 (U101-156) function is with the A/D conversion control circuit.Other pin of CPLD (pin name with b beginning) be used for STD bus be the S1 communication.CPLD also has the pin that does not draw individually on figure, all be power supply or ground connection.

Accompanying drawing 4 (c) is a configuration CPLD single chip part in the SDRAM cache control circuit, and clock circuit.The annexation of single-chip microcomputer and CPLD is similar substantially with the relation that links to each other in the A/D change-over circuit, the P1.6 of single-chip microcomputer U401 (MSC2051), P1.5 and P1.4 are through latching the pin aCONFIG# (U101-105) that U402 (74HC244) is connected to CPLD, aDCLK (U101-155), aDATA0 (U101-156), in order to write configuration data to CPLD, the aCONFIG_DONE of CPLD (U101-2) and aSTATUS# (U101-52) give single-chip microcomputer by latching P1.3 and the P1.2 that is connected to single-chip microcomputer in order to return configuration status.Using clock chip still is ICS601, in the SDRAM cache control circuit, the frequency of operation of CPLD is 60M, be that ICS601 will deliver to CPLD (U101-79) by U9001-1 after 10M STD bus frequency 6 frequencys multiplication of U9001-8 input, and CPLD provides 30M clock by internal logic for SDRAM, outputs to (S2-42, S2-79 from (U101-111), S2-125, S2-163).

Network control circuit has realized receiving the instruction from the 10M Ethernet, and according to other circuit on the indication control self-defined bus of these orders.It can divide for the network interface be made up of single-chip microcomputer and network interface card and be self-defined bus interface two parts of core with CPLD.Network interface is a core with the single chip computer AT 89C51 of atmel corp, it and address latch, and static RAM (SRAM) has been formed a complete Single Chip Microcomputer (SCM) system.Because the network interface card that native system uses is with the isa bus Ethernet card of DM9008 as control chip.And isa bus is an asynchronous bus, and its read-write sequence is identical with the sequential of 51 series monolithics.So this network interface card can easier insert Single Chip Microcomputer (SCM) system.Because the CPLD that has only used static RAM (SRAM), network interface card here and controlled, totally 3 external chips as self-defined bus.So native system only uses the highest 2 (P2.7 and the P2.6) of single-chip microcomputer external address bus selection signal as these 3 chips.The visible Fig. 5 of its circuit block diagram.In addition, in single-chip microcomputer, realized ICP/IP protocol in the present embodiment, made native system can realize with INTERNET exchange message easily.

The circuit theory diagrams of network control circuit can be referring to Figure 11 (a) and Figure 11 (b).Its main element comprises that among Figure 11 (a), U6 (89C51) is a single-chip microcomputer, is used for controlling the operation of network interface card.J7 and J10 are the socket of isa bus plate altogether, will plug the network interface card of an isa bus during actual the use.U5 (74HC373) is for latching, and U7 (62256) is the RAM of expansion.In the accompanying drawing 5 (b), the CPLD that UBF1 (EP1K10TC100-3) selects for use for us, U601 provides 2.5V power supply for CPLD.S1 (STD), U401 (MSC2051) is identical with preceding two parts circuit function with U402 (74LV244) function.

This part circuit is that the typical case of one 51 single-chip microcomputer uses, address bus ADDR[8..14], data bus DATA[7..0], single-chip microcomputer U6 (89C51) passes through ADDR15, ADDR14 realizes the ISA network interface card, expansion RAM, CPLD is gating respectively, the RD of single-chip microcomputer (U6-17) respectively with the ISA network interface card, expansion RAM, the read gate pin of CPLD links to each other (CPLD read gate pin is UBF1-29), the WR of single-chip microcomputer (U6-16) respectively with the ISA network interface card, expansion RAM, the write gate pin of CPLD (CPLD write gate pin is UBF1-30) links to each other.CPLD has used the EP1K10TC100-3 of the ACEX1K series of altera corp, its pinout comprise with the pin (network name starts with b) of STD bus communication and and the used pin of single-chip microcomputer configuration CPLD: aCONF_DONE (UBF1-1), aSTATUS# (UBF1-25), aCONFIG# (UBF1-51), aDCLK (UBF1-75), aDATA0 (UBF1-76), joining of these pins and peripheral cell is the same substantially with preceding two parts circuit, no longer repeat specification.Also have I/OWRITE (UBF-30) in addition, I/OREAD (UBF1-29), ADDR[14..15 in order to link to each other with the network interface card control single chip computer] (UBF1-31, UBF1-32), DATA[0...7] (UBF1-33, UBF1-43 is to UBF1-50).Work clock bCLK (UBF1-90).This part circuit CPLD directly uses bus clock as work clock, does not have independent clock circuit.Remaining pin (the pin name starts with b) all is used for promptly linking to each other with S1 (STD) with the STD bus communication.The pin that draws on circuit diagram in the end is power supply or ground connection.

Configuration and debugging network: the CPLD that has used altera corp in the system in a large number, the chip of ACEX 1K series is realized and the control of self-defined bus communication and each plug-in card inherent logic, is comprised DMA communication between SDRAM control, A/D acquisition controlling, network interface card and self-defined bus.These CPLD chips are to use the static RAM (SRAM) in the sheet to store the configuration parameter of CPLD, so after powering on, all need they are carried out initialization operation again at every turn.So native system has been set up a configuration network specially.In order to realize debugging, on configuration network, carried Debugging message simultaneously, synthesized configuration and debugging network system's each several part.This network is a core with the configuration debug circuit, and comprises the debugging configuration executive circuit in other each circuit.The configuration debug circuit by FLASH chip, single-chip microcomputer, be used to debug the CPLD of other circuit, the power supply circuit on the self-defined bus and form for each communication signal based on the OC door provides the resistor chain circuit that draws and the clock signal generating circuit of self-defined bus.The VHDL code that wherein is used to debug the CPLD of other circuit is made up of self-defined bus interface and debug serial port logic.The circuit block diagram of configuration and debugging part is seen Fig. 6.

The circuit theory diagrams of configuration and debugging part are referring to Figure 12 (a) and Figure 12 (b).Main element comprises, among Figure 12 (a), UBF1 (EP1K10P100) is for being used for the CPLD with bus communication; 2.5V power supply produces chip U601 (RC1117) and provides 2.5V power supply for CPLD.U9001 (ICS601) is a clock chip; Y9001 is the 10M crystal oscillator; J9001 is supply socket; In order to insert in the ATX attaching plug that PC uses; R9014-R9017 is a resistor chain, draws for each communication signal based on the OC door provides.Among Figure 12 (b), MAX232 respectively disposes and calls single-chip microcomputer by serial mode and PC contact in order to realize read-write; CON302 is the socket that Serial Port Line inserts; U303 (NX25F080A) is a slice FLASH, stores the configuration of each CPLD; U301 (MSC2051) is the single-chip microcomputer of read-write FLASH; S1 (STD), U401 (MSC2051) is identical with first three partial circuit function with U402 (74LV244) function.

Here CPLD has selected EP1K10TC100-3 for use.Its pinout and network interface card control section are just the same (to be annotated: the I/OWRITE that defines in the network interface card control section, I/OREAD, DATA[0..7], ADDR[14..15] inoperative in this part), with configuration and debugging single-chip microcomputer, 2.5V power supply produces chip U601 (RC1117), metal finger S1 annexation and network interface card control circuit are just the same, so locate no longer to describe in detail.U301 (MSC2051) is by four input/output port (SF_SI, SF_SO, SF_SCK, SF_CS#) realize the SPI mouth, carry out the read-write operation among the FLASH, and by (RXD) P3.0 that links to each other with bRxd with the bTxd of STD bus and (TXD) P3.1) the serial side's row that is configured to of reading each CPLD in the FLASH delivers to the single-chip microcomputer that respectively disposes CPLD, by those single-chip microcomputers CPLD is configured.This part circuit is fairly simple, herein enumeration no longer.

In addition, use PC to be configured to PII667 in the present embodiment, 256 MB of memory, with the network interface card of a TPLINK, operating system is Windows 2000, has developed the acquisition software of communication Network Based under the VB environment.Because in the hardware design, based on the standard ICP/IP protocol, so do not need on the PC additionally any driver to be installed, software development also is easy to the network interface card control circuit to the control of network interface card.Since based on the standard ICP/IP protocol, if this system transplantation is arrived all the other operating systems, under LINUX, also very simple.

Claims (1)

1. under PC control, be used for the network information gathering device of ultrasonic rf signal analysis, comprise the PC controller, it is characterized in that it contains following each ingredient:

The network information gathering device, it comprises following each circuit:

The A/D change-over circuit, it contains:

The simulation part:

B ultrasonic radiofrequency signal path: mainly be composed in series successively by the input impedance matching circuit that is input as the B ultrasonic radiofrequency signal, pre-amplification circuit and level adjusting circuit collection,

The frame synchronizing signal path: mainly adjust circuit by the signal waveform that is input as frame synchronizing signal and constitute, it is a comparer that is barricaded as with the general-purpose operation amplifier,

The A/D conversion portion, it is the A/D conversion chip that a TLC5540 constitutes,

A/D conversion and control part: it is a complex programmable logic device (CPLD) 1, its input end and above-mentioned A/D conversion chip, and each output terminal of Waveform adjusting circuit and system clock circuit links to each other; Its output terminal links to each other with the clock signal input terminal of A/D conversion chip; It and configuration, debugging interconnects with self-defined bus STD again with the single-chip microcomputer interconnection simultaneously; Its inside is by the A/D steering logic assembly of mutual interconnection, debug serial port logic module and three partly integrated compositions of self-defined bus interface logic assembly.Wherein, the input signal of A/D steering logic is adjusted path from A/D conversion chip and frame synchronizing signal, and the clock signal of output is delivered to the A/D conversion chip, and the debug serial port logical and disposes, debugging interconnects with single-chip microcomputer;

Single-chip microcomputer is used in configuration, debugging, and it links to each other with a latch, links to each other with STD bus by universal serial bus in addition;

Clock circuit, it is to CPLD1 output system clock signal;

The SDRAM cache control circuit, it contains:

Synchronous Dynamic Random Access Memory SDRAM,

Be used for realizing SDRAM read-write, refresh control also are sent to the data of SDRAM the complex programmable logic chip CPLD2 of self-defined bus plate STD, it is mainly by the steering logic assembly of the read-write of SDRAM being controlled by the DIMM socket, self-defined bus interface logic assembly, with the debug serial port logic module that disposes, debugging interconnects with single-chip microcomputer, and inner different in width bus interface conversion logic assembly, address accumulator logic module are formed

Be interconnected to SDRAM and to its read-write, refresh control is with the DIMM socket between the CPLD,

Configuration, the debugging single-chip microcomputer, it and above-mentioned CPLD2 interconnect, and link to each other with STD bus by universal serial bus in addition;

Clock circuit, it is to CPLD2 output system clock signal

Network control circuit, it contains:

Network interface, it contains the network interface card control single-chip microcomputer that is connecting address latch and static RAM (SRAM) respectively, and network interface card interface ISA socket, will insert an ISA network interface card on it, link to each other with PC by netting twine,

The complex programmable logic chip CPLD3 of control network interface card and self-defined internal bus communication, it mainly by with the self-defined bus steering logic assembly of self-defined bus STD interconnection, with the debug serial port logic module that disposes, debugging interconnects with single-chip microcomputer, with the parallel port communication logic module of network interface card control with the single-chip microcomputer interconnection, and and the integrated composition of dma control logic assembly of network interface card (the ISA socket of network interface card) interconnection

Configuration, debugging single-chip microcomputer, it and CPLD3 interconnect, and link to each other with STD bus by universal serial bus in addition, and it also has a serial ports and the serial ports level transferring chip used with the communication of PC controller

Configuration and debug circuit, it contains:

The ATX power interface of power supply is provided for the network information gathering device

Debugging is with complex programmable logic device (CPLD) 4, it be by with configuration and debugging with the debug serial port logic module of single-chip microcomputer interconnection and with integrated the forming of self-defined bus steering logic assembly of self-defined bus STD interconnection,

Configuration, debugging single-chip microcomputer, it and CPLD4 interconnect

The FLASH storer, the logic of wherein storing the CPLD1～CPLD4 of each part mentioned above,

FLASH reads and writes single-chip microcomputer, it and FLASH memory interconnect, and it is also through universal serial bus and self-defined bus plate STD interconnection (closure and each configuration, debug opposite with single-chip microcomputer),

Serial ports and serial ports are changed conversion chip, are connected in the serial port of PC controller, and are connected with single-chip microcomputer with each configuration, debugging by the universal serial bus of STD bus

Clock circuit is for self-defined bus provides 10M clock signal

Self-defined internal bus interface plate STD, it with above-mentioned A/D change-over circuit, SDRAM control circuit, network control circuit and configuration and debug circuit in separately CPLD definition bus steering logic assembly interconnect mutually, it contains following self-defined internal bus:

The bCLK clock signal,

The bRST# reset signal,

BAD[31 ∷ 0] 32 bit address and data multiplex, definition is same with pci bus,

BC/BE[3 ∷ 0] bus line command, be equivalent to the C/BE[3 ∷ 0 of pci bus] bus line command,

BFRAME# frame period signal is equivalent to the definition of pci bus signal,

The bMRDY# main equipment is ready to, and is identical with the IRDY# definition of pci bus,

The bSRDY# slave unit is ready to, and is identical with the TRDY# definition of pci bus,

The bREQ# bus takies request signal,

The bLOCK# bus takies locking signal,

The signal wire bTXD and the bRXD that are used for serial communication.

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