CN1549319A - Open-window type ball grid array semiconductor packaging elements and its producing method and used chip bearing elements - Google Patents
Open-window type ball grid array semiconductor packaging elements and its producing method and used chip bearing elements Download PDFInfo
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- CN1549319A CN1549319A CNA031369448A CN03136944A CN1549319A CN 1549319 A CN1549319 A CN 1549319A CN A031369448 A CNA031369448 A CN A031369448A CN 03136944 A CN03136944 A CN 03136944A CN 1549319 A CN1549319 A CN 1549319A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
The present invention relates to a window-opened spherical grid array semiconductor package capable of preventing sealant overflow, its making method and used chip-bearing carrier. Said invention includes: a base plate with through hole, several bonding wire portions and ball-implanting portions defined on a surface and predefined exposed region positioned at one side of the through hole of said bonding wire portion, chip connected with said base plate and used for covering said through hole, flux-repelling layer laid on said base plate and exposing said ball-implanting portion, forming an opening around said through hole and exposing said through hole, said several bonding wire portions and said predefined exposed region, several bonding wires passed through said through hole and electrically connected with said chip and said bonding wire portion, and packaging sealant body covering said chip and bonding wire.
Description
Technical field
The invention relates to a kind of window type ball gird array semiconductor package part and method for making and used chip bearing member that prevents excessive glue, particularly about a kind of window type ball gird array semiconductor package part and method for making and used chip bearing member of preventing excessive glue that is of value to its electric connection quality.
Background technology
Window type ball gird array (Windows Ball Grid Array) semiconductor package part is to offer at least one through hole that runs through this substrate at employed substrate, supplying chip to connect in the mode that covers this through hole puts on a surface of this substrate, and by means of the bonding wire that passes in this through hole, electrically connect this chip and substrate, and on another apparent surface of substrate, plant a plurality of soldered balls, thereby chip is connected with the electronic building brick in the external world, therefore, get final product a design whereby and make central welding pad type (Central-Pad Type) chip shorten its wire length, reduce transfer impedance, and then can promote the thickness of its electrical quality and reduction overall package part.
This existing window type ball gird array encapsulating structure is shown in Fig. 5 A, on use one has, lower surface 81,82 substrate 80, on this substrate 80, offer a through hole 83 that runs through this substrate 80, and the default a plurality of position of bonding wire 84 of the conductive trace layer of the lower surface 82 of this substrate with plant ball position 85, for a chip 86 down with its action face 86a (Active Surface), connect and put on the upper surface 81 of this substrate, and cover an end of this through hole 83, make weld pad default on this chip 86 87 outer being exposed in this through hole 83, make many bonding wires 88 pass this through hole 83, weld pad 87 on this chip 86 is electrically connected to corresponding position of bonding wire 84 on this base lower surface 82, then, also on this substrate, lower surface 81,82 form one first packing colloid 90 and second packing colloid 91 respectively, make this first packing colloid 90 coat this chip 86, make this second packing colloid 91 fill up this through hole 83 and coat this bonding wire 88, at last, also on this lower surface 82 not by planting on the ball position 85 that this packing colloid 91 coats, plant a plurality of soldered balls 92, make this soldered ball 92 this chip 86 is electrically connected to extraneous printed circuit board (PCB) as I/O (I/O) end, for example United States Patent (USP) the 6th, 048, No. 755 cases, the 6th, 190, No. 943 cases, the 6th, 218, No. 731 cases and the 6th, 326, No. 700 prior aries such as case, all are dependency structure and the method for makings that propose window type ball gird array packaging part, solve the electrical or size restrictions of existing packaging part.
Though this window type ball gird array packaging part has above-mentioned advantage, because of also derived a difficult problem on other acceptance rate of its special procedure, this be since this type of packaging part when the sealing operation, owing to need to form in order to coat second packing colloid 91 of this bonding wire 88, so at this up and down in the both sides sealing operation, the bed die 94 of its set of molds certainly will need to form a die cavity 94a, forming the reservation shape of this second packing colloid 91, rather than employed bed die with smooth contact surface in the sealing operation as other ball grid array (BGA) packaging part; Therefore, shown in Fig. 5 B, when it carries out mold pressing sealing operation, be that the substrate 80 that will be laid with chip 86 and bonding wire 88 places an encapsulating mould 95, when an epoxy resin (Epoxy) material injects mould 95, can be filled among the upper mould cave 93a of its mold 93, and form first packing colloid 90, and be filled among the following die cavity 94a of its bed die 94 and form in order to coat second packing colloid 91 of bonding wire 88 in order to coating chip 86; Yet, on being somebody's turn to do, bed die 93,94 owing to be subject to the design of packaging part, so its die cavity size (Cavity Size) and cramping (Clamp) position be difference to some extent, the situation of the area of upper mould cave 93a covered substrate 80 greater than following die cavity 94a will be produced as shown in the figure, on this moment this base lower surface 82 in abutting connection with the not cramping (NC of this second packing colloid 91, Non-Clamping) zone, owing to do not bear the clamping force of this mold 93, and only bear the cramping that this bed die 94 makes progress, in this region generating not during the situation of driving fit clamping, and then after injecting resin material, the resin that causes forming this second packing colloid 91 overflows glue (Flash) to base lower surface 82, as the cutaway view of Fig. 5 C and the bottom view of 5D (5C looks from the B-B of 5D direction), this excessive glue pollution phenomenon not only reduces the surface smoothness and the good looking appearance of this packaging part, more may pollute simultaneously the predetermined ball position 85 of planting on this lower surface 82, cause soldered ball 92 can't intactly be soldered to substrate 80, thereby influence the electric connection quality of this packaging part.
Therefore, for above-mentioned United States Patent (USP) or other prior art, if can't effectively solve the excessive glue problem of this window type ball gird array packaging part, will definitely have a strong impact on the electrical quality of its assembly, can reduce the electrical transmission quality of this class packaging part, can't satisfy its improvement original intention, also make initial design meaning way have a greatly reduced quality.
In sum, how to develop a kind of window type ball gird array semiconductor package part and method for making thereof of the glue that prevents to overflow, electrically connect quality, take into account the surface smoothness and the clean outward appearance of this packaging part simultaneously, really the problem that need urgently face of this field to promote it.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of window type ball gird array semiconductor package part and method for making and used chip bearing member that prevents excessive glue, make it electrically connect effect and effectively promoted.
Another purpose of the present invention is to provide a kind of window type ball gird array semiconductor package part and method for making and used chip bearing member that prevents excessive glue, can improve the surface smoothness of this packaging part.
Another object of the present invention is to provide a kind of window type ball gird array semiconductor package part and method for making and used chip bearing member that prevents excessive glue, make this packaging part have cleaner outward appearance.
For reaching above-mentioned and other purpose, the window type ball gird array method for producing semiconductor packaging part of excessive glue that prevents provided by the present invention comprises: prepare a sandwich layer, have a first surface and an opposing second surface and have a through hole that runs through this sandwich layer, and on this second surface, define a plurality of bonding wire portions and plant the bulb, and be positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; On this second surface, lay one and refuse welding flux layer, and expose outside this a plurality of bulbs of planting, simultaneously, around this through hole, form an opening to expose outside this through hole, these a plurality of bonding wire portions and should predetermined expose the zone; Prepare at least one chip, put at the first surface of this sandwich layer and cover an end of this through hole, make this chip section be exposed at especially in this through hole so that this chip is connect; Form many bonding wires that pass this through hole, to electrically connect this chip and this bonding wire portion; Carry out a sealing operation, on the first surface of this sandwich layer, form first packing colloid and coat this chip, form second packing colloid and coat this bonding wire on the second surface of this sandwich layer, wherein, this is scheduled to expose the zone will form the narrowed flow path of this second packing colloid in this sealing operation; And plant a plurality of soldered balls and plant on the bulb in this.
The window type ball gird array semiconductor package part that prevents excessive glue that utilizes method for making of the present invention to make comprises: the sandwich layer with a first surface and an opposing second surface, has a through hole that runs through this sandwich layer, wherein, be that definition has a plurality of bonding wire portions and plants the bulb on this second surface, and be positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; At least one chip is to connect to put at the first surface of this sandwich layer and cover an end of this through hole, and makes this chip section be exposed to especially in this through hole; Be laid in the welding flux layer of refusing on the second surface of this sandwich layer, and expose outside this a plurality of bulbs of planting, and around this through hole, form an opening to expose outside this through hole, these a plurality of bonding wire portions and should predetermined expose the zone; Pass this through hole to electrically connect many bonding wires of this chip and this bonding wire portion; Packing colloid is to form first packing colloid coating this chip on the first surface of this sandwich layer, and forms second packing colloid cover this predetermined exposing on the zone to coat this bonding wire and to apply on the second surface of this sandwich layer; And plant at this and plant a plurality of soldered balls on the bulb.
Simultaneously, the chip bearing member that is used for above-mentioned window type ball gird array semiconductor package part that the present invention proposes comprises: have the sandwich layer of a first surface and an opposing second surface, a through hole that runs through this sandwich layer is arranged; Be laid in conductive trace layer on the second surface of this sandwich layer, and be that definition has a plurality of bonding wire portions and plants the bulb, and be positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; And refuse welding flux layer on this conductive trace layer that is laid in, and can make these a plurality of bulbs of planting expose outside this and refuse outside the welding flux layer, simultaneously, this is refused welding flux layer and forms an opening to expose outside this through hole, these a plurality of bonding wire portions and should predetermined expose the zone.
The above-mentioned predetermined width that exposes the zone is between 0.2 to 0.8 millimeter, and be the best with 0.4 millimeter (mm), and be to be adjacent to this bonding wire portion, with by this design, make this A/F of refusing welding flux layer be slightly larger than die cavity width in order to the mould that forms this second packing colloid, therefore, should predetermined expose the zone can be in the sealing operation, form this refuse between welding flux layer edge and this die cavity edge distance at interval, enclosed the narrowed flow path that is set to this second packing colloid by the surface of this mould, and the length of this runner is this predetermined width that exposes the zone.
Therefore work as this packaging part and carry out the sealing operation, when injecting packing colloid, this second packing colloid will be filled in this die cavity to coat these many bonding wires, and will flow in this runner to fill up this runner, at this moment, because this packing colloid is the viscous fluid of a low reynolds number (Reynolds Number), so to enter a bore anxious during according to the narrowed flow path of dwindling when it, according to hydromechanical theory, this moment, the viscosity of this viscous fluid slowed down flow velocity rising, and cause its dissipation of energy, second packing colloid that order flows in this narrowed flow path is stuck in this runner, unlikely overflow enters this and refuses pressing gap between welding flux layer and this die surface, can avoid existing excessive glue pollution problem.
Therefore, window type ball gird array semiconductor package part proposed by the invention and method for making thereof and used chip bearing member, be by this predetermined region design that exposes, make and form a sealing runner between itself and mould, make this second packing colloid also coat these many bonding wires except that complete being filled in this through hole, also by filling to this narrowed flow path, apply and cover this predetermined exposing on the zone, and form and highly approximate the plane that this refuses welding flux layer, and then can avoid the colloid glue that overflows to plant the bulb and influence the relevant issues of electric connection to this, can improve the surface smoothness of this packaging part, make this packaging part have cleaner outward appearance.
Description of drawings
Fig. 1 is the preferred embodiment cutaway view of window type ball gird array semiconductor package part of the present invention;
Fig. 2 A is the cutaway view of semiconductor package part of the present invention before the sealing operation;
Fig. 2 B is the bottom view of semiconductor package part of the present invention before the sealing operation;
Fig. 3 is the cutaway view of semiconductor package part of the present invention when carrying out the sealing operation;
Fig. 4 A to Fig. 4 F is the preparation flow chart of semiconductor package part of the present invention;
Fig. 5 A is the cutaway view of existing window type ball gird array semiconductor package part;
Fig. 5 B is the existing cutaway view of window type ball gird array semiconductor package part when carrying out the sealing operation;
Fig. 5 C is existing window type ball gird array semiconductor package part produces the glue phenomenon of overflowing in the sealing operation a cutaway view; And
Fig. 5 D is existing window type ball gird array semiconductor package part produces the glue phenomenon of overflowing in the sealing operation a bottom view.
Embodiment
Embodiment
The preferred embodiment cutaway view that is the glue window type ball gird array semiconductor package part that prevents to overflow of the present invention shown in Figure 1, it comprises that one has the substrate sandwich layer 10 (hereinafter to be referred as substrate) of first surface 11 and opposing second surface 12, connect the chip 20 of putting on this substrate 10 and having an action face 21 and non-action face 22, be formed on the first surface 11 of this substrate and the packing colloid 31,32 on the second surface 12, and plant a plurality of soldered balls 50 that are connected on this substrate second surface 12; Wherein, the central authorities of this substrate 10 have a through hole 13 that runs through this substrate 10, and 40 definition of the conductive trace (Trace) on this second surface 12 layer have a plurality of bonding wire portion 41 and plant bulb 42, make this a plurality of bonding wire portion 41 be distributed in this through hole 13 around, make this plant the both sides that bulb 42 arrays are arranged in this through hole 13 and connect a plurality of soldered balls 50 to plant, simultaneously, this chip 20 is to connect the first surface of putting at this substrate 11 with its action face 21, and cover an end of this through hole 13, make the electrical areas 23 on this action face 21 expose among this through hole 13, and the bonding wire portion 41 on the electrical areas 23 of passing this through hole 13 and electrically connecting this chip with many bonding wires 45 and this conductive trace layer 40, in addition, this first packing colloid 31 that is formed on the first surface 11 is in order to coat this chip 20, this is formed on the second surface 12, and 32 of more a spot of second packing colloids are in order to coating this bonding wire 45, and make be not subjected to that this second packing colloid 32 coats a plurality of plant bulb 42 to plant and connect corresponding a plurality of soldered ball 50.
On the first surface 11 and second surface 12 of aforesaid substrate 10, be to be laid with one first as shown in the figure respectively to refuse solder flux (Solder Mask) layer 43 and 1 second and refuse welding flux layer 44, wherein, this chip 20 is to connect to put at this first to refuse on the welding flux layer 43, make this first packing colloid 31 coat this chip 20 fully and first refuse welding flux layer 43 with this, second to refuse welding flux layer 44 be to be laid on this conductive trace layer 40 for this, be formed with a plurality of array type perforates to expose outside this a plurality of bulbs 42 of planting, and can connect corresponding soldered ball 50 in order to plant, in addition, this second refuse welding flux layer 44 in addition in the central the position be formed with an opening 44a, expose outside the through hole 13 of this substrate and be laid in this through hole 13 bonding wire portion 41 on every side, and width S 1 and the area of this opening 44a are larger than width S 2 and area in order to following die cavity 73 (see figure 3)s that form this second packing colloid 32.
This second size design of refusing the opening 44a of welding flux layer 44 formation, be feature of the present invention place, as Fig. 2 A, shown in Fig. 2 B, it is cutaway view and the bottom view (Fig. 2 A looks from the A-A of Fig. 2 B direction) that this packaging part 1 does not carry out the sealing operation as yet, prior art compared to Fig. 5 B, second of the present invention design to refuse welding flux layer opening 44a width S 1 bigger than the opening of existing packaging part as can be known, make this opening 44a corresponding to substrate through-hole 13 positions, except that the bonding wire portion 41 that can expose outside these conductive trace layer 40 edges, also can expose outside extra second surface in these bonding wire portion 41 both sides 12 and part conductive trace layer 40 respectively, make this second refuse between the edge of welding flux layer 44 and this bonding wire portion 41 a preset distance w is arranged, promptly expose outside the predetermined zone 60 of exposing on this second surface 12 and the conductive trace layer 40 as shown in the figure; Wherein, the width w that should predetermined expose zone 60 approximately can design between 0.2 to 0.8 millimeter (mm), and be the best with 0.4 millimeter (mm), this width w is above-mentioned this second reservation distance of refusing 41 in welding flux layer 44 edges and this bonding wire portion, makes this second refuse opening 44a that welding flux layer 44 forms and have and be equivalent to the predetermined width S 1 that exposes the width sum total in zone 60 in this substrate through-hole 13, this both sides bonding wire portion 41 and these both sides.
Therefore, this predetermined design that exposes zone 60 can be in order to prevent the excessive glue pollution problem on this substrate second surface 12.As shown in Figure 3, when this packaging part 1 carries out the sealing operation and makes this upper and lower mould 70,71 insert and put this substrate 10, though this moment, die cavity edge 72a, the 73a of this upper and lower mould were also unjustified, can make not cramping (NC) zone of the second surface 12 of this substrate not driving fit situation occur, just this will be as shown in the figure in order to the following die cavity edge 73a that forms second packing colloid 32, pastes neat position in this bonding wire portion 41 generally.Therefore, above-mentioned predetermined expose zone 60 will be by the surperficial 71a of this bed die, borrow its die cavity edge 73a to be separated into a narrow short channel 61, and then can when injecting glue, form the runner 61 of this second packing colloid 32, the size of this runner 61 is by this conductive trace layer 40 (or substrate second surface 12), this second surperficial 71a that refuses welding flux layer 44 and this bed die defines, the length w of its runner 61 is the rough above-mentioned predetermined width w that exposes zone 60 that equals, between 0.2 to 0.8 millimeter (mm), and be the best with 0.4 millimeter (mm), its height h then is equivalent to this second thickness h of refusing welding flux layer 44, between 0.02 to 0.03 millimeter (mm).
Therefore, design by the narrowed flow path 61 that in the sealing operation, forms, when this second packing colloid of forming by thermoplasticity or thermosetting resin 32, when flowing into the die cavity 73 of this bed die 71 via injecting glue, such as Merlon (Polycarbonate Ester), acrylic resin, the colloidal materials of polychlorostyrene methylene or polyesters resins such as (Polyester), it will be the viscous fluid that is a low reynolds number, coat this bonding wire 45 when its filling, and when entering this narrowed flow path 61, because this runner 61 is that a bore is anxious according to the channel that dwindles compared to this die cavity 73, according to hydromechanical theory, the viscosity of this viscous fluid can rise flow velocity was slowed down this moment, and cause the dissipation of energy, therefore, packing colloid 32 in this inflow narrowed flow path 61 will be close to be stagnated in this runner 61, and unlikely overflow is gone in this second pressing gap of refusing between welding flux layer 44 and this bottom mold surface 71a, also unlikely naturally this plant bulb 42 around produce the problem of excessive glue pollution.
After finishing above-mentioned sealing operation and planting the ball step, this encapsulating structure promptly becomes window type ball gird array semiconductor package part 1 as shown in Figure 1, by finding out among the figure, on above-mentioned, bed die 70, after 71 demouldings are removed, can fill up this second packing colloid 32 in this narrowed flow path 61, and it is filled surface 33 and will be close to according to the surperficial 71a of this bed die and be aligned in this and second refuse welding flux layer 44, therefore, compared to the existing semiconductor package part that produces the glue that overflows shown in Fig. 5 C, second packing colloid 32 that the present invention filled, meeting coats these many bonding wires 45 and applies and covers this predetermined exposing on the zone 60, and forms the deflection angle that conforms to die cavity 73 shapes of this bed die at this deposited edge that covers plane 33.At this moment, this second second packing colloid 32 of refusing not have on the welding flux layer 44 overflow.
The method for making of window type ball gird array semiconductor package part 1 of the present invention is shown in Fig. 4 A to Fig. 4 F, its step comprises: prepare a substrate 10 earlier shown in Fig. 4 A, it has a first surface 11 and an opposing second surface 12, and its central authorities have a through hole 13 that runs through this substrate 10; Also shown in Fig. 4 B, on this second surface 12, lay the conductive trace layer 40 of a patterning, and according to the layout of circuit, define a plurality of be that array arranges plant bulb 42, be laid in the bonding wire portion 41 of these through hole 13 both sides and be positioned at predetermined the expose zone 60 of this bonding wire portion 41 with respect to a side of this through hole 13, laying one first more respectively on this first surface 11 and conductive trace layer 40 refuses welding flux layer 43 and second and refuses welding flux layer 44, and make this first refuse that welding flux layer 43 forms openings and the through hole 13 that exposes outside this substrate 10, make this second refuse welding flux layer 44 and expose outside this a plurality of default bulbs 42 of planting, simultaneously, make this second refuse welding flux layer 44 and around this through hole 13, form an opening 44a, to expose outside this through hole 13, this a plurality of bonding wire portions 41 and this predetermined zone 60 of exposing; Then,, prepare a chip 20, its action face 21 is connect the end putting on the first surface 11 of this substrate 10 and cover this through hole 13 down, make electrical areas 23 outer being exposed in this through hole 13 on this action face 21 as Fig. 4 C; Shown in Fig. 4 D, form many bonding wires 45 that pass this through hole 13 for another example, with the electrical areas 23 that electrically connects this chip 20 bonding wire pairing portion 41 with it; Be the sealing operation in this method for making shown in Fig. 4 E, it is with on the icon, bed die 70,71 insert and put this substrate 10, make this chip 20 and this first refuse welding flux layer 43 and be installed with in the die cavity 72 of this mold 70, make this bonding wire 45 be installed with in the die cavity 73 of this bed die 71, and inject a packing colloid 31,32, first packing colloid 31 that order is formed on this first surface 11 coats this chip 20, second packing colloid 32 that order is formed on this second surface 12 coats this bonding wire 45, wherein, should predetermined expose zone 60 will form a narrowed flow path 61 with this conductive trace layer 40 by the surperficial 71a of this bed die, make this second packing colloid 32 flow into behind these runners 61 meeting viscous in wherein; At last, when above-mentioned sealing operation is finished and after this packing colloid 31,32 all solidified, can be shown in Fig. 4 F, carry out the demoulding and plant a plurality of soldered balls 50 on the bulb 42 its pairing planting, and as shown in the figure, form second packing colloid 32 that applies lid on the zone 60 this predetermined exposing, become a window type ball gird array semiconductor package part 1 that can prevent to overflow glue.
Therefore, the present invention utilizes to lay this second when refusing welding flux layer 44, by design in advance, make its than prior art expose outside extraly one have preliminary dimension expose the zone 60, can in follow-up sealing operation, form a narrowed flow path 61, avoid packing colloid 32 to plant on the bulb 42 to this because of the different glue that overflow in the cramping position of upper and lower mould 70,71, just this predetermined position of exposing zone 60 and narrowed flow path 61 or size are not only shown in above-mentioned embodiment, can change this yet and second refuse the opening 44a of welding flux layer 44 to change its design section.The edge that for example makes this opening 44a is corrugated non-straight edges, only need make this second opening 44a width S 1 of refusing welding flux layer 44 be slightly larger than die cavity 73 width S 2 of this bed die, make this second die cavity edge 73a that refuses the edge of welding flux layer 44 and this bed die 71 have distance w at interval, can in this sealing operation, enclose and be set to a narrowed flow path 61 and get final product.
In sum, window type ball gird array semiconductor package part and method for making and the used chip bearing member that prevents excessive glue of the present invention, really has the effect of avoiding excessive glue pollution, can promote its electric connection and transmission quality, hold concurrently simultaneously and can take the surface smoothness of this packaging part and clean outward appearance into account, fully solve the problem of existing packaging part and method for making.
Claims (25)
1. the method for making of a window type ball gird array semiconductor package part is characterized in that, this step comprises:
Prepare a sandwich layer, have a first surface and an opposing second surface, and have one and run through the through hole of this sandwich layer, and on this second surface, define a plurality of bonding wire portions and plant the bulb, and be positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; Lay one and refuse welding flux layer on this second surface, and order should be a plurality of plants the bulb and expose outside this and refuse outside the welding flux layer, simultaneously, this is refused welding flux layer and forms an opening, exposes outside this through hole, these a plurality of bonding wire portions and should be scheduled to expose the zone; Prepare at least one chip, this chip is connect put at the first surface of this sandwich layer and cover an end of this through hole, make this chip section be exposed at especially in this through hole; Form many bonding wires that pass this through hole, to electrically connect this chip and this bonding wire portion; Carry out a sealing operation, on the first surface of this sandwich layer, to form first packing colloid that coats this chip, on the second surface of this sandwich layer, form second packing colloid that coats this bonding wire, wherein, this is scheduled to expose the zone and will forms the narrowed flow path of this second packing colloid in this sealing operation; And plant at this and to plant a plurality of soldered balls on bulb.
2. method for making as claimed in claim 1 is characterized in that, this predetermined width that exposes the zone is between 0.2 to 0.8 millimeter.
3. method for making as claimed in claim 1 is characterized in that, this predetermined width that exposes the zone is to be the best with 0.4 millimeter.
4. method for making as claimed in claim 1 is characterized in that, this is scheduled to expose the zone is to be adjacent to this bonding wire portion.
5. method for making as claimed in claim 1 is characterized in that, this A/F of refusing welding flux layer is the die cavity width that is slightly larger than in order to the mould that forms this second packing colloid.
6. method for making as claimed in claim 1 is characterized in that, this second packing colloid is can be filled in this narrowed flow path, and makes this predetermined second packing colloid thickness that applies lid on the zone that exposes approximate the thickness that this refuses welding flux layer.
7. method for making as claimed in claim 1 is characterized in that, this method for making also is included in the second surface of this sandwich layer and this refuses to lay between welding flux layer the conductive trace layer of a patterning.
8. method for making as claimed in claim 1 is characterized in that, this method for making also is included in the first surface of this sandwich layer and this chip chamber and lays one and refuse welding flux layer.
9. method for making as claimed in claim 1 is characterized in that, this chip is to connect with its action face to put on the first surface of this sandwich layer.
10. window type ball gird array semiconductor package part, it is characterized in that, this semiconductor package part comprises: sandwich layer, have a first surface and an opposing second surface and have a through hole that runs through this sandwich layer, wherein, definition has a plurality of bonding wire portions and plants the bulb on this second surface, and is positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; At least one chip connects and puts at the first surface of this sandwich layer and cover an end of this through hole, and makes this chip section be exposed to especially in this through hole;
Refuse welding flux layer, on the second surface of this sandwich layer that is laid in, make these a plurality of bulbs of planting expose outside this and refuse outside the welding flux layer, simultaneously, this is refused welding flux layer and forms an opening to expose outside this through hole, these a plurality of bonding wire portions and should predetermined expose the zone; Many bonding wires pass this through hole to electrically connect this chip and this bonding wire portion;
Packing colloid forms first packing colloid coating this chip on the first surface of this sandwich layer, and forms second packing colloid cover this predetermined exposing on the zone to coat this bonding wire and to apply on the second surface of this sandwich layer; And
A plurality of soldered balls plant at this and plant on the bulb.
11. semiconductor package part as claimed in claim 10 is characterized in that, this predetermined width that exposes the zone is between 0.2 to 0.8 millimeter.
12. semiconductor package part as claimed in claim 10 is characterized in that, this predetermined width that exposes the zone is to be the best with 0.4 millimeter.
13. semiconductor package part as claimed in claim 10 is characterized in that, this is scheduled to expose the zone is to abut against this bonding wire portion.
14. semiconductor package part as claimed in claim 10 is characterized in that, this A/F of refusing welding flux layer is the die cavity width that is slightly larger than in order to the mould that forms this second packing colloid.
15. semiconductor package part as claimed in claim 10 is characterized in that, this is scheduled to expose the second packing colloid thickness of going up deposited lid in the zone is to approximate the thickness that this refuses welding flux layer.
16. semiconductor package part as claimed in claim 10 is characterized in that, this semiconductor package part comprises that also the second surface of this sandwich layer that is laid in and this refuse the pattern conductive trace layer between welding flux layer.
17. semiconductor package part as claimed in claim 10 is characterized in that, this semiconductor package part also comprises the welding flux layer of refusing of the first surface of this sandwich layer that is laid in and this chip chamber.
18. semiconductor package part as claimed in claim 10 is characterized in that, this chip is to connect with its action face to put on the first surface of this sandwich layer.
19. a chip bearing member that is used for window type ball gird array semiconductor package part is characterized in that, this chip bearing member comprises:
Sandwich layer has a first surface and an opposing second surface and has a through hole that runs through this sandwich layer;
Conductive trace layer on the second surface of this sandwich layer that is laid in and be that definition has a plurality of bonding wire portions and plants the bulb, and is positioned at predetermined the expose zone of this bonding wire portion with respect to a side of this through hole; And
Refuse welding flux layer, on this conductive trace layer that is laid in, make these a plurality of bulbs of planting expose outside this and refuse outside the welding flux layer, simultaneously, this is refused welding flux layer and forms an opening, to expose outside this through hole, these a plurality of bonding wire portions and should predetermined expose the zone.
20. chip bearing member as claimed in claim 19 is characterized in that, this chip bearing member is a substrate.
21. chip bearing member as claimed in claim 19 is characterized in that, this predetermined width that exposes the zone is between 0.2 to 0.8 millimeter.
22. chip bearing member as claimed in claim 19 is characterized in that, this predetermined width that exposes the zone is to be the best with 0.4 millimeter.
23. chip bearing member as claimed in claim 19 is characterized in that, this is scheduled to expose the zone is to abut against this bonding wire portion.
24. chip bearing member as claimed in claim 19 is characterized in that, this chip bearing member comprises that also the second surface of this sandwich layer that is laid in and this refuse the pattern conductive trace layer between welding flux layer.
25. chip bearing member as claimed in claim 19 is characterized in that, this chip bearing member also comprises the welding flux layer of refusing on the first surface of this sandwich layer that is laid in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031369448A CN100365782C (en) | 2003-05-23 | 2003-05-23 | Open-window type ball grid array semiconductor packaging elements and its producing method and used chip bearing elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031369448A CN100365782C (en) | 2003-05-23 | 2003-05-23 | Open-window type ball grid array semiconductor packaging elements and its producing method and used chip bearing elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1549319A true CN1549319A (en) | 2004-11-24 |
| CN100365782C CN100365782C (en) | 2008-01-30 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031369448A Expired - Lifetime CN100365782C (en) | 2003-05-23 | 2003-05-23 | Open-window type ball grid array semiconductor packaging elements and its producing method and used chip bearing elements |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100365782C (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416808C (en) * | 2005-09-15 | 2008-09-03 | 南茂科技股份有限公司 | Chip packaging body without kernel dielectric layer and stack chip packaging structure |
| CN100421243C (en) * | 2005-10-31 | 2008-09-24 | 南茂科技股份有限公司 | Extensive use type chip capsulation structure |
| CN100463157C (en) * | 2006-07-10 | 2009-02-18 | 南茂科技股份有限公司 | Encapsulation structure for preventing adhesive crystal glue from polluting wafer welding cushion |
| CN101350335B (en) * | 2007-07-19 | 2010-06-02 | 矽品精密工业股份有限公司 | Open window type ball grid array semiconductor packaging piece and web board structure used thereby |
| CN101419953B (en) * | 2007-10-23 | 2010-09-08 | 南茂科技股份有限公司 | Junction construction used for an encapsulation device |
| CN102034801A (en) * | 2010-06-04 | 2011-04-27 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN101894813B (en) * | 2009-05-22 | 2012-09-19 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacture method thereof |
| CN103515333A (en) * | 2012-06-25 | 2014-01-15 | 南亚科技股份有限公司 | Semiconductor package structure |
| CN107706158A (en) * | 2017-11-14 | 2018-02-16 | 睿力集成电路有限公司 | Semiconductor package and manufacture method |
| CN108447843A (en) * | 2017-07-13 | 2018-08-24 | 睿力集成电路有限公司 | Window-type ball grid array package assembling |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
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2003
- 2003-05-23 CN CNB031369448A patent/CN100365782C/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416808C (en) * | 2005-09-15 | 2008-09-03 | 南茂科技股份有限公司 | Chip packaging body without kernel dielectric layer and stack chip packaging structure |
| CN100421243C (en) * | 2005-10-31 | 2008-09-24 | 南茂科技股份有限公司 | Extensive use type chip capsulation structure |
| CN100463157C (en) * | 2006-07-10 | 2009-02-18 | 南茂科技股份有限公司 | Encapsulation structure for preventing adhesive crystal glue from polluting wafer welding cushion |
| CN101350335B (en) * | 2007-07-19 | 2010-06-02 | 矽品精密工业股份有限公司 | Open window type ball grid array semiconductor packaging piece and web board structure used thereby |
| CN101419953B (en) * | 2007-10-23 | 2010-09-08 | 南茂科技股份有限公司 | Junction construction used for an encapsulation device |
| CN101894813B (en) * | 2009-05-22 | 2012-09-19 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacture method thereof |
| CN102034801A (en) * | 2010-06-04 | 2011-04-27 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN102034801B (en) * | 2010-06-04 | 2012-10-10 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN103515333A (en) * | 2012-06-25 | 2014-01-15 | 南亚科技股份有限公司 | Semiconductor package structure |
| CN108447843A (en) * | 2017-07-13 | 2018-08-24 | 睿力集成电路有限公司 | Window-type ball grid array package assembling |
| CN108447843B (en) * | 2017-07-13 | 2023-08-18 | 长鑫存储技术有限公司 | Window type ball grid array package assembly |
| CN107706158A (en) * | 2017-11-14 | 2018-02-16 | 睿力集成电路有限公司 | Semiconductor package and manufacture method |
| CN107706158B (en) * | 2017-11-14 | 2023-11-03 | 长鑫存储技术有限公司 | Semiconductor packaging structure and manufacturing method |
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| CN100365782C (en) | 2008-01-30 |
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