CN1545129A - Cobalt silicide technique for realizing smooth of interface by preprocessing - Google Patents

Abstract

The invention belongs to the field of IC manufacturing technique. For being able to meet the requirements to junction leakage by updated technique, it need improve the existing cobalt silicide technique: one of the methods adopts ion injection pretreatment, injects different kinds of ions into a silicon substrate by a large dosage and at low energy, to influence the formation course of cobalt silicide so as to form a smoother-interface cobalt silicide. By this method, it can make cobalt silicide able to be used in 0.13 mum below techniques and achieve satisfactory performance.

Description

Realize the more level and smooth Cobalt silicide process in interface by preliminary treatment

Technical field

The invention belongs to field of IC technique, be specifically related to a kind of by the more level and smooth Cobalt silicide process in preliminary treatment realization interface.

Background technology

Along with the continuous development of integrated circuit, transistorized minimum feature is constantly dwindled.The length that present main flow technology 0.13 μ m technology is exactly a finger grid is 0.13 micron.When live width was constantly dwindled, in order to improve transistorized performance, the degree of depth of source/drain junction was also constantly reducing, and the degree of depth of tying under 0.13 micron technology has only tens nanometer.

All use salicide process techniques to reduce the resistance of source and drain areas and polycrystalline electrodes in the present integrated circuit fabrication process.Wherein under the 0.18/0.13 micron technology, use cobalt silicide (CoSi ₂) replacement Titanium silicide technology in the past.The outstanding advantage of Cobalt silicide process is exactly that resistance does not dwindle with live width and becomes big effect.But for the Cobalt silicide process, being not only and will keeping low resistance, under the very shallow situation of junction depth, guarantee that the electric leakage of knot is enough little, also is the great critical technological point that the Cobalt silicide process is faced.At present main method is exactly to regulate the thickness of Co film of sputter or the temperature of regulating rapid thermal annealing.And this causes probably and satisfies the resistance requirement and just do not satisfy the electric leakage requirement, satisfies the dilemma that electric leakage requires just not satisfy the resistance requirement.Particularly under the more shallow 0.09 μ m technology of junction depth, existingly can replace CoSi such as new module such as NiSi ₂In order to satisfy under renewal technology, need present cobalt silicide technology be made improvements the requirement of silicide.

Summary of the invention

The objective of the invention is to propose a kind ofly can satisfy face resistance, the integrated circuit cobalt silicide technology of may command junction leakage makes the interface between Cobalt silicide and the silicon substrate more level and smooth again, thereby suppresses junction leakage effectively, to be fit to the needs of littler live width, satisfy higher requirement on devices.

For the Cobalt silicide, it is to cause a main failure cause of electric leakage that RTP (quick high-temp annealing) causes cobalt silicide that the sharp projection of some similar " burrs " is arranged in forming process.In order to form more level and smooth interface, the method that can inject by ion obtains or effect decrystallized or that the grain growth size is dwindled, can guarantee that then it is enough little to leak electricity under the enough thick situation of film.Thereby make cobalt silicide technology in the more advanced technology below the 0.13 μ m, still obtain gratifying effect.

The cobalt silicide technology that the present invention proposes is before forming cobalt silicide, and the method by ion injects is injected into different types of ion in the substrate, takes general cobalt silicide to form technology subsequently, forms the more level and smooth cobalt silicide in interface.

The kind of above-mentioned injection ion can have multiple, as N, Ar, Ge, BF ₂Perhaps As or the like; The energy that ion injects can be 10 to 40keV, dosage desirable 1 * 10 ¹⁵/ cm ²To 9 * 10 ¹⁵/ cm ²

Description of drawings

Before Fig. 1 is the Co sputter, pretreated ion is carried out on the surface inject

After Fig. 2 was Co/Ti (N) sputter, whole silicon wafer was covered with metal.

Only there is silicide in Fig. 3 for silicon chip surface silicide distribution map after the selective corrosion among the figure on transistorized three electrode zones (source electrode, grid, drain electrode).

Drawing reference numeral: 1 is that transistor source, 2 is that transistor gate, 3 is that transistor drain, 4 is that metal or silicide, 5 are silicide, 6 expression ions injections.

Embodiment

1, after forming source-drain area, injects with some element, as N, Ar, perhaps with Ge, BF by ion ₂, As re-injects in the substrate.By or destroy the interface surface state or form the effect of Co diffusion impervious layer in substrate interior, the growth of cobalt silicide is impacted, form the more purpose of smooth interface thereby reach.Use BF ₂, As can divide p+, n+ zone to inject respectively when injecting.General low-yield, heavy dose of injection, the desirable 20-30keV of energy, the dosage desirable 2 * 10 of adopting ¹⁵/ cm ², or 8 * 10 ¹⁵/ cm ², as shown in Figure 1.

2, with the hydrofluoric acid cleaning silicon wafer surface of diluting.

3, the method by PVD forms the metal that silicide needs in the deposit of silicon chip surface full wafer, as 10nmCo (cobalt)/8nmTiN (titanium nitride), as shown in Figure 2.

4, adopt the method for rapid thermal annealing (RTP),,, form high-resistance silicide CoSi (cobalt silicide) as the 500-600 degree at lower temperature, different with the RTP formation temperature meeting of no pretreating process, as shown in Figure 2.

5, by APM (ammoniacal liquor hydrogen peroxide)/SPM (dioxysulfate water) residual metal is given and is eroded, as the Co on the spacer and (or) Ti (N), as shown in Figure 3.

6, by the rapid thermal annealing of higher temperature,, form low-resistance silicide CoSi at active area as the 800-900 degree ₂(cobalt disilicide).

Claims (3)

1, a kind of integrated circuit cobalt silicide technology that realizes that the interface is more level and smooth, it is characterized in that before forming cobalt silicide, method by ion injects is injected into different types of ion in the substrate, takes general cobalt silicide to form technology subsequently and forms the more level and smooth cobalt silicide in interface.

2,, it is characterized in that the kind of injecting ion has N, Ar, Ge, BF according to the described cobalt silicide technology of claim 1 ₂Perhaps As.

3, according to claim 1,2 described cobalt silicide technologies, it is characterized in that the energy that ion injects is 10 to 40keV, dosage is 1 * 10 ¹⁵/ cm ²To 9 * 10 ¹⁵/ cm ²

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