CN1542984A

CN1542984A - Power MOSFET device and method for manufacturing same

Info

Publication number: CN1542984A
Application number: CNA031241123A
Authority: CN
Inventors: 贡中元; 涂高维; 简凤佐; 黄彦智
Original assignee: HUARUI CO Ltd
Current assignee: HUARUI CO Ltd; Chino Excel Tech Corp
Priority date: 2003-04-29
Filing date: 2003-04-29
Publication date: 2004-11-03

Abstract

This invention relates to a double-ditch power metal oxide semiconductor fieldistor device including a drain of a silicon base plate, a crystal layer formed on the base plate, a gate formed by etching a gate ditch region in a trap zone formed above the crystal layer and a source doped region formed on the top of the trap, among which, a source ditch is included by etching the said doped region to form another ditch same height as the silicon base plate. The advantages are at low conductive resistance, high collapse voltage and high density and simplified manufacturing process not necessary to have the heat implantation.

Description

Power metal oxide semiconductor field-effect transistor device and manufacture method thereof

Technical field

The present invention relates to a kind of pair of aqueduct type power mos field effect transistor device and manufacture method thereof, and relate more particularly to a kind of in conjunction with gate ditching type and source channel formula power metal oxide semiconductor field-effect transistor device and manufacture method thereof, the advantage of low on-resistance, high breakdown voltage and highly dense intensity can be realized, and the complexity of manufacture process can be reduced.

Background technology

At present, power metal oxide semiconductor field-effect transistor device (powerMOSFET) is the switching device that is used for power electronic circuit.When said apparatus conducting (on), should have low conducting resistance (Ron); When said apparatus is closed (off), then should be able to keep out higher voltage, just has higher breakdown voltage (VB), in order to realize this purpose, the power MOSFET device is fabricated to rectilinear double diffusion structure usually, and has ＂ skew (drift) ＂ brilliant (epi) of heap of stone layer of little doping, yet, the breakdown voltage of said apparatus can increase along with the increase of the reduction of the doping content of deflection layer and thickness, thereby causes conducting resistance (Ron) to increase.

As shown in Figure 1, be the structure of known ditching type (gate ditching type) power MOSFET device.For convenience of description, will adopt N channel power MOSFET device to be described among the application, these explanations are equally applicable to P channel power MOSFET device, wherein only N need be changed into P and changes P into N getting final product.In known aqueduct type power MOSFET device fabrication, the technology of hydrogen annealing method (Hydrogen Annealing) that adopt are made irrigation canals and ditches more, make corner, irrigation canals and ditches below slyness, thereby roughness reduces, making originally, the intensive shortcoming in above-mentioned corner of electric field relaxes to some extent, so device is unlikely to collapse in the irrigation canals and ditches corner in advance, thereby improved the withstand voltage of apparatus structure, and because irrigation canals and ditches structural reason, the size (die size) of device chip area is littler by 2/3 than traditional MOSFET's, but thereby the closeness of lifting device unit cell (cell).After closeness improves, the number of whole unit cell in parallel will increase, thereby conducting resistance Ron (ds) is significantly reduced.Can find that from the structure of aqueduct type power MOSFET device utmost point junction resistance (Rj) does not exist, only remaining epitaxial layer resistance (Repi) and channel resistance (Rch) determine above-mentioned conducting resistance.In Fig. 1, shown substrate 1, epitaxial layer 2, trap 3, gate irrigation canals and ditches 4, source area 5 and source metal A16.

As shown in Figure 2, tie the structural representation of (super junction) power MOSFET device for the super utmost point.The design of wherein super utmost point knot mainly is in order to replace the epitaxial layer in the known power MOSFET device, by this super utmost point knot, can to improve the relation between device conducting resistance (Ron) and breakdown voltage (VB) widely.This type of power MOSFET device is also referred to as COOLMOS ^TMIn fact, after passing through with said structure replacement epitaxial layer, with regard to the epitaxial layer of same thickness, have super utmost point knot power MOSFET device and can bear higher voltage, its reason is: above-mentioned super utmost point knot power MOSFET device mainly is made up of the essential power MOSFET of Fig. 2 left side and the utmost point knot FET of Fig. 2 right-hand part, wherein utmost point knot FET (promptly, JFET) under the reverse bias effect, can make the pinch off (pinch-off) of exhaustion region more tight, thereby can bear than original higher voltage.In Fig. 2, comprise substrate 1, epitaxial layer 2, well region 2 ' and 3, gate 4 ' and source area 5.

So, being necessary to develop and a kind of power MOSFET device, it can have the advantage of low on-resistance, high breakdown voltage and the highly dense intensity of ditching type and super utmost point knot power MOSFET device simultaneously, and manufacture method is more simple.

Summary of the invention

Main purpose of the present invention is to provide a kind of pair of aqueduct type power mos field effect transistor device (double trench power MOSFET device) and manufacture method thereof, the wherein above-mentioned pair of aqueduct type power MOSFET device can be respectively in conjunction with the advantage of ditching type and super utmost point junction structure and in manufacture process, need not the step that any cloth is planted (implantation).

For achieving the above object, the invention provides a kind of pair of aqueduct type power mos field effect transistor device, it comprises: the drain of a silicon substrate; Be formed on the epitaxial layer on the above-mentioned silicon substrate, etching one gate irrigation canals and ditches district in the well region that above above-mentioned epitaxial layer, forms and the gate that forms; Be formed on the one source pole doped region of above-mentioned well region the top; Wherein, also comprise one source pole irrigation canals and ditches district, above-mentioned source channel district forms another irrigation canals and ditches by the above-mentioned source doping region of etching, and the degree of depth of above-mentioned another irrigation canals and ditches arrives above-mentioned silicon substrate place.

The present invention also provides the manufacture method of a kind of pair of aqueduct type power mos field effect transistor device, comprises the following step:

(1) preparation one silicon substrate forms an epitaxial layer, a well region and one source pole doped region in order as drain on above-mentioned silicon substrate;

(2), utilize photoetching process to etch a gate irrigation canals and ditches district with a light shield shading;

(3), utilize photoetching process etching one degree of depth on above-mentioned source doping region to arrive the one source pole irrigation canals and ditches district of above-mentioned silicon substrate with another light shield shading;

(4) on the above-mentioned source channel district of above-mentioned gate irrigation canals and ditches district and part, form the monoxide floor;

(5) above-mentioned gate irrigation canals and ditches district's filling one polysilicon at above-mentioned formation oxide skin(coating) forms a polycrystalline silicon gate pole, and at the above-mentioned polysilicon of above-mentioned source channel district's filling of above-mentioned part;

(6) on above-mentioned polycrystalline silicon gate pole, make a boron phosphorus silicate glass insulant; And

(7) deposition one metal on the surface of said apparatus forms the source electrode contact of a conductivity.

Description of drawings

Fig. 1 is the structural representation of known gate aqueduct type power mos field effect transistor device;

Fig. 2 is the structural representation of known super utmost point knot power metal oxide semiconductor field-effect transistor device;

Fig. 3 (a) is the manufacture process schematic diagram of of the present invention pair of aqueduct type power mos field effect transistor device to Fig. 3 (g), and wherein Fig. 3 (g) is the schematic diagram of apparatus of the present invention.

Embodiment

Hereinafter, to Fig. 3 (g), the manufacture process of of the present invention pair of aqueduct type power mos field effect transistor device is described with reference to Fig. 3 (a).In the epitaxial layer manufacture process of Fig. 3 (a), prepare a N ⁺Silicon substrate 1 is as the drain of said apparatus, at above-mentioned N ⁺Set gradually a N on the silicon substrate 1 ^-Epitaxial layer 2, a P ^-A trap 3 and a N ⁺Source doping region 5.In the gate irrigation canals and ditches manufacture process of Fig. 3 (b), utilize photoetching technique to etch a gate irrigation canals and ditches district 4 with light shield (not icon).In the source channel manufacture process of Fig. 3 (c), with another light shield (not icon) utilize the above-mentioned source doping region 5 of photoetching technique etching until the degree of depth of above-mentioned silicon substrate 1 form one source pole irrigation canals and ditches district 6 '.In the oxide skin(coating) manufacture process of Fig. 3 (d), the above-mentioned source channel district 6 of above-mentioned gate irrigation canals and ditches district 4 and part ' sidewall on form monoxide floor 7.In the polysilicon manufacture process of Fig. 3 (e), form a polycrystalline silicon gate pole 8 with the above-mentioned gate irrigation canals and ditches of a polysilicon 8 fillings district 4, and the above-mentioned source channel district 6 of the above-mentioned part of filling '.In boron phosphorus silicate glass (BPSG) manufacture process of Fig. 3 (f), on above-mentioned polycrystalline silicon gate pole 8, make a BPSG insulant 9, to protect above-mentioned polycrystalline silicon gate pole 8.At last, in the source metallization manufacture process of Fig. 3 (g), deposition one metal level 6 on the surface of said apparatus such as Al (aluminium), and finish two aqueduct type power mos field effect transistor devices that contain gate irrigation canals and ditches district and source channel district.

As above-mentioned, in Fig. 3 (g), finished according to of the present invention pair of aqueduct type power mos field effect transistor device, wherein include the structure of an aqueduct type power mos field effect transistor device, in said structure, have a N ⁺The drain of silicon substrate 1 is at above-mentioned N ⁺Form a N on the silicon substrate 1 ^- Epitaxial layer 2 is at above-mentioned N ^-The P that epitaxial layer 2 tops form ^-Etching one gate irrigation canals and ditches district 4 among the well region 3 and form gate forms a N above above-mentioned well region 3 ⁺ Source doping region 5, wherein above-mentioned N ⁺ Source doping region 5 etching one source pole irrigation canals and ditches 6 ', its degree of depth reaches above-mentioned N ⁺The silicon substrate place and form one source pole irrigation canals and ditches 6 '.In two ditching type structures like this, the well region that reaches silicon substrate deeply of above-mentioned source channel 6 ' in being equivalent to install as shown in Figure 2, this device comprises the super utmost point knot power metal oxide semiconductor field-effect transistor device of a utmost point junction field effect transistor again for both including the power metal oxide semiconductor field-effect transistor device.

In sum, the of the present invention pair of aqueduct type power mos field effect transistor device has the advantage of low on-resistance, high breakdown voltage and highly dense intensity.In addition, in its manufacture process, need not the step that cloth is planted, can reduce the complexity of manufacture process, and owing to omitted the step that enters high temperature furnace pipe, can avoid device in the process of high temperature, cause outdiffusion (out-diffusion) or outside the mix phenomenon of (out-dopping), make device more stable in electric property.

Though above-mentioned explanation is described and illustrated that the present invention also is applicable to P channel power MOSFET by N channel power MOSFET, wherein only need P changed into N and change N into P to get final product.In addition, the present invention also can be applicable to such as devices such as IGBT.

Claims

1. two aqueduct type power mos field effect transistor device, it comprises: the drain of a silicon substrate; Be formed on the epitaxial layer on the above-mentioned silicon substrate, etching one gate irrigation canals and ditches district in the well region that above above-mentioned epitaxial layer, forms and the gate that forms; Be formed on the one source pole doped region of above-mentioned well region the top; It is characterized in that, also comprise one source pole irrigation canals and ditches district, above-mentioned source channel district forms another irrigation canals and ditches by the above-mentioned source doping region of etching, and the degree of depth of above-mentioned another irrigation canals and ditches arrives above-mentioned silicon substrate place.

2. the manufacture method of two aqueduct type power mos field effect transistor devices comprises the following step: