CN1542943A - Method for making bottle-shape groove capacitor - Google Patents
Method for making bottle-shape groove capacitor Download PDFInfo
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- CN1542943A CN1542943A CNA031286771A CN03128677A CN1542943A CN 1542943 A CN1542943 A CN 1542943A CN A031286771 A CNA031286771 A CN A031286771A CN 03128677 A CN03128677 A CN 03128677A CN 1542943 A CN1542943 A CN 1542943A
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Abstract
This invention discloses a method for manufacturing bottle type trench capacitors. First of all, a conduction layer is filled in the lower part of a trench of a base surrounded by a doped layer, then an isolation layer is formed on the base and the upper part of the trench to cover them, a heat treatment is applied to form a doped zone adjacent to the doped layer as the bottom electrode then to non-isoclinicly etch the isolation layer to form a neck ring isolation layer on the trench upper part sidewall as a cover to remove the conduction layer and the doped layer to expose the doped zone surface then to partly etch the exposed doped zone to form a bottle trench. Finally, a rough polycrystal silicon layer and a capacitor dielectric layer are formed on the lower part and fill in a conduction layer as the top electrode.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, particularly relevant for a kind of manufacture method of bottle type channel capacitor (bottle-shaped trench capacitor) of semiconductor storage.
Background technology
In the present widely used semiconductor storage, for example (dynamicrandom access memory, DRAM), capacitor is to be made of across a megohmite insulant two conductive layer surfaces (being battery lead plate) to DRAM (Dynamic Random Access Memory).The ability of capacitor stores electric charge is that the dielectric constant by the surface area of the thickness of megohmite insulant, battery lead plate and megohmite insulant is determined.
Along with manufacture of semiconductor design in recent years all develops with the direction that improves the integrated circuit integration towards dwindling the semiconductor subassembly size, the area of base of memory cell in the internal memory (memory cell) must constantly reduce to be made integrated circuit can hold a large amount of memory cell and improves integration, but simultaneously, the battery lead plate of memory cell capacitor must have enough surface areas could store sufficient electric charge.
Yet, in size constantly under the situation of granular, groove in the DRAM (Dynamic Random Access Memory) stores node capacitance (trench storage node capacitance) also along with dwindling, and therefore must manage to increase storage capacitors to keep the good operating characteristics of internal memory.The method that has been widely used at present the storage capacitors that increases DRAM (Dynamic Random Access Memory) is for increasing the width of channel bottom, thereby forms a bottle type channel capacitor that can improve surface area.
Said method is after a groove first half forms the first half of a ring-type shielding layer with the protection groove with selective oxidation (selective oxidation), and the Lower Half of this groove is carried out wet etching to form the bottle type groove of diameter greater than the first half.Detailed it, conventional process is to have at the oxide layer and the laminated semiconductor-based end that nitration case constituted, form a groove with dry ecthing after, then laminated and this groove forms nitration case, oxide layer, compound crystal silicon layer and oxide layer along this in regular turn again.Yet above-mentioned processing procedure is numerous and diverse, needs repeatedly deposition step, all is not inconsistent economic benefit in manufacturing cost or on the time no matter be.Therefore need the method for a kind of processing procedure simplification with the formation bottle type channel capacitor of raising production capacity.In addition, in response to the dynamical demand of next generation internal memory, also need a kind of bottle type channel capacitor manufacture method that increases the capacitance of storage capacitors.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of bottle type channel capacitor of novelty, to simplify fabrication steps and to increase bottle capacitance of type channel capacitor.
In order to achieve the above object, the present invention adopts once oxidation layer deposition with the necklace oxide layer of while as the etch stop layer of making bottle type groove and bottle type channel capacitor.Moreover the present invention forms a coarse compound crystal silicon layer between flush type bottom electrode (buried plate) and capacitance dielectric layer, so as to the further surface area that increases bottle type groove.
According to above-mentioned purpose, the invention provides the manufacture method of a kind of bottle of type channel capacitor.At first, in a substrate, form a groove, insert one first conductive layer in lower half part of groove again, and first conductive layer is surrounded by a tool doped layer.Then, in substrate, reach groove first half compliance and form an insulating barrier to cover first conductive layer and tool doped layer.Afterwards, substrate is implemented a heat treatment to form a doped region with as a flush type bottom electrode in the substrate of contiguous tool doped layer.Then, the anisotropic etching insulating barrier to be forming a necklace insulating barrier at groove first half sidewall, and relends by the necklace insulating barrier and expose the doped region surface as the cover curtain to remove first conductive layer and tool doped layer in regular turn.Then, the partially-etched doped region that exposes is to constitute one bottle of type groove.At last, bottle type lower half part of groove in regular turn compliance form a coarse compound crystal silicon layer and a capacitance dielectric layer and insert one second conductive layer with as a top electrode.Wherein, said method more is included in and forms one the 3rd conductive layer and one the 4th conductive layer on second conductive layer in regular turn to fill up a bottle type groove.Wherein, second, third, and the 4th conductive layer can be the compound crystal silicon layer of doping.
Moreover, after forming coarse compound crystal silicon layer, more comprise and implement a gas phase doping (gas phasedoping, GPD) step of Chu Liing.
Moreover first conductive layer can be a compound crystal silicon layer.The tool doped layer can be an arsenic doping silex glass (ASG).Insulating barrier can be for by tetraethyl-metasilicate (tetraethyl orthosilicate, TEOS) formed oxide.
Moreover heat treatment temperature is 900 ℃ to 1100 ℃ scope.
Description of drawings
Fig. 1 a-1h is the generalized section that shows according to the manufacture method of the bottle type channel capacitor of the embodiment of the invention.
Symbol description:
The 100-substrate
101-pad silicon oxide layer
The 102-silicon nitride layer
The 103-cover curtain layer
The 104-groove
The 105-depression
The 106-silicon nitride
108,108 ', 108 "-the tool doped layer
110,120,122-conductive layer
111-flush type bottom electrode
The 112-insulating barrier
112 ', 112 "-the necklace insulating barrier
113-bottle type groove
114,114 '-thick behaviour's compound crystal silicon layer
116,116 "-dielectric layer
The 118-top electrode
119-bottle type channel capacitor
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Below cooperate 1a to be applicable to a storage device, for example DRAM to the manufacture method of the bottle type channel capacitor of the 1h figure explanation embodiment of the invention.
At first, as shown in Figure 1a, provide a substrate 100, for example a silicon base.On substrate 100 surfaces, form a cover curtain layer 103.As shown in FIG., cover curtain layer 103 can be made up of the thicker silicon nitride layer 102 of one deck pad silicon oxide layer 101 and one deck.Wherein, about about 100 dusts of thickness () of pad silicon oxide layer 101, and its formation method can be thermal oxidation method deposition and forms.The thickness of silicon nitride layer 102 is about the scope of 1000 to 2000 dusts, and can utilize Low Pressure Chemical Vapor Deposition, with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.Then, in cover curtain layer 103, form plural opening by known little shadow and etch process, again with cover curtain layer 103 as etch mask, carry out the anisotropic etching processing procedure, reactive ion etching (reactive ionetching for example, RIE), the substrate 100 of the opening of etch mask layer 103 below and form plural groove.Herein, for simplicity of illustration, only with a groove 104 expressions.
Next, shown in Fig. 1 b, (bufferhydrofluoric acid, BHF) isotropic etching pad silicon oxide layer 101 to the one set degree of depth are for example in the scope of 15 to 40 dusts (), to form a recess 105 optionally to utilize buffered hydrofluoric acid.Then, insert silicon nitride 106 at recess.This silicon nitride 106 is to be subjected to etching in order to neonychium silicon oxide layer 101 in the subsequent etch processing procedure, avoids the tack of silicon nitride layer 102 to reduce and peels off.Afterwards, by known deposition technique, (chemical vapor deposition CVD), reaches groove 104 inner surface compliances and forms a tool doped layer 108 on cover curtain layer 103 in for example chemical vapour deposition (CVD).In the present embodiment, this tool doped layer 108 can be the oxide layer of an arsenic doped or claims the arsenic doping silex glass that (arsenicsilicate glass, ASG), its thickness is in the scope of 200 to 400 dusts.
Next, shown in Fig. 1 c, by known deposition technique, CVD for example forms a conductive layer (not illustrating) on tool doped layer 108, a compound crystal silicon layer for example, and insert in the groove 104.Afterwards, by a milled processed, cmp (chemical mechanicpolishing for example, CMP), remove unnecessary conductive layer and tool doped layer 108 on the cover curtain layer 103, reach at groove 104 sidewalls and bottom with the conductive layer that in groove 104, stays part and stay tool doped layer 108 ' partly.Then, the set degree of depth of the conductive layer in the etch-back groove 104, for example 1 micron (μ m) is to stay the conductive layer 110 of part in groove 104 Lower Halves.
Next, shown in Fig. 1 d, as cover curtain layer, the tool doped layer 108 ' of conductive layer 110 tops is removed in etching, to stay the tool doped layer 108 around conductive layer 110 in groove 104 Lower Halves with conductive layer 110 ".Then, by conventional deposition technique, for example low-pressure chemical vapor deposition (low-pressure CVD, LPCVD), on cover curtain layer 103 and groove 104 first half inner surface compliances form an insulating barrier 112, to cover conductive layer 110 and tool doped layer 108 ".Herein, insulating barrier 112 can be for by tetraethyl-metasilicate (tetraethyl orthosilicate, TEOS) formed oxide, and its thickness is in the scope of 100 to 300 dusts.
Then, a heat treatment is implemented in substrate 100, with tool doped layer 108 " in doped chemical, arsenic for example, high temperature drives in and forms a doped region 111 in the contiguous substrate 100.This doped region 111 is the usefulness that is made for a flush type bottom electrode (buried bottom plate).In the present embodiment, heat treated temperature is 900 ℃ to 1100 ℃ scope, and preferable temperature is about 1050 ℃.
Next, shown in Fig. 1 e, by anisotropic etching, reactive ion etching (reactive ion etching for example, RIE), remove the insulating barrier 112 of cover curtain layer 103 tops and groove 104 bottoms (conductive layer 110 tops), to form a necklace (collar) insulating barrier 112 ' at groove 104 first half sidewalls and to expose conductive layer 110 and the tool doped layer 108 of part ".
Next, shown in Fig. 1 f, utilize necklace insulating barrier 112 ' as covering curtain to remove conductive layer 110 and tool doped layer 108 in regular turn " and expose doped region 111 surfaces.In the present embodiment, be earlier to remove conductive layer 110 in the groove 104 by dry ecthing, then utilize again gas phase hydrofluoric acid (vaporhydrofluoric acid, VHF) removal tool doped layer 108 ".Then, utilize necklace insulating barrier 112 ' to carry out isotropic etching equally, for example use ammonium hydroxide (NH as the cover curtain
4OH), constitute the more roomy bottle type groove 113 in a bottom with the partially-etched doped region that exposes 110 as etchant.
Then, by conventional deposition technique, LPCVD for example, under 565 ℃ to 585 ℃ growth temperature, above cover curtain layer 103, reach bottle type groove 113 inner surface compliances and form a coarse compound crystal silicon (rugged polysilicon) layer 114, or title dome-type grain silicon (hemisphericalgrained silicon, HSG), in order to increase the surface area of flush type bottom electrode 111.Afterwards, to coarse compound crystal silicon layer 114 implement a gas phase doping (gas phase doping, GPD), with the concentration difference between the compound crystal silicon layer 114 that reduces unadulterated necklace insulating barrier 112 ' and doping.Then, can form a dielectric layer 116 by LPCVD compliance on coarse compound crystal silicon layer 114 equally, for example the silicon nitride layer of Can Zaing, nitrogenize silicon/oxidative silicon (NO) is laminated or silicon oxide/silicon nitride/silicon oxide (ONO) is laminated.
Next, shown in Fig. 1 g, by conventional deposition technique, CVD for example forms a conductive layer (not illustrating) above cover curtain layer 103, the compound crystal silicon layer of Can Zaing for example, and insert a bottle type groove 113.Afterwards, the etch-back conductive layer, with the conductive layer 118 that stays part in bottle type groove 113 Lower Halves with as a top electrode.Then, the dielectric layer 116 that can expose by hot phosphoric acid or other suitable solution removal conductive layer 118 tops, to stay the dielectric layer 116 ' of part in bottle type groove 113 Lower Halves, it is the usefulness that is made for capacitance dielectric layer.Afterwards, can remove the coarse compound crystal silicon layer 114 of capacitance dielectric layer 116 ' top, finish the making of bottle type channel capacitor 119 of the present invention with the coarse compound crystal silicon layer 114 ' that stays part in bottle type groove 113 Lower Halves by RIE.
At last, shown in Fig. 1 h, by conventional deposition technique, CVD for example forms a conductive layer (not illustrating) above cover curtain layer 103, the compound crystal silicon layer of Can Zaing for example, and insert bottle type groove 113 first halves (bottle type channel capacitor 119 tops).Then, this conductive layer of etch-back with the conductive layer 120 that stays part with as a conductor layer No.1.Afterwards,, remove the necklace insulating barrier 112 ' of its top and stay the necklace insulating barrier 112 of part as cover curtain with conductive layer 120 ".Next, equally by CVD, above cover curtain layer 103, form a conductive layer (not illustrating), the compound crystal silicon layer of Can Zaing for example, and fill up a bottle type groove 113, and by a milled processed, for example CMP, the conductive layer of removing cover curtain layer 103 tops to be staying the conductive layer 122 of part in bottle type groove 113, so as to as one second conductor layer.
The method according to this invention only adopts once oxidation layer deposition, with a etch stop layer as making bottle type groove, simultaneously, with the necklace oxide layer of this etch stop layer as bottle type channel capacitor.Therefore, can simplify fabrication steps and then reduction cost of manufacture and increase production capacity.Moreover the present invention forms a coarse compound crystal silicon layer between flush type bottom electrode (buried plate) and capacitance dielectric layer, therefore can further increase bottle surface area of type groove and increases bottle capacitance of type channel capacitor.That is, the usefulness of raising storage device.
Claims (24)
1. the manufacture method of a bottle type channel capacitor comprises the following steps:
In a substrate, form a groove;
Insert one first conductive layer in this lower half part of groove, and this first conductive layer is surrounded by a tool doped layer;
In this substrate, reach this groove first half compliance and form an insulating barrier to cover this first conductive layer and this tool doped layer;
This substrate is implemented a heat treatment to form a doped region with as a flush type bottom electrode in this substrate of contiguous this tool doped layer;
This insulating barrier of anisotropic etching is to form a necklace insulating barrier at this groove first half sidewall;
Expose this doped region surface as the cover curtain to remove this first conductive layer and this tool doped layer in regular turn by this necklace insulating barrier;
The partially-etched doped region that this exposes is to constitute one bottle of type groove;
This bottle type lower half part of groove in regular turn compliance form a coarse compound crystal silicon layer and a capacitance dielectric layer and insert one second conductive layer with as a top electrode.
2. the manufacture method of bottle according to claim 1 type channel capacitor more is included in and forms one the 3rd conductive layer and one the 4th conductive layer on this second conductive layer in regular turn to fill up this bottle type groove.
3. the manufacture method of bottle type channel capacitor according to claim 2, wherein the 3rd and the 4th conductive layer is the compound crystal silicon layer that mixes.
4. the manufacture method of bottle type channel capacitor according to claim 1, wherein this first conductive layer is a compound crystal silicon layer.
5. the manufacture method of bottle type channel capacitor according to claim 1, wherein this tool doped layer is an arsenic doping silex glass (ASG).
6. the manufacture method of bottle type channel capacitor according to claim 5 is wherein removed this tool doped layer by gas phase hydrofluoric acid (VHF).
7. the manufacture method of bottle type channel capacitor according to claim 1, wherein this insulating barrier is by the formed oxide of tetraethyl-metasilicate (TEOS).
8. the manufacture method of bottle according to claim 1 type channel capacitor, wherein this heat treatment temperature is 900 ℃ to 1100 ℃ scope.
9. the manufacture method of bottle according to claim 1 type channel capacitor, wherein by ammonium hydroxide with the partially-etched doped region that this exposes.
10. the manufacture method of bottle type channel capacitor according to claim 1, wherein this second conductive layer is the compound crystal silicon layer that mixes.
11. the manufacture method of bottle type channel capacitor according to claim 1, wherein this capacitance dielectric layer comprises a silicon nitride layer.
12. the manufacture method of bottle type channel capacitor according to claim 1 wherein after forming this coarse compound crystal silicon layer, more comprises and implements the step that a gas phase doping (GPD) is handled.
13. the manufacture method of a bottle type channel capacitor comprises the following steps:
One substrate is provided, and covering one has the cover curtain layer of an opening on it;
This substrate of this opening below of etching is to form a groove therein;
Insert a compound crystal silicon layer in this lower half part of groove, and this compound crystal silicon layer is surrounded by a silicon oxide layer that mixes;
On this cover curtain layer, reach this groove first half compliance and form an insulating barrier to cover the silicon oxide layer of this compound crystal silicon layer and this doping;
This substrate is implemented a heat treatment to form a doped region with as a flush type bottom electrode in this substrate of the silicon oxide layer of contiguous this doping;
This insulating barrier of anisotropic etching is to form a necklace insulating barrier at this groove first half sidewall;
Expose this doped region surface as the cover curtain to remove this compound crystal silicon layer and this tool doped layer in regular turn by this necklace insulating barrier;
The partially-etched doped region that this exposes is to constitute one bottle of type groove;
This bottle type lower half part of groove in regular turn compliance form a coarse compound crystal silicon layer and a capacitance dielectric layer and insert one first compound crystal silicon layer that mixes with as a top electrode;
On this first compound crystal silicon layer that mixes, form one second compound crystal silicon layer that mixes and one the 3rd compound crystal silicon layer that mixes in regular turn to fill up this bottle type groove.
14. the manufacture method of bottle type channel capacitor according to claim 13, wherein this cover curtain layer is made of a pad silicon oxide layer and a silicon nitride layer in regular turn.
15. the manufacture method of bottle type channel capacitor according to claim 14 wherein before inserting this compound crystal silicon layer, more comprises the following steps:
The set degree of depth of this pad silicon oxide layer to of isotropic etching is to form a recess;
Insert silicon nitride at this recess.
16. the manufacture method of bottle type channel capacitor according to claim 15 wherein should the pad silicon oxide layer by buffered hydrofluoric acid (BHF) etching.
17. the manufacture method of bottle type channel capacitor according to claim 15, wherein this set degree of depth is in the scope of 15 to 40 dusts.
18. the manufacture method of bottle type channel capacitor according to claim 13, wherein the silicon oxide layer of this doping is an arsenic doping silex glass (ASG).
19. the manufacture method of bottle type channel capacitor according to claim 18 is wherein removed the silicon oxide layer of this doping by gas phase hydrofluoric acid (VHF).
20. the manufacture method of bottle type channel capacitor according to claim 13, wherein this insulating barrier is by the formed oxide of tetraethyl-metasilicate (TEOS).
21. the manufacture method of bottle according to claim 13 type channel capacitor, wherein this heat treatment temperature is 900 ℃ to 1100 ℃ scope.
22. the manufacture method of bottle according to claim 13 type channel capacitor, wherein by ammonium hydroxide with the partially-etched doped region that this exposes.
23. the manufacture method of bottle type channel capacitor according to claim 13, wherein this capacitance dielectric layer comprises a silicon nitride layer.
24. the manufacture method of bottle type channel capacitor according to claim 13 wherein after forming this coarse compound crystal silicon layer, more comprises and implements the step that a gas phase doping (GPD) is handled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031286771A CN1542943A (en) | 2003-04-29 | 2003-04-29 | Method for making bottle-shape groove capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031286771A CN1542943A (en) | 2003-04-29 | 2003-04-29 | Method for making bottle-shape groove capacitor |
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| CN1542943A true CN1542943A (en) | 2004-11-03 |
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| CNA031286771A Pending CN1542943A (en) | 2003-04-29 | 2003-04-29 | Method for making bottle-shape groove capacitor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7683416B2 (en) | 2007-01-18 | 2010-03-23 | International Business Machines Corporation | Post STI trench capacitor |
| US7682922B2 (en) | 2007-01-18 | 2010-03-23 | International Business Machines Corporation | Post STI trench capacitor |
| US20210210386A1 (en) * | 2014-11-24 | 2021-07-08 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Capacitor and method for producing the same |
-
2003
- 2003-04-29 CN CNA031286771A patent/CN1542943A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7683416B2 (en) | 2007-01-18 | 2010-03-23 | International Business Machines Corporation | Post STI trench capacitor |
| US7682922B2 (en) | 2007-01-18 | 2010-03-23 | International Business Machines Corporation | Post STI trench capacitor |
| US20210210386A1 (en) * | 2014-11-24 | 2021-07-08 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Capacitor and method for producing the same |
| US11854890B2 (en) * | 2014-11-24 | 2023-12-26 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Capacitor and method for producing the same |
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