CN1237600C - Method for forming buried electrode board - Google Patents
Method for forming buried electrode board Download PDFInfo
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- CN1237600C CN1237600C CN 02147303 CN02147303A CN1237600C CN 1237600 C CN1237600 C CN 1237600C CN 02147303 CN02147303 CN 02147303 CN 02147303 A CN02147303 A CN 02147303A CN 1237600 C CN1237600 C CN 1237600C
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- lead plate
- battery lead
- bottle type
- protective layer
- crystal silicon
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Abstract
The present invention relates to a method for forming a buried layer electrode plate, which is suitable for a base with a cushion layer structure. A bottle type ditch groove embedded into the base is formed on the established position of the base. Procedures comprise (a) a protective layer is formed on one side wall at the upper half part of the bottle type ditch groove along the cushion layer structure around the bottle type ditch groove; (b) an adulterated hemispherical crystal silicon grain layer is formed on the side wall and the bottom of the bottle type ditch groove along the protective layer; (c) a hemispherical crystal silicon grain layer positioned on the protective layer is removed, and hemispherical crystal silicon grain layers positioned on the side wall and the bottom at the lower half part of the bottle type ditch groove are reserved; (d) a coverage layer is formed on the protective layer; (e) ions adulterated at the hemispherical crystal silicon grain layer are driven and diffused into a silicon base, and a buried layer electrode plate is formed in the side wall at the lower half part of the bottle type ditch groove.
Description
Technical field
The present invention relates to the method for a kind of formation buried regions battery lead plate (Buried Plate), be particularly to a kind of with hemisphere crystal silicon grain (Hemispherical silicon Grain; HSG) by driving in tempering (Drive InAnneal) at dynamic random access memory (Dynamic Random Access Memory; DRAM) form the method for buried regions battery lead plate in the trench capacitor (trench capacitor).
Background technology
At present in the processing procedure of semiconductor RAM (semiconductor Integrated circuits), particularly 64 and the making of 256Mb memory chip, extensively with deep trench (deep trench) definition reservior capacitor (storage capacitors).The essential structure of this reservior capacitor is the deep trench that is formed in the silicon substrate of doping for, and the surperficial holomorphism in whole inside of this deep trench becomes a dielectric layer, and this deep trench inside is to fill up with doped polycrystalline silicon (doped silicon), and this doped polycrystalline silicon/dielectric layer/doped polycrystalline silicon then forms so-called reservior capacitor.Lasting granular along with capacitor sizes, the thickness of above-mentioned dielectric layer also must be along with dwindling to keep its capacitance, and therefore the voltage of whole dielectric layer also must significantly dwindle the voltage collapse effect (voltage breakdown effect) to avoid not expecting.Reduce in order to reach voltage, thereby around above-mentioned reservior capacitor bottom, form a doped region (doped area), just so-called buried regions battery lead plate.
The formation method of buried regions battery lead plate in the at present general plough groove type dynamic random access memory means, shown in Fig. 1 a-1h, at first, have one at cushion layer structure A (pad stacked layer) the semiconductor-based end 100, form at both allocations one goed deep into the groove 140 of substrate, wherein cushion layer structure A comprises a pad oxide 130 and a pad nitration case 120.Then, after this groove first half forms as shown in Figure 1a protective layer 110, enlarge the Lower Half that this groove do not cover by this protective layer and form the bottle type groove 150 shown in Fig. 1 b with etching.
Next, shown in Fig. 1 c and 1d, silica glass (the Arsenic Doped Silicon DioxideGlass that forms an arsenic doped in regular turn along the sidewall and the bottom of this protective layer 110 and this bottle type groove 150; ASG) layer 160 and one tetraethoxysilane (TEOS) layer 170, drive in (drivein) then and form the internal electrical pole plate 180 shown in Fig. 1 e in the interior of this bottle type groove.
Then; after shown in Fig. 1 f, removing the silica glass layer 160 and tetraethoxysilane layer 170 of arsenic doped; sidewall and bottom deposit at this protective layer 110 and this bottle type groove 150 forms 190 layers of semispherical silicon crystal grain shown in Figure 19 comprehensively; at last; shown in Fig. 1 h; remove the semispherical silicon crystal grain layer that is positioned on this protective layer, and keep the semispherical silicon crystal grain layer that is positioned on this bottle type trenched side-wall and the bottom.
Yet, above-mentioned conventional process, under the prerequisite that process window (Process Window) is more and more tiny at present, owing to must in very trickle groove, form the silica glass layer and the tetraethoxysilane layer of arsenic doped in regular turn, be easy in groove, cause prominent outstanding (overhang), to bottle type groove successive process is disadvantageous, easily increase the degree of difficulty of processing procedure, thereby conventional method is inapplicable gradually.
Summary of the invention
The objective of the invention is for a kind of manufacture method that can avoid the buried regions battery lead plate of known prominent outstanding problem is provided, this method can reduce and form the required step of buried regions battery lead plate, to form the good trench capacitor of quality.
Purpose of the present invention can realize by following measure:
A kind of method that forms the buried regions battery lead plate is applicable to that one has the substrate of cushion layer structure, and forms a bottle type groove that gos deep into substrate on both allocations of this substrate, comprises the steps:
(a) form a protective layer on the sidewall of the cushion layer structure around this bottle type groove and this bottle type groove first half;
(b) on the sidewall of this protective layer and this bottle type groove and bottom, form doping hemisphere crystal silicon granulosa;
(c) remove the hemisphere crystal silicon granulosa that is positioned on this protective layer, be positioned at the sidewall of bottle Lower Half of type groove and the hemisphere crystal silicon granulosa on the bottom and keep;
(d) on this protective layer, form cover layer; And
(e) drive in and make the ions diffusion that is doped in hemisphere crystal silicon granulosa in silicon base and form the buried regions battery lead plate in the inside of the sidewall of the Lower Half of this bottle type groove.
Said method comprises that also one removes this tectal step.
The described impurity that is doped in hemisphere crystal silicon granulosa is arsenic.
Described cover layer is a tetraethoxysilane.
Described protective layer is a silicon nitride.
Described bed course structure comprises a pad oxide and a pad nitration case.
Described bed course structure is to carry out with chemical vapour deposition (CVD).
A kind of method that forms the buried regions battery lead plate is applicable to the semiconductor substrate, comprises the steps:
(a) in this substrate, form a cushion layer structure in regular turn;
(b) this cushion layer structure and this substrate are set, and on both allocations of this substrate, form a groove that gos deep into substrate;
(c) form the first half that a protective layer covers this pad nitride layer and this trenched side-wall;
(d) form one bottle of type groove in this lower half part of groove;
(e) sidewall along this protective layer and this bottle type groove forms the hemisphere crystal silicon granulosa that mixes;
(f) remove the hemisphere crystal silicon granulosa that is positioned on this protective layer and keep the hemisphere crystal silicon granulosa that is positioned on this bottle type trenched side-wall;
(g) on this protective layer, form a cover layer; And
(h) the hemisphere crystal silicon granulosa that is positioned at bottle type groove is applied drive in, make the ion that mixes in the hemisphere crystal silicon granulosa in bottle type trenched side-wall, form the buried regions battery lead plate toward the silicon base diffusion.
Said method comprises that also one removes this tectal step.
The described impurity that is doped in hemisphere crystal silicon granulosa is arsenic.
Described cover layer is a tetraethoxysilane.
Described protective layer is a silicon nitride.
The formed bed course structure of described step (a) comprises a pad oxide, and a pad nitration case.
Described bed course structure is to carry out with chemical vapour deposition (CVD).
The present invention has following advantage compared to existing technology:
The method of formation buried regions battery lead plate provided by the invention; by the step of omitting the silica glass that forms arsenic doped; and with the hemisphere crystal silicon grain that mixes as the ion source that forms the buried regions battery lead plate; said method can avoid must forming in the known technology silica glass of arsenic doped; tetraethoxysilane and protective layer are in groove; cause prominent outstanding problem easily; simultaneously because reduce fabrication steps; and save manufacturing cost and time; to the miniaturization of dynamic random access memory (DRAM) overall process, especially has concrete effect less than 0.11 μ m.
Description of drawings
Fig. 1 a-1h is the processing procedure profile that known technology is made the buried regions battery lead plate.
Fig. 2 a-2g is the processing procedure profile of the formation buried regions battery lead plate method of embodiments of the invention.
Concrete execution mode
See also Fig. 2 a-2g, it shows the processing procedure profile of the formation buried regions battery lead plate method of embodiments of the invention.
At first, provide semiconductor substrate 200, for example form by the silicon material, for convenience of description for the purpose of, be example at this with a silicon base.Then, on this semiconductor-based end 200, form bed course structure A, for example with chemical vapour deposition (CVD) (Chemical Vapor Deposition; CVD) silicon oxide layer deposited 230 reaches deposition one insulating barrier such as silicon nitride layer 220 on the surface of silicon oxide layer 230 on surface, the semiconductor-based ends 200 in regular turn, and this bed course structure A is as the hard cover screen that is used for the deep trench etching step at this.
Then, in this pad stromatolithic structure A, form a cover curtain opening, to expose the part semiconductor substrate surface, for example can utilize micro-photographing process such as the coating of photoresist and exposure imaging to form a photoresistance pattern earlier, and then utilize reactive ion etching (Reactive Ion Etching on this pad stromatolithic structure surface; RIE) or electric paste etching this pad stromatolithic structures of etching such as (Plasma Etching) to form a cover curtain opening.Next, expose the semiconductor-based end with this cover curtain opening of electric paste etching, thereby form the groove 240 shown in Fig. 2 a.The method of above-mentioned formation groove is the anisotropic dry ecthing (Anisotropic Dry Etching) that comprises as reactive ion etching method and electric paste etching etc.
Next; after forming an insulation material layer along the sidewall of this groove and bottom; the Lower Half of this groove is filled up with photoresist and expose; remove the photoresist part of this exposure then; remove the insulation material layer that is positioned on this lower half part of groove sidewall simultaneously, and shown in Fig. 2 a, on the sidewall of the first half of this groove 240, form a protective layer 210; its material is to select from insulating material, for example silicon dioxide (SiO
2), silicon nitride (SiN) etc., and its thickness is about 100A.Above-mentioned protective layer is in order to protect the first half of this groove, to prevent to undermine silicon base in the follow-up step that drives in.The degree of depth of the thickness of this protective layer and the covering groove first half wherein, there is no particular restriction, decides on processing procedure is required.
Then, do not carry out wet etching, and form the bottle type groove 250 shown in Fig. 2 b that a diameter enlarges at the Lower Half that is covered of this groove 240 by this protective layer 210.Then, formation is doped with the hemisphere crystal silicon granulosa 290 of arsenic (As) to cover this protective layer 210 and whole trenched side-wall and bottom, shown in Fig. 2 c.
Then; shown in Fig. 2 d; to wait tropism's dry-etching method to remove the hemisphere crystal silicon granulosa that is positioned on this protective layer 210; and keep be positioned at the hemisphere crystal silicon granulosa of this bottle type groove 250 sidewalls and bottom after; form tetraethoxysilane cover layer 270 with low-pressure chemical vapor deposition method and cover this protective layer 210 and hemisphere crystal silicon granulosa 290, shown in Fig. 2 e.The formation of this cover layer 270 be carry out making when tempering drives in arsenic in the hemisphere crystal silicon grain can folk prescription to the sidewall that is diffused into doleiform groove 250.
Then, this hemisphere crystal silicon granulosa 290 is driven in, make the ions diffusion (out diffuse) that is entrained in the hemisphere crystal silicon granulosa to the sidewall of this bottle type groove 250, around the Lower Half of this bottle type groove 250, form the buried regions battery lead plate 280 shown in Fig. 2 f.The above-mentioned method that drives in is to drive in method with tempering to carry out.
After finishing the buried regions battery lead plate of above-mentioned formation, also can shown in Fig. 2 g, remove this tetraethoxysilane cover layer 270 optionally with conventional method.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, thus protection scope of the present invention with claims the person of being defined be as the criterion.
Claims (7)
1, a kind of method that forms the buried regions battery lead plate is applicable to that one has the substrate of cushion layer structure, and forms a bottle type groove that gos deep into substrate on both allocations of this substrate, comprises the steps:
(a) form a protective layer on the sidewall of the cushion layer structure around this bottle type groove and this bottle type groove first half;
(b) on the sidewall of this protective layer and this bottle type groove and bottom, form doping hemisphere crystal silicon granulosa;
(c) remove the doping hemisphere crystal silicon granulosa that is positioned on this protective layer, be positioned at the sidewall of bottle Lower Half of type groove and the hemisphere crystal silicon granulosa on the bottom and keep;
(d) on this protective layer, form cover layer; And
(e) drive in and make the ions diffusion that is doped in this doping hemisphere crystal silicon granulosa in silicon base and form the buried regions battery lead plate in the inside of the sidewall of the Lower Half of this bottle type groove.
2, the method for formation buried regions battery lead plate as claimed in claim 1 is characterized in that also comprising that one removes this tectal step.
3, the method for formation buried regions battery lead plate as claimed in claim 1 is characterized in that described doping hemisphere crystal silicon granulosa contains arsenic impurities.
4, the method for formation buried regions battery lead plate as claimed in claim 1 is characterized in that described cover layer is a tetraethoxysilane.
5, the method for formation buried regions battery lead plate as claimed in claim 1 is characterized in that described protective layer is a silicon nitride.
6, the method for formation buried regions battery lead plate as claimed in claim 1 is characterized in that described cushion layer structure comprises a pad oxide and a pad nitration case.
7, the method for formation buried regions battery lead plate as claimed in claim 6 is characterized in that described cushion layer structure is to carry out with chemical vapour deposition (CVD).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02147303 CN1237600C (en) | 2002-10-17 | 2002-10-17 | Method for forming buried electrode board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02147303 CN1237600C (en) | 2002-10-17 | 2002-10-17 | Method for forming buried electrode board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1490865A CN1490865A (en) | 2004-04-21 |
| CN1237600C true CN1237600C (en) | 2006-01-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02147303 Expired - Lifetime CN1237600C (en) | 2002-10-17 | 2002-10-17 | Method for forming buried electrode board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1237600C (en) |
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2002
- 2002-10-17 CN CN 02147303 patent/CN1237600C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1490865A (en) | 2004-04-21 |
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Granted publication date: 20060118 |