KR0150049B1 - Manufacturing method of charge storage electrode of capacitor - Google Patents

Abstract

The present invention relates to a method for forming a charge storage electrode of a capacitor, by using a wet etching ratio of doped silicon and undoped silicon, and removing the spacer after using the spacer when forming the charge storage electrode contact hole. Disclosed is a method of forming a charge storage electrode of a capacitor in which an uneven structure is formed on an outer sidewall to maximize an effective area of a degradation storage electrode under a limited area.

Description

Method of forming charge storage electrode of capacitor

1A to 1F are cross-sectional views of devices sequentially shown to explain a method of forming a charge storage electrode of a capacitor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: impurity region

3: interlayer insulation film (BPSG) 4: PSG

5A, 5B, 5C: undoped silicon 6A, 6B, 6C: doped silicon

7: nitride film 7A: nitride film spacer

10: charge storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a capacitor, and more particularly, by using a wet etching ratio of doped silicon and undoped silicon, and using a spacer in the charge storage electrode contact hole former to remove the spacers. And it relates to a method of forming a charge storage electrode of a capacitor that is formed in the outer side wall uneven structure to maximize the effective area of the charge storage electrode under a limited area.

Recently, as semiconductor devices have been highly integrated, the area occupied by the charge storage electrodes of the capacitors is reduced, thereby reducing the charge capacity of the capacitors. However, in order to operate the device, a charge capacity of a predetermined capacity or more is required, so that the charge storage electrode structure is three-dimensional in order to maximize the charge capacity of the capacitor under a limited area, thereby maximizing the effective area.

Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode of a capacitor which can be easily performed while maximizing the effective area of the charge storage electrode so as to be suitable for a high integration device.

In the method of forming a charge storage electrode of a capacitor according to the present invention for achieving the above object, a predetermined process is performed to form an interlayer insulating film with BPSG on the silicon substrate on which an impurity region is formed, and to deposit PSG on the interlayer insulating film. And stacking a plurality of layers of undoped silicon and doped silicon in an amorphous state over the entire structure including the PSG, wherein the first undoped, the first dope, the second undoped, the second dope and the third undoped. Depositing silicon in order, etching the undoped and doped silicon until the first undoped silicon is exposed using a charge storage electrode contact mask, and depositing a nitride film over the entire structure; The nitride film is etched to partially remove the nitride film over the first undoped silicon, thereby partially removing the nitride film. And partially depositing a nitride film on the third undoped silicon layer, and sequentially dry etching the exposed first undoped silicon layer, the PSG layer, and the interlayer insulating layer to form a contact hole in contact with the impurity region. Forming a nitride spacer, treating the contact hole with a wet etching solution to selectively etch the PSG from a sidewall of the contact hole to a predetermined depth, and depositing amorphous third doped silicon on the entire structure Burying the contact hole, exposing the upper portion of the nitride spacer by a blanket etching process, removing the nitride spacer, and defining a charge storage electrode by using a charge storage electrode mask. Heat-treated at a temperature of from 670 ° C. for 0.5 to 1.5 hours, and for undoped silicon. It is characterized in that it comprises the step of processing the silicon etching solution having a large etching rate of the silicon to make the inside and outside of the charge storage electrode to the uneven structure.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views of devices sequentially shown to explain a method of forming a charge storage electrode of a capacitor according to the present invention.

As shown in FIG. 1A, a predetermined process is performed to form an interlayer insulating film 3 made of BPSG on the silicon substrate 1 on which the impurity regions 2 are formed. Thin PSG (Phosphosilicate Glass) 4 is deposited on the entire structure including the interlayer insulating film 3.

FIG. 1B shows the first to third undoped silicon 5A, 5B, 5C without impurities doped on the PSG 4 and the first and second doped silicon 6A doped with impurities. , 6B) is a cross-sectional view showing a state of sequentially stacking.

When the undoped and doped silicon (5A, 5B, 5C and 6A, 6B) forming a plurality of layers are deposited, SiH ₄ or Si ₂ H ₆ gas, which is used as a silicon source gas by a low pressure chemical vapor deposition method, is continuously supplied. While intermittently the supply of PH ₃ gas used as the impurity source gas is deposited in the same chamber. At this time, the two layers of the undoped silicon and the undoped silicon are deposited so that the two layers of the undoped silicon have a thicker ratio of 1: 1 to 1: 3.

On the other hand, in the example of the present invention, three and two stacks of undoped silicon and doped silicon, respectively, are not limited to the number of such stacks.

As illustrated in FIG. 1C, the first undoped silicon 5A is exposed by etching from the third undoped silicon 5C to the first doped silicon 6A using the charge storage electrode contact mask. After the nitride film 7 is deposited by a chemical vapor deposition method using plasma, the first undoped silicon 5A is derived by etching the nitride film 7 by a predetermined thickness.

At this time, the deposition process of the nitride film 7 is performed at 550 ° C. or less so that the undoped and doped silicon 5A, 5B, 5C, 6A, and 6B deposited in an amorphous state do not become phase transition to polycrystalline silicon. When the nitride film 7 is etched to the time point at which the first undoped silicon 5A is exposed due to poor step coverage of the nitride film, the nitride film 7 is partially disposed on the third undoped silicon 5C. It will remain in thickness.

As shown in FIG. 1D, the first undoped silicon 5A PSG 4 and the BPSG exposed by the dry etching process using the nitride film 7 remaining on the third undoped silicon 5C as an etch barrier layer. The interlayer insulating film 3 is etched sequentially to form contact holes in communication with the impurity regions 2 (source / drain regions) of the silicon substrate 1. Thereafter, the PSG 4 is partially etched by treating the contact hole with a wet etching solution having a very high etch rate of the PSG relative to the BPSG. An amorphous third doped silicon 6C is formed on the entire structure including the contact hole.

While sequentially etching the interlayer insulating film 3 made of the first undoped silicon 5A, the PSG 4 and the BPSG, the nitride film 7 remaining on the third undoped silicon 5C is naturally removed and the silicon ( Nitride film spacers 7A are formed on the sidewalls of 6A, 5B, 6B, and 5C. In order to selectively etch the PSG (4) inside the charge storage electrode contact hole to form a groove under the first undoped silicon (5A) BOE solution in the ratio NH ₄ F: HF = 50: 1 compared to BPSG Relatively etch PSG. The etched portion of the PSG 4 is filled by the third doped silicon 6C deposited in a subsequent process.

As shown in FIG. 1E, a third etching silicon (6C) is formed by a blanket etching process using a chlorine-based etching gas having a lower etching rate than that of the doping silicon. By etching, the upper portion of the nitride film spacer 7A is exposed. After the nitride film spacer 7A is removed, the charge storage electrode is defined by using the charge storage electrode mask.

When the nitride film spacer 7A is removed, the nitride film is first removed by an oxide dry etching method to selectively remove the surrounding silicon, and then treated with a phosphoric acid solution.

FIG. 1f illustrates that a wafer having such a structure is heat-treated in a nitrogen atmosphere at a temperature of 630 to 670 ° C. for 0.5 to 1.5 hours, and then treated in a silicon etching solution to thereby have a convex and convexity on sidewalls inside and outside the charge storage electrode 10. It is sectional drawing which shows the state which formed ().

During the heat treatment process, the undoped silicon (5A, 5B, 5C) is phase-transformed from amorphous to polycrystalline silicon to reduce the etch rate in the silicon etching solution, while the doped silicon (6A, 6B, 6C) is impurity activated to phase change. It compensates for the decrease in the etch rate of silicon due to the high wet etching rate similar to that of amorphous silicon doped with impurities. In addition, the oxides formed on top of the doped silicon 6A, 6B, and 6C among the surface oxides grown on the silicon surface during heat treatment are higher than the etching rate of the oxides formed on the top of the undoped silicon 5A, 5B, and 5C. Therefore, the etching of the doped silicon (6A, 6B, 6C) in the silicon etching solution in the ratio of HNO ₃ : CH ₃ COOH: HF: DI = 30: 3: 0.5: 15.5 was performed. ), The inner and outer sidewalls of the charge storage electrode 10 are concave-convex structure.

As described above, according to the present invention, the effective surface area of the charge storage electrode can be maximized under a limited area, thereby increasing the charge capacity of the capacitor.

Claims (4)

Performing a predetermined process to form an interlayer insulating film with BPSG on the silicon substrate on which the impurity region is formed, depositing PSG on the interlayer insulating film, and undoped silicon and doped silicon on the entire structure including the PSG. Stacking in a multi-layer amorphous state, and depositing in the order of first undoped, first dope, second undoped, second dope and third undoped silicon, and using the charge storage electrode contact mask. Etching the undoped and doped silicon until the undoped silicon is exposed, depositing a nitride film over the entire structure, and etching the nitride film to partially remove the nitride film on the first undoped silicon. Exposing a portion of the first undoped silicon and leaving a portion of the nitride film over the third undoped silicon; Sequentially dry-etching the exposed first undoped silicon, PSG and the interlayer insulating film to form a contact hole in contact with the impurity region, thereby forming a nitride film spacer, and treating the contact hole with a wet etching solution. Causing the PSG to pre-etch the PSG from a sidewall of the contact hole to a predetermined depth; depositing the amorphous third doped silicon on the entire structure to fill the contact hole, and then forming an upper portion of the nitride layer spacer by a blanket etching process. After exposing, removing the nitride film spacer, defining the charge storage electrode by using the charge storage electrode mask, and heat-treated for 0.5 to 1.5 hours at a temperature of 630 to 670 ℃ with a nitrogen atmosphere, to the undoped silicon Inside and outside of the charge storage electrode by treating the silicon etching solution having a large etching rate of the doped silicon Forming a charge storage electrode of the capacitor, it characterized in that comprising the step of a concavo-convex structure to be. The method of claim 1, wherein the wet etching solution treating the contact hole is a BOE solution of NH ₄ F: HF = 50: 1 having a large PSG etch rate with respect to BPSG. The method of claim 1, wherein the blanket etching process of the third doped silicon uses a chlorine dry etching gas. The method of claim 1, wherein the silicon etching solution is HNO ₃ : CH ₃ COOH: HF: DI = 30: 3: 0.5: A method for forming a charge storage electrode of a capacitor, characterized in that the ratio of 15.5.