CN1530915A

CN1530915A - Data driving device

Info

Publication number: CN1530915A
Application number: CNA031205291A
Authority: CN
Inventors: 薛玮杰
Original assignee: Toppoly Optoelectronics Corp
Current assignee: TPO Displays Corp
Priority date: 2003-03-13
Filing date: 2003-03-13
Publication date: 2004-09-22
Anticipated expiration: 2023-03-13
Also published as: CN1317688C

Abstract

A data driving apparatus for an active organic light emitting diode display (AMOLED) includes a plurality of converters for converting digital voltage signals into analog current signals to drive pixels on a panel to emit light. The converter comprises a plurality of current mirror devices, two control signals are used for controlling the generation of the mirror current, and the error of the transistor shape ratio in manufacturing can not cause the distortion of the mirror current.

Description

Data driven unit

Technical field

The present invention is a kind of data driven unit (datadriver) that is used for the active organic LED display, and is in order to convert a digital voltage signal to an analog current signal, luminous with each pixel in the driving display.

Technical background

Active organic LED display (AMOLED) can utilize an analog current value to come each pixel in the driving display luminous at present.Yet, but be a digital voltage value in order to control the luminous control signal of each pixel, therefore, AMOLED just needs a data drive unit, or is called source electrode driving device (source driver), converts its digital voltage signal to analog current signal.

Fig. 1 is a known data driven unit 1.As shown in the figure, this device 1 comprises one first shift register (shift register), 101, one data register (data register), 103, one voltage latch unit (voltage latch), 105, one converter (converter) 107, an electric current latch unit (currentlatch) 109, a current source (current source) 111 and 1 second shift register 113.Wherein, converter 107 receives from voltage latch unit 105, and in order to drive the luminous digital voltage signal 110 of pixel, the reference current levels that is provided according to current source 111 converts its digital voltage signal 110 to analog current signal 112 simultaneously.Second shift register 113 is used for the switch of each unit (cell) in the Control current latch unit 109, to deposit the analog current signal 112 from converter 107.After suitable a period of time, start (enable) signal 108 starting current latch units 109, all analog current signals 114 export each pixel simultaneously to, to finish the operation that shows a picture.

The structure of converter 107 is essentially a current mirror (current mirror) structure.Fig. 2 is a kind of of known current-mirror structure, as shown in Figure 2, and reference current I _sCurrent source 111 from Fig. 1.Via transistor MP1, reference current I _sMirror image produces I _P1, I _P2, I _P3Deng.Wherein, image current I _P1, I _P2, I _P3Deng value can be with the shape of MP1 and MP2, MP3, MP4 etc. than (aspect ratio) and different.Because image current I _P1, I _P2, I _P3Deng the shape of value and MP2, MP3, MP4 etc. more relevant than, critical voltage (Vth) and mobility (mobility), if the shape of MP2, MP3, MP4 etc. than, critical voltage and mobility when making and theoretical value produce some error, will cause image current I _P1, I _P2, I _P3Deng value and theoretical value discrepancy is arranged, though that its error amount is unlikely to is too big, the acceptable analog current signal scope of each pixel is very narrow in the AMOLED.Therefore, even image current I _P1, I _P2, I _P3Deng error amount very little, also might make the analog current signal generation error that is produced, and this error is enough to make actual value and theoretical value to drop on different gray areas, and then causes some pixels to produce different brightness, cause distortion.

Summary of the invention

The present invention discloses a kind of data driven unit that is used for the active organic LED display, and is in order to convert a digital voltage signal to an analog current signal, luminous with each pixel in the driving display.

This data driven unit comprises one first shift register, a data register, a voltage latch unit, one second shift register and N converter.First shift register is exported first control signal of a N position, and data register is enabled the unit in the data register successively according to this first control signal, stores the digital voltage signal of N M position respectively.Data register just is sent to the voltage latch unit with these signals in the lump after receiving and storing all digital voltage signals that finish.The voltage latch unit responds a switching signal after receiving all digital voltage signals, this N digital voltage signal is sent to N converter respectively.Second shift register then is used to provide second control signal of one (M+1) position, digital voltage signal is converted to the process of analog current signal in order to N converter of control.

Converter in the data driven unit of the present invention is a kind ofly to convert digital voltage the element of analog current to, and it comprises M unit, and each unit is a current mirror arrangement.This current mirror arrangement has two control signals, and in order to starting or to forbid (disable) transistor wherein, and control produces the time of image current.This current mirror arrangement can be improved the shortcoming of known current mirror arrangement, and image current can not changed along with transistorized shape ratio difference.

Description of drawings

Fig. 1 is the synoptic diagram of well known data drive unit;

Fig. 2 is the circuit diagram of known current mirror arrangement;

Fig. 3 is the synoptic diagram of data driven unit of the present invention;

Fig. 4 is the synoptic diagram of converter of the present invention;

Fig. 5 is the circuit diagram of current mirror arrangement of the present invention.

The element shown symbol description

1 well known data drive unit

2 data driven units of the present invention

Unit 3

101 first shift registers

103 data registers, 105 voltage latch units

107 converters, 108 enabling signals

109 electric current latch units, 110 digital voltage signals

111 current sources, 112 analog current signals

113 second shift registers

114 analog current signals, 201 first shift registers

202 data shift signals, 203 data registers

204 first control signals, 205 voltage latch units

206 digital voltage signals, 207 second shift registers

A 208 digital voltage signal 209N converter

210 switching signals, 211 current-source arrangements

212 digital voltage signals, 214 signals

216 second control signals, 218 analog current signals

301 first devices, 303 second devices

Embodiment

As shown in Figure 3, data driven unit 2 disclosed in this invention comprises one first shift register 201, a data register 203, a voltage latch unit 205, one second shift register 207 and N converter 209.Wherein, first shift register 201 is accepted a data shift signal (data shiftsignal) 202, exports first control signal 204 of a N position.This first control signal 204 inputs to data register 203, is used for enabling successively the unit in the data register 203, with the digital voltage signal 206 of storing N M position respectively.This digital voltage signal 206 is to convert analog current signal 218 to, and (data line) is sent to each pixel via data line, makes its luminous control signal.Data register 203 just is sent to voltage latch unit 205 with these signals in the lump after receiving and storing all digital voltage signals 206 that finish.Voltage latch unit 205 is after finishing these digital voltage signals 208 of reception, and in the specific time, switching signal 210 can be enabled voltage latch unit 205, makes this N digital voltage signal 208 be sent to N converter 209 respectively.Second shift register, 207 responses, one signal 214 provides one (M+1) second control signal 216 of position, digital voltage signal 212 is converted to the process of analog current signal 218 in order to N converter 209 of control.Converter 209 is the conversion equipment that a digital voltage revolving die is intended electric current, has the function of electric current latch unit 109 among Fig. 1 simultaneously, can wait all digital voltage signals 212 all to change into analog current signal 218 after, export each pixel more in the lump to.

For explanation one embodiment of the invention, suppose that each digital voltage signal 206 is six signals.As shown in Figure 4, each converter 209 need comprise six first devices and six second devices for the input of six of cooperations.The first six position SW in each the first device response, second control signal 216 ₀-SW ₅One of them, in order to produce six first image currents (first mirrored current) I _M0-I _M5, be sent to each second device.Last SW in each the second device response, second control signal 216 ₆, and according to the first image current I from the first device input _M0-I _M5, convert a digital voltage signal 212 to an analog current signal 218.

With the unit 3 among Fig. 4 is example, and first device is receiving second position SW of second control signal 216 ₁After, the reference current I that will be provided by current-source arrangement 211 _Ref1Convert the first image current I to _M1Second device is at last SW that receives second control signal 216 ₆After, second position D of cooperation digital voltage signal 206 ₁Value, with the first image current I _M1Convert the second image current I to ₁₁

Among this embodiment, current-source arrangement 211 need have six outputs at least, in order to six kinds of different reference current I to be provided _Ref0-I _Ref5, allow first device produce six first image current I _M0-I _M5These six reference current I _Ref0-I _Ref5Value can be respectively increase progressively with the multiplying power of twice successively, if I _Ref0=2 μ A, then I _Ref1=4 μ A, I _Ref2=8 μ A, I _Ref3=16 μ A, I _Ref4=32 μ A, I _Ref5=64 μ A.Suppose that a certain digital voltage signal 206 is (D ₅D ₄D ₃D ₂D ₁D ₀)=(101001), the corresponding analog current signal I that then comes out by 209 conversions of the converter among Fig. 4 _TOTAL=I _M0+ I _M3+ I _M5=I _Ref0+ I _Ref3+ I _Ref5=82 μ A.

The circuit diagram of unit 3 as shown in Figure 5 among Fig. 4.Converter 209 can provide a high level voltage source VDD and a low level voltage source VSS by outside or inside.First device 301 comprises a first transistor M1, a transistor seconds M2, one the 3rd transistor M3 and one first capacitor C 1.The first transistor M1 and transistor seconds M2 are the TFT of n passage, and the 3rd transistor M3 then is the TFT of p passage.Three transistor M1, M2, M3 all have one source pole (source), a drain electrode (drain) and a grid (gate), but because the source electrode of TFT there is no different with drain electrode, for avoiding misleading, in this instructions source electrode and drain electrode are loosely referred to as first utmost point and second utmost point, first capacitor C 1 comprises one first end 1st and one second end 2nd.Its connected mode is: the grid G of the first transistor M1 is in order to import second position SW in second control signal 216 ₁, second utmost point 2nd of the first transistor M1 is connected to 211 second output terminal I of current-source arrangement _Ref1First utmost point 1st of the first transistor M1 is connected to first utmost point 1st of transistor seconds M2 and second utmost point 2nd of the 3rd transistor M3, the grid G of transistor seconds M2 is connected to the grid G of the first transistor M1, second utmost point 2nd of transistor seconds M2 is connected to the second end 2nd of the grid G and first capacitor C 1 of the 3rd transistor M3, and the first end 1st of first capacitor C 1 is connected to first utmost point 1st and the high level voltage source VDD of the 3rd transistor M3.

Second device 303 comprises one the 4th transistor M4, one the 5th transistor M5, one the 6th transistor M6, one the 7th transistor M7 and one second capacitor C 2.The 4th transistor M4 to the seven transistor M7 are all the TFT of n passage, and also have one first utmost point 1st, one second utmost point 2nd and a grid G, and second capacitor C 2 comprises one first end 1st and one second end 2nd.Its mode of connection is: the grid G of the 4th transistor M4 is in order to import last SW in second control signal 216 ₆Second utmost point 2nd of the 4th transistor M4 is connected to second utmost point 2nd of the 3rd transistor M3 of first device 301, first utmost point 1st of the 4th transistor M4 is connected to first utmost point 1st of the 5th transistor M5 and second utmost point 2nd of the 6th transistor M6, the grid G of the 5th transistor M5 is connected to the grid G of the 4th transistor M4, second utmost point 2nd of the 5th transistor M5 is connected to the second end 2nd of the grid G and second capacitor C 2 of the 6th transistor M6, the first end 1st of second capacitor C 2 is connected to first utmost point 1st and the low level voltage source VSS of the 6th transistor M6, first utmost point 1st of the 7th transistor M7 is connected to second utmost point 2nd of the 6th transistor M6, and the grid G of the 7th transistor M7 is in order to import second D1 of one six bit digital voltage signal 212.

Second position SW in second control signal 216 ₁In order to start or to forbid the first transistor M1 and transistor seconds M2.Second position SW in second control signal 216 ₁During for high level, the first transistor M1 and transistor seconds M2 are activated, second reference current I of current-source arrangement 211 _Ref1Via the first transistor M1 and the 3rd transistor M3, to 1 charging of first capacitor C.So, reference current I _Ref1Just convert corresponding first store voltages in first capacitor C 1.After 1 charging of first capacitor C finishes, second position SW in second control signal 216 ₁Change low level into, forbidding the first transistor M1 and transistor seconds M2, and first voltage pinned in first capacitor C 1.

Last SW in second control signal 216 ₆In order to start or to forbid the 4th transistor M4 and the 5th transistor M5.Last SW in second control signal 216 ₆During for high-voltage level, the 4th transistor M4 and the 5th transistor M5 are activated, and first voltage that be stored in first capacitor C 1 this moment converts corresponding second store voltages in second capacitor C 2 via the 4th transistor M4 and the 6th transistor M6.After 2 chargings of second capacitor C finish, last SW in second control signal 216 ₆Change low level into, forbidding the 4th transistor M4 and the 5th transistor M5, and second voltage pinned in second capacitor C 2.If input is second D of the digital voltage signal 212 of a converter 209 so far ₁Be high-voltage level, second voltage can convert the second image current I of flow through the 6th transistor M6 and the 7th transistor M7 to ₁₁When field-effect transistor worked in the saturation region, the pass of the voltage difference of its electric current and lock source electrode was

i_{D} = \frac{1}{2} μ C_{OX} \frac{W}{L} {(v_{GS} - V_{t})}^{2}

According to this relational expression, (be SW when first capacitor C 1 is in charged state ₁Be high-voltage level) time, no matter than W/L, critical voltage and mobility why the shape of the 3rd transistor M3 all can store a corresponding V _GSIn first capacitor C 1.Work as SW ₆When being in high-voltage level, it is stored in the V of first capacitor C 1 _GSConvert the first image current I to via the 3rd transistor M3 _M1To 2 chargings of second capacitor C, because this V _GSStill the 3rd transistor M3 is setovered, so the first image current I _M1Can be equal to reference current I _Ref1In like manner, the second image current I ₁₁Can be equal to the first image current I _M1, promptly be equal to reference current I _Ref1

Therefore, the unit 3 of Fig. 5 is a current mirror arrangement, SW ₁In this current mirror arrangement, can be considered one first control signal, in order to starting or to forbid the first transistor M1 and transistor seconds M2, and control reference current I _Ref1Convert first store voltages in first capacitor C 1.SW ₆In this current mirror arrangement, can be considered one second control signal, in order to starting or to forbid the 4th transistor M4 and the 5th transistor M5, and control first voltage transitions and become corresponding second store voltages in second capacitor C 2, and the second image current I ₁₁It then is the image current that is produced according to second voltage.This structure can be improved the shortcoming of known current mirror arrangement among Fig. 2, make image current not can along with transistorized shape than the difference of W/L, critical voltage and mobility and change.

The structure of other unit and principle of operation are all identical with unit 3 among Fig. 4.As shown in Figure 4, second utmost point 2nd of the 7th transistor M7 in all second devices 30 3 all is connected to node n1.Therefore, the flow through electric current summation I of this node n1 _TOTALBe an analog current signal 218, luminous in order to a pixel that drives among the AMOLED.Converter 209 total N of the present invention are individual, and are luminous in order to N the pixel that drives simultaneously on the AMOLED panel.

From the above, after the luminous digital voltage control signal of pixel on the control AMOLED inputs to data driven unit disclosed in this invention, be convertible into the analog current signal of direct driven for emitting lights diode.Simultaneously, because of transistorized shape than W/L, critical voltage and mobility some error can take place during fabrication, therefore converter disclosed in this invention can be avoided and the coarse analog current signal that produces is undistorted with the brightness of guaranteeing light emitting diode.

Claims

1. A data driving device for an active organic light emitting diode display (AMOLED), comprising:

A first shift register, used to provide an N-bit first control signal;

A data register, in response to the first control signal, stores N digital voltage signals of M bits respectively;

A voltage latch, used to receive the N digital voltage signals, and transmit the N digital voltage signals in response to a start signal;

a second shift register for providing a second control signal of M+1 bits; and

N converters, each converter contains:

M first devices, for generating M first mirror currents in response to one of the first M bits in the second control signal; and

M second devices, in response to the last bit of the second control signal, convert one of the N digital voltage signals into an analog current signal according to the M first mirror currents.

2. The data driving device as claimed in claim 1, wherein the switching signal enables the voltage latch after the voltage latch finishes receiving all the N digital voltage signals from the data register, so that the N digital voltage signals are sent to the N converters.

3. The data driving device as claimed in claim 1, wherein the data driving device further comprises a current source device having at least M output terminals for providing M different reference current values for the first A device generates the M first mirror currents.

4. The data driving device as claimed in claim 3, wherein the converter further comprises a high-level voltage source and a low-level voltage source, and the first device comprises:

A first transistor, including a first pole, a second pole and a gate;

A second transistor, including a first pole, a second pole and a gate;

A third transistor including a first pole, a second pole and a gate; and

A first capacitor, including a first terminal and a second terminal;

Wherein, the gate of the first transistor is used to input one of the first M bits of the second control signal, the second pole of the first transistor is connected to one of the plurality of output terminals, and the first The first pole of a transistor is connected to the first pole of the second transistor and the second pole of the third transistor, the gate of the second transistor is connected to the gate of the first transistor, the first The second pole of the second transistor is connected to the gate of the third transistor and the second terminal of the first capacitor, and the first terminal of the first capacitor is connected to the first pole of the third transistor and the second terminal of the first capacitor. High level voltage source.

5. The data drive device as claimed in claim 4, wherein the second device comprises:

A fourth transistor, including a first pole, a second pole and a gate;

A fifth transistor, including a first pole, a second pole and a gate;

A sixth transistor, including a first pole, a second pole and a gate;

A seventh transistor including a first pole, a second pole and a gate; and

A second capacitor, including a first terminal and a second terminal;

Wherein, the gate of the fourth transistor is used to input the last bit of the second control signal, the second pole of the fourth transistor is connected to the second pole of the third transistor, and the second pole of the fourth transistor is connected to the second pole of the third transistor. The first pole is connected to the first pole of the fifth transistor and the second pole of the sixth transistor, the gate of the fifth transistor is connected to the gate of the fourth transistor, and the gate of the fifth transistor is connected to the gate of the fifth transistor. The second pole is connected to the gate of the sixth transistor and the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to the first pole of the sixth transistor and the low level A voltage source, the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and the gate of the seventh transistor is used to input one of the M-bit digital voltage signals.

6. The data driving device as claimed in claim 5, wherein the second poles of the seventh transistors in the M second devices are all connected to a node, and the sum of the currents flowing through the node is the analog current signal .

7. A digital voltage-to-analog current converter, responsive to a first control signal and a second control signal, for converting an M-bit digital voltage signal into an analog current signal, comprising:

M first devices, for generating M first mirror currents in response to the first control signal; and

M second devices, in response to the second control signal, convert the digital voltage signal into the analog current signal according to the M first mirror currents.

8. The digital voltage to analog current converter as claimed in claim 7, wherein the digital voltage to analog current converter further comprises:

A current source device having at least M output terminals for providing M different reference current values for the first device to generate the M first mirror currents;

a high level voltage source; and

a low level voltage source.

9. The digital voltage to analog current converter as claimed in claim 8, wherein the first means comprises:

A first transistor including a source, a drain and a gate;

a second transistor including a source, a drain and a gate;

a third transistor comprising a source, a drain and a gate; and

A first capacitor, including a first terminal and a second terminal;

Wherein, the gate of the first transistor is used to input the first control signal, the drain of the first transistor is connected to one of the plurality of output terminals, and the source of the first transistor is connected to the first The source of the second transistor and the drain of the third transistor, the gate of the second transistor is connected to the gate of the first transistor, the drain of the second transistor is connected to the third transistor The gate and the second terminal of the first capacitor, the first terminal of the first capacitor are connected to the source of the third transistor and the high-level voltage source.

10. The digital voltage to analog current converter as claimed in claim 9, wherein the second means comprises:

a fourth transistor including a source, a drain and a gate;

A fifth transistor including a source, a drain and a gate;

A sixth transistor including a source, a drain and a gate;

a seventh transistor comprising a source, a drain and a gate; and

A second capacitor, including a first terminal and a second terminal;

Wherein, the gate of the fourth transistor is used to input the second control signal, the drain of the fourth transistor is connected to the drain of the third transistor, and the source of the fourth transistor is connected to the first The source of the fifth transistor and the drain of the sixth transistor, the gate of the fifth transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor is connected to the sixth transistor The gate and the second terminal of the second capacitor, the first terminal of the second capacitor is connected to the source of the sixth transistor and the low level voltage source, the source of the seventh transistor is connected to To the drain of the sixth transistor, the gate of the seventh transistor is used to input one of the M-bit digital voltage signals.

11. The digital voltage to analog current converter as claimed in claim 10, wherein the drains of the seventh transistors in the M second devices are all connected to a node, and the sum of the currents flowing through the node is the Analog current signal.

12. A current mirror device comprising:

a current source device;

a high-level voltage source;

a low-level voltage source;

a first control signal;

a second control signal;

A first transistor including a source, a drain and a gate;

a second transistor including a source, a drain and a gate;

a third transistor including a source, a drain and a gate;

a fourth transistor including a source, a drain and a gate;

A fifth transistor including a source, a drain and a gate;

A sixth transistor including a source, a drain and a gate;

a first capacitor, including a first terminal and a second terminal; and

A second capacitor, including a first terminal and a second terminal;

Wherein, the gate of the first transistor is used to input the first control signal, the drain of the first transistor is connected to the current source device, the source of the first transistor is connected to the second transistor source and the drain of the third transistor, the gate of the second transistor is connected to the gate of the first transistor, the drain of the second transistor is connected to the gate of the third transistor and The second terminal of the first capacitor, the first terminal of the first capacitor is connected to the source of the third transistor and the high-level voltage source, and the gate of the fourth transistor is used to input the first Two control signals, the drain of the fourth transistor is connected to the drain of the third transistor, the source of the fourth transistor is connected to the source of the fifth transistor and the drain of the sixth transistor , the gate of the fifth transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor is connected to the gate of the sixth transistor and the second terminal of the second capacitor, the The first terminal of the second capacitor is connected to the source of the sixth transistor and the low-level voltage source, and a current value flowing through the sixth transistor is substantially the same as that of the current source device.

13. The current mirror device as claimed in claim 12, wherein the first control signal is used to enable or disable the first transistor and the second transistor, when the first transistor and the second transistor are enabled, the current The source device is converted into a corresponding first voltage through the third transistor and stored in the first capacitor.

14. The current mirror device as claimed in claim 13, wherein the second control signal is used to enable or disable the fourth transistor and the fifth transistor, when the fourth transistor and the fifth transistor are enabled, the first A voltage is converted into a corresponding second voltage through the sixth transistor and stored in the second capacitor

15. The current mirror device of claim 14, wherein the second voltage is converted into the current flowing through the sixth transistor when the fourth transistor and the fifth transistor are disabled.