CN1530915A - Data driver - Google Patents
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- CN1530915A CN1530915A CNA031205291A CN03120529A CN1530915A CN 1530915 A CN1530915 A CN 1530915A CN A031205291 A CNA031205291 A CN A031205291A CN 03120529 A CN03120529 A CN 03120529A CN 1530915 A CN1530915 A CN 1530915A
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Abstract
A data driving device used for an active organic LED diplay comprises a plurality of converters for converting a digital voltage signal into an analog current signal to drive the pixels on panel to emit light. The converter comprises a plurality of current mirror devices to control producing mirror-image current, and the error of shape ratio of transistors resulting from manufacturing will not result in the distortion of the mirror-image current.
Description
Technical field
The present invention is a kind of data driven unit (datadriver) that is used for the active organic LED display, and is in order to convert a digital voltage signal to an analog current signal, luminous with each pixel in the driving display.
Technical background
Active organic LED display (AMOLED) can utilize an analog current value to come each pixel in the driving display luminous at present.Yet, but be a digital voltage value in order to control the luminous control signal of each pixel, therefore, AMOLED just needs a data drive unit, or is called source electrode driving device (source driver), converts its digital voltage signal to analog current signal.
Fig. 1 is a known data driven unit 1.As shown in the figure, this device 1 comprises one first shift register (shift register), 101, one data register (data register), 103, one voltage latch unit (voltage latch), 105, one converter (converter) 107, an electric current latch unit (currentlatch) 109, a current source (current source) 111 and 1 second shift register 113.Wherein, converter 107 receives from voltage latch unit 105, and in order to drive the luminous digital voltage signal 110 of pixel, the reference current levels that is provided according to current source 111 converts its digital voltage signal 110 to analog current signal 112 simultaneously.Second shift register 113 is used for the switch of each unit (cell) in the Control current latch unit 109, to deposit the analog current signal 112 from converter 107.After suitable a period of time, start (enable) signal 108 starting current latch units 109, all analog current signals 114 export each pixel simultaneously to, to finish the operation that shows a picture.
The structure of converter 107 is essentially a current mirror (current mirror) structure.Fig. 2 is a kind of of known current-mirror structure, as shown in Figure 2, and reference current I
sCurrent source 111 from Fig. 1.Via transistor MP1, reference current I
sMirror image produces I
P1, I
P2, I
P3Deng.Wherein, image current I
P1, I
P2, I
P3Deng value can be with the shape of MP1 and MP2, MP3, MP4 etc. than (aspect ratio) and different.Because image current I
P1, I
P2, I
P3Deng the shape of value and MP2, MP3, MP4 etc. more relevant than, critical voltage (Vth) and mobility (mobility), if the shape of MP2, MP3, MP4 etc. than, critical voltage and mobility when making and theoretical value produce some error, will cause image current I
P1, I
P2, I
P3Deng value and theoretical value discrepancy is arranged, though that its error amount is unlikely to is too big, the acceptable analog current signal scope of each pixel is very narrow in the AMOLED.Therefore, even image current I
P1, I
P2, I
P3Deng error amount very little, also might make the analog current signal generation error that is produced, and this error is enough to make actual value and theoretical value to drop on different gray areas, and then causes some pixels to produce different brightness, cause distortion.
Summary of the invention
The present invention discloses a kind of data driven unit that is used for the active organic LED display, and is in order to convert a digital voltage signal to an analog current signal, luminous with each pixel in the driving display.
This data driven unit comprises one first shift register, a data register, a voltage latch unit, one second shift register and N converter.First shift register is exported first control signal of a N position, and data register is enabled the unit in the data register successively according to this first control signal, stores the digital voltage signal of N M position respectively.Data register just is sent to the voltage latch unit with these signals in the lump after receiving and storing all digital voltage signals that finish.The voltage latch unit responds a switching signal after receiving all digital voltage signals, this N digital voltage signal is sent to N converter respectively.Second shift register then is used to provide second control signal of one (M+1) position, digital voltage signal is converted to the process of analog current signal in order to N converter of control.
Converter in the data driven unit of the present invention is a kind ofly to convert digital voltage the element of analog current to, and it comprises M unit, and each unit is a current mirror arrangement.This current mirror arrangement has two control signals, and in order to starting or to forbid (disable) transistor wherein, and control produces the time of image current.This current mirror arrangement can be improved the shortcoming of known current mirror arrangement, and image current can not changed along with transistorized shape ratio difference.
Description of drawings
Fig. 1 is the synoptic diagram of well known data drive unit;
Fig. 2 is the circuit diagram of known current mirror arrangement;
Fig. 3 is the synoptic diagram of data driven unit of the present invention;
Fig. 4 is the synoptic diagram of converter of the present invention;
Fig. 5 is the circuit diagram of current mirror arrangement of the present invention.
The element shown symbol description
1 well known data drive unit
2 data driven units of the present invention
Unit 3
101 first shift registers
103 data registers, 105 voltage latch units
107 converters, 108 enabling signals
109 electric current latch units, 110 digital voltage signals
111 current sources, 112 analog current signals
113 second shift registers
114 analog current signals, 201 first shift registers
202 data shift signals, 203 data registers
204 first control signals, 205 voltage latch units
206 digital voltage signals, 207 second shift registers
A 208 digital voltage signal 209N converter
210 switching signals, 211 current-source arrangements
212 digital voltage signals, 214 signals
216 second control signals, 218 analog current signals
301 first devices, 303 second devices
Embodiment
As shown in Figure 3, data driven unit 2 disclosed in this invention comprises one first shift register 201, a data register 203, a voltage latch unit 205, one second shift register 207 and N converter 209.Wherein, first shift register 201 is accepted a data shift signal (data shiftsignal) 202, exports first control signal 204 of a N position.This first control signal 204 inputs to data register 203, is used for enabling successively the unit in the data register 203, with the digital voltage signal 206 of storing N M position respectively.This digital voltage signal 206 is to convert analog current signal 218 to, and (data line) is sent to each pixel via data line, makes its luminous control signal.Data register 203 just is sent to voltage latch unit 205 with these signals in the lump after receiving and storing all digital voltage signals 206 that finish.Voltage latch unit 205 is after finishing these digital voltage signals 208 of reception, and in the specific time, switching signal 210 can be enabled voltage latch unit 205, makes this N digital voltage signal 208 be sent to N converter 209 respectively.Second shift register, 207 responses, one signal 214 provides one (M+1) second control signal 216 of position, digital voltage signal 212 is converted to the process of analog current signal 218 in order to N converter 209 of control.Converter 209 is the conversion equipment that a digital voltage revolving die is intended electric current, has the function of electric current latch unit 109 among Fig. 1 simultaneously, can wait all digital voltage signals 212 all to change into analog current signal 218 after, export each pixel more in the lump to.
For explanation one embodiment of the invention, suppose that each digital voltage signal 206 is six signals.As shown in Figure 4, each converter 209 need comprise six first devices and six second devices for the input of six of cooperations.The first six position SW in each the first device response, second control signal 216
0-SW
5One of them, in order to produce six first image currents (first mirrored current) I
M0-I
M5, be sent to each second device.Last SW in each the second device response, second control signal 216
6, and according to the first image current I from the first device input
M0-I
M5, convert a digital voltage signal 212 to an analog current signal 218.
With the unit 3 among Fig. 4 is example, and first device is receiving second position SW of second control signal 216
1After, the reference current I that will be provided by current-source arrangement 211
Ref1Convert the first image current I to
M1Second device is at last SW that receives second control signal 216
6After, second position D of cooperation digital voltage signal 206
1Value, with the first image current I
M1Convert the second image current I to
11
Among this embodiment, current-source arrangement 211 need have six outputs at least, in order to six kinds of different reference current I to be provided
Ref0-I
Ref5, allow first device produce six first image current I
M0-I
M5These six reference current I
Ref0-I
Ref5Value can be respectively increase progressively with the multiplying power of twice successively, if I
Ref0=2 μ A, then I
Ref1=4 μ A, I
Ref2=8 μ A, I
Ref3=16 μ A, I
Ref4=32 μ A, I
Ref5=64 μ A.Suppose that a certain digital voltage signal 206 is (D
5D
4D
3D
2D
1D
0)=(101001), the corresponding analog current signal I that then comes out by 209 conversions of the converter among Fig. 4
TOTAL=I
M0+ I
M3+ I
M5=I
Ref0+ I
Ref3+ I
Ref5=82 μ A.
The circuit diagram of unit 3 as shown in Figure 5 among Fig. 4.Converter 209 can provide a high level voltage source VDD and a low level voltage source VSS by outside or inside.First device 301 comprises a first transistor M1, a transistor seconds M2, one the 3rd transistor M3 and one first capacitor C 1.The first transistor M1 and transistor seconds M2 are the TFT of n passage, and the 3rd transistor M3 then is the TFT of p passage.Three transistor M1, M2, M3 all have one source pole (source), a drain electrode (drain) and a grid (gate), but because the source electrode of TFT there is no different with drain electrode, for avoiding misleading, in this instructions source electrode and drain electrode are loosely referred to as first utmost point and second utmost point, first capacitor C 1 comprises one first end 1st and one second end 2nd.Its connected mode is: the grid G of the first transistor M1 is in order to import second position SW in second control signal 216
1, second utmost point 2nd of the first transistor M1 is connected to 211 second output terminal I of current-source arrangement
Ref1First utmost point 1st of the first transistor M1 is connected to first utmost point 1st of transistor seconds M2 and second utmost point 2nd of the 3rd transistor M3, the grid G of transistor seconds M2 is connected to the grid G of the first transistor M1, second utmost point 2nd of transistor seconds M2 is connected to the second end 2nd of the grid G and first capacitor C 1 of the 3rd transistor M3, and the first end 1st of first capacitor C 1 is connected to first utmost point 1st and the high level voltage source VDD of the 3rd transistor M3.
Second device 303 comprises one the 4th transistor M4, one the 5th transistor M5, one the 6th transistor M6, one the 7th transistor M7 and one second capacitor C 2.The 4th transistor M4 to the seven transistor M7 are all the TFT of n passage, and also have one first utmost point 1st, one second utmost point 2nd and a grid G, and second capacitor C 2 comprises one first end 1st and one second end 2nd.Its mode of connection is: the grid G of the 4th transistor M4 is in order to import last SW in second control signal 216
6Second utmost point 2nd of the 4th transistor M4 is connected to second utmost point 2nd of the 3rd transistor M3 of first device 301, first utmost point 1st of the 4th transistor M4 is connected to first utmost point 1st of the 5th transistor M5 and second utmost point 2nd of the 6th transistor M6, the grid G of the 5th transistor M5 is connected to the grid G of the 4th transistor M4, second utmost point 2nd of the 5th transistor M5 is connected to the second end 2nd of the grid G and second capacitor C 2 of the 6th transistor M6, the first end 1st of second capacitor C 2 is connected to first utmost point 1st and the low level voltage source VSS of the 6th transistor M6, first utmost point 1st of the 7th transistor M7 is connected to second utmost point 2nd of the 6th transistor M6, and the grid G of the 7th transistor M7 is in order to import second D1 of one six bit digital voltage signal 212.
Second position SW in second control signal 216
1In order to start or to forbid the first transistor M1 and transistor seconds M2.Second position SW in second control signal 216
1During for high level, the first transistor M1 and transistor seconds M2 are activated, second reference current I of current-source arrangement 211
Ref1Via the first transistor M1 and the 3rd transistor M3, to 1 charging of first capacitor C.So, reference current I
Ref1Just convert corresponding first store voltages in first capacitor C 1.After 1 charging of first capacitor C finishes, second position SW in second control signal 216
1Change low level into, forbidding the first transistor M1 and transistor seconds M2, and first voltage pinned in first capacitor C 1.
Last SW in second control signal 216
6In order to start or to forbid the 4th transistor M4 and the 5th transistor M5.Last SW in second control signal 216
6During for high-voltage level, the 4th transistor M4 and the 5th transistor M5 are activated, and first voltage that be stored in first capacitor C 1 this moment converts corresponding second store voltages in second capacitor C 2 via the 4th transistor M4 and the 6th transistor M6.After 2 chargings of second capacitor C finish, last SW in second control signal 216
6Change low level into, forbidding the 4th transistor M4 and the 5th transistor M5, and second voltage pinned in second capacitor C 2.If input is second D of the digital voltage signal 212 of a converter 209 so far
1Be high-voltage level, second voltage can convert the second image current I of flow through the 6th transistor M6 and the 7th transistor M7 to
11When field-effect transistor worked in the saturation region, the pass of the voltage difference of its electric current and lock source electrode was
According to this relational expression, (be SW when first capacitor C 1 is in charged state
1Be high-voltage level) time, no matter than W/L, critical voltage and mobility why the shape of the 3rd transistor M3 all can store a corresponding V
GSIn first capacitor C 1.Work as SW
6When being in high-voltage level, it is stored in the V of first capacitor C 1
GSConvert the first image current I to via the 3rd transistor M3
M1To 2 chargings of second capacitor C, because this V
GSStill the 3rd transistor M3 is setovered, so the first image current I
M1Can be equal to reference current I
Ref1In like manner, the second image current I
11Can be equal to the first image current I
M1, promptly be equal to reference current I
Ref1
Therefore, the unit 3 of Fig. 5 is a current mirror arrangement, SW
1In this current mirror arrangement, can be considered one first control signal, in order to starting or to forbid the first transistor M1 and transistor seconds M2, and control reference current I
Ref1Convert first store voltages in first capacitor C 1.SW
6In this current mirror arrangement, can be considered one second control signal, in order to starting or to forbid the 4th transistor M4 and the 5th transistor M5, and control first voltage transitions and become corresponding second store voltages in second capacitor C 2, and the second image current I
11It then is the image current that is produced according to second voltage.This structure can be improved the shortcoming of known current mirror arrangement among Fig. 2, make image current not can along with transistorized shape than the difference of W/L, critical voltage and mobility and change.
The structure of other unit and principle of operation are all identical with unit 3 among Fig. 4.As shown in Figure 4, second utmost point 2nd of the 7th transistor M7 in all second devices 30 3 all is connected to node n1.Therefore, the flow through electric current summation I of this node n1
TOTALBe an analog current signal 218, luminous in order to a pixel that drives among the AMOLED.Converter 209 total N of the present invention are individual, and are luminous in order to N the pixel that drives simultaneously on the AMOLED panel.
From the above, after the luminous digital voltage control signal of pixel on the control AMOLED inputs to data driven unit disclosed in this invention, be convertible into the analog current signal of direct driven for emitting lights diode.Simultaneously, because of transistorized shape than W/L, critical voltage and mobility some error can take place during fabrication, therefore converter disclosed in this invention can be avoided and the coarse analog current signal that produces is undistorted with the brightness of guaranteeing light emitting diode.
Claims (15)
1. data driven unit that is used for active organic LED display (AMOLED) comprises:
One first shift register is in order to provide first control signal of a N position;
One data register responds this first control signal, stores the digital voltage signal of N M position respectively;
One voltage latch unit in order to receiving this N digital voltage signal, and responds an enabling signal, transmits this N digital voltage signal;
One second shift register is in order to provide second control signal of a M+1 position; And
N converter, each converter comprises:
M first device, respond in this second control signal preceding M position one of them, in order to produce individual first image current of M; And
M second device responds last position in this second control signal, and according to this M first image current, with this N digital voltage signal wherein one convert an analog current signal to.
2. data driven unit as claimed in claim 1, wherein after this voltage latch unit is finished all this N digital voltage signals from this data register of reception, this switching signal just can be enabled this voltage latch unit, makes this N digital voltage signal be sent to this N converter.
3. data driven unit as claimed in claim 1, wherein this data driven unit also comprises a current-source arrangement, this current-source arrangement has M output terminal at least, in order to M different reference current value to be provided, produces this M first image current for this first device.
4. data driven unit as claimed in claim 3, wherein this converter also comprises a high level voltage source and a low level voltage source, and this first device comprises:
One the first transistor comprises one first utmost point, one second utmost point and a grid;
One transistor seconds comprises one first utmost point, one second utmost point and a grid;
One the 3rd transistor comprises one first utmost point, one second utmost point and a grid; And
One first electric capacity comprises one first end and one second end;
Wherein, this grid of this first transistor in order to import in this second control signal preceding M position one of them, this of this first transistor second utmost point be connected to these a plurality of output terminals one of them, this of this first transistor first utmost point is connected to this first utmost point and the 3rd transistorized this second utmost point of this transistor seconds, this grid of this transistor seconds is connected to this grid of this first transistor, this of this transistor seconds second utmost point is connected to this second end of the 3rd transistorized this grid and this first electric capacity, and this first end of this first electric capacity is connected to the 3rd transistorized this first utmost point and this high level voltage source.
5. data driven unit as claimed in claim 4, wherein this second device comprises:
One the 4th transistor comprises one first utmost point, one second utmost point and a grid;
One the 5th transistor comprises one first utmost point, one second utmost point and a grid;
One the 6th transistor comprises one first utmost point, one second utmost point and a grid;
One the 7th transistor comprises one first utmost point, one second utmost point and a grid; And
One second electric capacity comprises one first end and one second end;
Wherein, the 4th transistorized this grid is in order to import last position in this second control signal, the 4th transistorized this second utmost point is connected to the 3rd transistorized this second utmost point, the 4th transistorized this first utmost point is connected to the 5th transistorized this first utmost point and the 6th transistorized this second utmost point, the 5th transistorized this grid is connected to the 4th transistorized this grid, the 5th transistorized this second utmost point is connected to this second end of the 6th transistorized this grid and this second electric capacity, this first end of this second electric capacity is connected to the 6th transistorized this first utmost point and this low level voltage source, the 7th transistorized this first utmost point is connected to the 6th transistorized this second utmost point, and the 7th transistorized this grid is in order to import wherein in this M bit digital voltage signal.
6. data driven unit as claimed in claim 5, wherein the 7th transistorized this in this M second device second extremely all is connected in a node, and the electric current summation of this node of flowing through is this analog current signal.
7. a digital voltage responds one first control signal and one second control signal to the analog current converter, converts an analog current signal in order to the digital voltage signal with a M position, comprises:
M first device responds this first control signal, in order to produce M first image current; And
M second device responds this second control signal, and according to this M first image current, converts this digital voltage signal to this analog current signal.
8. digital voltage as claimed in claim 7 is to the analog current converter, and wherein this digital voltage to analog current converter also comprises:
One current-source arrangement has M output terminal at least, in order to M different reference current value to be provided, produces this M first image current for this first device;
One high level voltage source; And
One low level voltage source.
9. digital voltage as claimed in claim 8 is to the analog current converter, and wherein this first device comprises:
One the first transistor comprises one source pole, a drain electrode and a grid;
One transistor seconds comprises one source pole, a drain electrode and a grid;
One the 3rd transistor comprises one source pole, a drain electrode and a grid; And
One first electric capacity comprises one first end and one second end;
Wherein, this grid of this first transistor is in order to import this first control signal, this drain electrode of this first transistor be connected to these a plurality of output terminals one of them, this source electrode of this first transistor is connected to this source electrode and the 3rd transistorized this drain electrode of this transistor seconds, this grid of this transistor seconds is connected to this grid of this first transistor, this drain electrode of this transistor seconds is connected to this second end of the 3rd transistorized this grid and this first electric capacity, and this first end of this first electric capacity is connected to the 3rd transistorized this source electrode and this high level voltage source.
10. digital voltage as claimed in claim 9 is to the analog current converter, and wherein this second device comprises:
One the 4th transistor comprises one source pole, a drain electrode and a grid;
One the 5th transistor comprises one source pole, a drain electrode and a grid;
One the 6th transistor comprises one source pole, a drain electrode and a grid;
One the 7th transistor comprises one source pole, a drain electrode and a grid; And
One second electric capacity comprises one first end and one second end;
Wherein, the 4th transistorized this grid is in order to import this second control signal, the 4th transistorized this drain electrode is connected to the 3rd transistorized this drain electrode, the 4th transistorized this source electrode is connected to the 5th transistorized this source electrode and the 6th transistorized this drain electrode, the 5th transistorized this grid is connected to the 4th transistorized this grid, the 5th transistorized this drain electrode is connected to this second end of the 6th transistorized this grid and this second electric capacity, this first end of this second electric capacity is connected to the 6th transistorized this source electrode and this low level voltage source, the 7th transistorized this source electrode is connected to the 6th transistorized this drain electrode, and the 7th transistorized this grid is in order to import wherein in this M bit digital voltage signal.
11. digital voltage as claimed in claim 10 is to the analog current converter, wherein the 7th transistorized this drain electrode in individual second device of this M all is connected in a node, and the electric current summation of this node of flowing through is this analog current signal.
12. a current mirror arrangement comprises:
One current-source arrangement;
One high level voltage source;
One low level voltage source;
One first control signal;
One second control signal;
One the first transistor comprises one source pole, a drain electrode and a grid;
One transistor seconds comprises one source pole, a drain electrode and a grid;
One the 3rd transistor comprises one source pole, a drain electrode and a grid;
One the 4th transistor comprises one source pole, a drain electrode and a grid;
One the 5th transistor comprises one source pole, a drain electrode and a grid;
One the 6th transistor comprises one source pole, a drain electrode and a grid;
One first electric capacity comprises one first end and one second end; And
One second electric capacity comprises one first end and one second end;
Wherein, this grid of this first transistor is in order to import this first control signal, this drain electrode of this first transistor is connected to this current-source arrangement, this source electrode of this first transistor is connected to this source electrode and the 3rd transistorized this drain electrode of this transistor seconds, this grid of this transistor seconds is connected to this grid of this first transistor, this drain electrode of this transistor seconds is connected to this second end of the 3rd transistorized this grid and this first electric capacity, this first end of this first electric capacity is connected to the 3rd transistorized this source electrode and this high level voltage source, the 4th transistorized this grid is in order to import this second control signal, the 4th transistorized this drain electrode is connected to the 3rd transistorized this drain electrode, the 4th transistorized this source electrode is connected to the 5th transistorized this source electrode and the 6th transistorized this drain electrode, the 5th transistorized this grid is connected to the 4th transistorized this grid, the 5th transistorized this drain electrode is connected to this second end of the 6th transistorized this grid and this second electric capacity, this first end of this second electric capacity is connected to the 6th transistorized this source electrode and this low level voltage source, and the 6th transistorized current value size of flowing through is identical substantially with this current-source arrangement.
13. current mirror arrangement as claimed in claim 12, wherein this first control signal is in order to start or to forbid this first transistor and this transistor seconds, when this first transistor and this transistor seconds are activated, this current-source arrangement converts corresponding one first store voltages in this first electric capacity through the 3rd transistor.
14. current mirror arrangement as claimed in claim 13, wherein this second control signal is in order to start or to forbid the 4th transistor and the 5th transistor, when the 4th transistor and the 5th transistor are activated, this first voltage converts corresponding one second store voltages in this second electric capacity through the 6th transistor
15. current mirror arrangement as claimed in claim 14, wherein when the 4th transistor and the 5th transistor are under an embargo, this second voltage transitions the 6th transistorized this electric current that becomes to flow through.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031205291A CN1317688C (en) | 2003-03-13 | 2003-03-13 | Data driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031205291A CN1317688C (en) | 2003-03-13 | 2003-03-13 | Data driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1530915A true CN1530915A (en) | 2004-09-22 |
| CN1317688C CN1317688C (en) | 2007-05-23 |
Family
ID=34285390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031205291A Expired - Fee Related CN1317688C (en) | 2003-03-13 | 2003-03-13 | Data driver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1317688C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414591C (en) * | 2004-10-08 | 2008-08-27 | 三星Sdi株式会社 | Light emitting display and data driver there of |
| CN101098145B (en) * | 2006-06-30 | 2010-05-12 | 中华映管股份有限公司 | Digital simulation data transducer and transducing method |
| US7733307B2 (en) | 2005-08-16 | 2010-06-08 | Samsung Mobile Display Co., Ltd. | Emission driver for organic light emitting display device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4384274A (en) * | 1979-06-22 | 1983-05-17 | American Microsystems, Inc. | Current mirror digital to analog converter |
| US4594577A (en) * | 1980-09-02 | 1986-06-10 | American Microsystems, Inc. | Current mirror digital to analog converter |
| DE19807856A1 (en) * | 1998-02-25 | 1999-08-26 | Philips Patentverwaltung | Circuit arrangement with current-digital-analog converters |
| US6166670A (en) * | 1998-11-09 | 2000-12-26 | O'shaughnessy; Timothy G. | Self calibrating current mirror and digital to analog converter |
| TW493153B (en) * | 2000-05-22 | 2002-07-01 | Koninkl Philips Electronics Nv | Display device |
| KR100344810B1 (en) * | 2000-07-26 | 2002-07-20 | 엘지전자주식회사 | current drive circuit using high voltage element |
| SG111928A1 (en) * | 2001-01-29 | 2005-06-29 | Semiconductor Energy Lab | Light emitting device |
| US7209101B2 (en) * | 2001-08-29 | 2007-04-24 | Nec Corporation | Current load device and method for driving the same |
-
2003
- 2003-03-13 CN CNB031205291A patent/CN1317688C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414591C (en) * | 2004-10-08 | 2008-08-27 | 三星Sdi株式会社 | Light emitting display and data driver there of |
| US7733307B2 (en) | 2005-08-16 | 2010-06-08 | Samsung Mobile Display Co., Ltd. | Emission driver for organic light emitting display device |
| CN101098145B (en) * | 2006-06-30 | 2010-05-12 | 中华映管股份有限公司 | Digital simulation data transducer and transducing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1317688C (en) | 2007-05-23 |
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