CN1529285A - Bit plane parallel rate distortion optimized cut-out built-in code block coding structure - Google Patents

Abstract

The structure comprises wavelet transformer, wavelet coefficient follower, external storage device, parallel bit plane encoder, parallel buffer, compound selector, and arithmetical encoder. Wavelet transform is carried out for image by wavelet transformer so as to obtain wavelet coefficients. Wavelet coefficient follower does following things: reading out coefficients, and sending it to each paralleled bit plane encoder, organizing state variable value of coefficient in relevant plane, storing each value to corresponding memory with dual ports in chip, generating context and data information, storing said information to context buffer. Context and data in each buffer through compound selector are merged and output to arithmetical encoder to carry out compressed encoding, which is provided for subsequent encoding module to carry out optimized intercepting so as to form standard code flow. The invention is suitable to image compressed encoding and network transmission of video data.

Description

The rate-distortion optimization intercepting built-in code block coding structure of bit plane parallel

Technical field

The present invention relates to technical field of image processing, particularly a kind of rate-distortion optimization of bit plane parallel intercepts built-in code block coding (EBCOT) structure, is used for the image compression encoding of various digital devices.

Background technology

Along with multimedia and development of internet technology and application, existing Joint Photographic Experts Group JPEG can not satisfy current market and requirement of actual application, and International Standards Organization has formulated the new standard JPEG2000 of rest image compression in November, 2000 for this reason.This new standard has adopted Australian scholar David Taubman at High PerformanceScalable Image Compression with EBCOT (IEEE Trans.Image Processing, vol.9, no.7, pp.1158-1170, July 2000) wavelet transformation and the rate-distortion optimization intercepting built-in code block encryption algorithm (EBCOT) that propose in the literary composition, this algorithm is divided into T1 and T2 two parts.T1 is made up of embedded bit-plane coding and MQ arithmetic encoder, finishes context and forms and arithmetic coding; Control of T2 part completion rate and code stream tissue.When carrying out rate-distortion optimization intercepting built-in code block encryption algorithm (EBCOT) coding, each wavelet sub-band is divided into littler code block (as 64 * 64), is that unit independently makes the T1 coding with the code block.The bitstream length that different code blocks produces is inequality, and they also are different to the contribution that recovers picture quality.Therefore for the bit stream of all code blocks generations, T2 has adopted the rate-distortion optimization technology to carry out the back compression and has handled, and finishes the rate control and the tissue of code stream.

Below the entropy coding principle among the new standard JPEG2000 of rest image compression is described:

If code block B _iIn quantization parameter be q _i[m, n] represents Δ with the form of symbol-amplitude _iBe corresponding quantization step-length, M _iBe q _iThe bit-planes number of [m, n], χ _i[m, n] is sign bit (0 expression positive number, 1 expression negative), v _i[m, n] is M _iThe range value of-bit.Make v _i ^p[m, n] is v _iThe bit of [m, n] p layer, wherein 0≤p＜M _iAnd p=0 is corresponding to lowest order LSB.Bit-plane coding is exactly at first to transmit most significant digit MSB:v _i ^Mi-1[m, n], transmission time important bit-planes then.

For effectively to v _i ^p[m, n] encodes, and utilized current sampling point s here _iCoded message before [m, n] and the adjacent spots, i.e. context.Each coefficient in the code block has a binary-state variable σ _i[m, n] is initialized as 0, represents that current coefficient is unessential, to first non-zero bit v _i ^p[m, n] ≠ 0 becomes 1 when encoding, and represents that current coefficient is important, σ _i[m, n] is called s _i" significance state " of [m, n].Wherein, at bit-planes p to s _iIn [m, n] when coding, the new standard JPEG2000 of rest image compression has used four kinds of coding units: " Zero-code " (ZC), " symbolic coding " (SC), " amplitude refinement " (MR) and " Run-Length Coding " (RLC).

If sampling point is unessential, i.e. σ _iWhether [m, n]=0 then uses Zero-code ZC or the Run-Length Coding RLC sampling point of encoding important at current bit-planes; If sampling point becomes important, then use symbolic coding SC to come the coded identification position and put σ _i[m, n] is 1; If sampling point is important at a last bit-planes, i.e. σ _i[m, n]=1 is then by the amplitude refinement MR v that encodes _i ^p[m, n].In each case, a coding unit output binit (0 or 1) and current context, and send arithmetic encoder MQ to and compress.The symbol of Zero-code ZC output is v _i ^p[m, n], its context state are the importance of 8 adjacent spots of current sampling point.Therefore current coefficient can have 256 kinds of context states at most, in order to reduce implementation complexity, according to some special regular clusters, can be these 256 kinds of state reductions 9 kinds of contexts.If v _i ^pSymbolic coding SC is then carried out in [m, n] ≠ 0.The symbol of this symbolic coding SC output is

Wherein

Be to represent XOR by the sign prediction value symbol that the context state of symbolic coding SC is determined.The context state of symbolic coding SC is made up of the importance and the corresponding symbol thereof of 4 sampling points up and down, and therefore 256 kinds of states are also arranged, and the new standard JPEG2000 that rest image compresses is reduced to 5 contexts with it.The output of amplitude refinement MR coding is v _i ^p[m, n] introduces another state variable σ here _i' [m, n] is used for representing whether use for the first time amplitude refinement MR coding.Pass through σ _iThe significance state of ' [m, n] and adjacent spots is divided into 3 kinds of contexts.Run-Length Coding RLC is used for handling continuous 4 sampling points of same row, to reduce the number of continuous 0 symbol.If the σ of 4 coefficients of these row _iRun-Length Coding RLC is then adopted in [m, n]=0 and all do not have important neighbours, and whether output wherein has v _i ^p[m, n]=1, it has only a context.If Run-Length Coding RLC in when coding 4 coefficients, have at least one become important, the position (two bits) that then will export first significant coefficient, fixing context is adopted in the output of position, its probability model is equally distributed.Then first significant coefficient is carried out symbolic coding SC, the coefficient of back carries out Zero-code ZC.When encoding, the bit-plane coding of quantization parameter is undertaken by following three cataloged procedures, has used one or more operations in above-mentioned Zero-code ZC, symbolic coding SC, amplitude refinement MR and four kinds of coding units of Run-Length Coding RLC in each step.In each cataloged procedure, the band that the coefficient in the code block is formed according to every four lines scans, and according to the row sequential scanning, till sweeping all over all coefficients in the intact code block, scanning sequency as shown in Figure 5 in the band.

Concrete bit-plane coding method is as follows:

The first step is carried out importance and is propagated P _i ^{P, 1}, promptly, carry out symbolic coding SC if coefficient becomes important for inessential but have important neighbours' coefficient to carry out Zero-code ZC;

Second step was carried out amplitude refinement P _i ^{P, 2},, carry out amplitude refinement MR coding promptly for important coefficient;

P is upgraded in the cleaning of the 3rd step _i ^{P, 3}, promptly carry out Zero-code ZC or Run-Length Coding RLC, if having coefficient to become important then carry out symbolic coding SC for coefficient inessential and that do not encode.

Return the first step and carry out the coding of next bit-planes p-1.

Though Australian scholar David Taubman is at High Performance Scalable ImageCompression with EBCOT (IEEE Trans.Image Processing, vol.9, no.7, pp.1158-1170, July2000) method that has provided the built-in code block coding (EBCOT) of wavelet transformation and rate-distortion optimization intercepting in the literary composition is described, but does not have concrete hardware implementation structure.Therefore, many scholars are devoted to the research of built-in code block coding (EBCOT) hardware configuration of rate-distortion optimization intercepting, and have proposed realization rate-distortion optimization intercepting built-in code block coding (EBCOT) hardware configuration.For example, American scholar Kishore Andra is respectively at IEEE Trans.on Circuits and Systemfor Video Technology periodical in 2003 A High-Performance JPEG2000 Architecture (Vol.13 that publishes an article, No.3 March 2003 pp209-218) and its PhD dissertation Wavelet and Entropy Coding Accelerators forJPEG2000, Arizona State University provides the hardware configuration of realizing rate-distortion optimization intercepting built-in code block coding (EBCOT) in detail among the December 2001.The principal feature of this structure has: 1) realize the input of status information by combinational logic; 2) status information is stored in 3 internal memories; 3) state and amplitude information are stored in 5 registers; 4) pass through the control of the state machine realization of one 24 state to whole module.And for example, Taiwan's scholars Chung-Jr Lian Chung-JrLian has also provided realization rate-distortion optimization intercepting built-in code block coding (EBCOT) hardware configuration in detail at IEEE Trans.on Circuits and System for Video Technology periodical in 2003 the Analysis and Architecture Design of Block Coding Engine for EBCOT in JPEG2000 (Vol.13, No.3 March 2003 pp219-230) that publishes an article.The principal feature of this structure has: 1) total is handled based on row; 2) adopt pixel to skip and row are skipped the raising processing speed.

Above-mentioned two kinds of structures that adopt hardware to realize rate-distortion optimization intercepting built-in code block coding (EBCOT), though represented the state-of-the-art technology of current hardware JPEG2000, but because these two kinds of structures adopt when handling the coded-bit plane is the serial mode of encoding successively to the lowest bit plane from higher bit plane, thereby coding rate and efficient are lower, and 24 state machines that American scholar Andra adopts are controlled, complex structure produces the clock waste at single pixel position easily.

The technical scheme of invention

Rate-distortion optimization intercepting built-in code block coding (EBCOT) hardware configuration that the purpose of this invention is to provide a kind of bit plane parallel is to overcome existing serial hardware configuration coding rate and the lower deficiency of efficient when realizing rest image compression new standard JPEG2000.

The key problem in technology of realizing the object of the invention is that parallel processing is carried out on the coded-bit plane, adopt combinational logic to realize the coding module structure, mainly comprise wavelet transformer, external memory storage, wavelet coefficient follower, parallel bit surface encoder, parallel buffer, the final election device, arithmetic encoder, wherein:

Wavelet transformer is used for raw image data is carried out wavelet transform, and conversion coefficient is write external memory storage;

External memory storage is used to store wavelet conversion coefficient;

The wavelet coefficient follower is used for reading wavelet coefficient by the resolution incremental order, and per four points are a band, and outputs to each parallel bit surface encoder;

The parallel bit surface encoder is used for each band of wavelet coefficient follower output is carried out simultaneously the tissue of bit-plane coding and state variable, and state variable is upgraded simultaneously;

Parallel buffer is used to deposit the contextual information from each parallel bit surface encoder input, and reads this contextual information successively;

The final election device is used for selecting output from a plurality of context informations of each parallel buffer input;

Arithmetic encoder is used for the contextual information from the input of final election device is carried out compressed encoding and exports compressed bit stream.

The rate-distortion optimization of above-mentioned bit plane parallel intercepting built-in code block coding structure, wherein the bit-plane coding device is mainly by status register, the context generator, the context follower, context buffer, controller, the stage counter, status register is formed; This status register adopts dual-ported memory in the sheet, is used to deposit the status information of each all band of code block; This context generator adopts the combinational logic gate array, is used for producing context and data and is sent to the context follower; This context follower is used to read context and the data that the context generator generates, and is written in the context buffer; This controller is used to produce the control signal of state of a control storer and status register; This stage counter is used for producing indication cataloged procedure signal, and promptly present located such as importance are propagated, and amplitude refinement and cleaning renewal wait the specific coding process; This status register adopts the status register (LEFT, MIDDLE, RIGHT) of three 30 bit wides in left, center, right, is used for the stripe information of temporary status register.

The rate-distortion optimization intercepting built-in code block coding structure of above-mentioned bit plane parallel, the output of wherein left status register LEFT is connected with the context generator with status register respectively, be used to finish to the renewal of state variable and participate in contextual formation, the input of right status register RIGHT is connected to the output terminal of status register, the output of right status register RIGHT is connected respectively to the input end of context generator and middle status register MIDDLE, in order to status register MIDDLE in participating in contextual formation and upgrading, the output of middle status register MIDDLE is connected to the context generator and participates in contextual formation.

The rate-distortion optimization intercepting built-in code block coding structure of above-mentioned bit plane parallel, wherein the context generator is according to the status values of three status registers (LEFT, MIDDLE, RIGHT), produce 15 data-signals of four positions simultaneously with the combinational logic form, promptly (7), position (8), position (9), position (10) produce Zero-code (ZC) in the position respectively, symbolic coding (SC) and amplitude refinement (MR), and three context data signals of Run-Length Coding (RLC), referring to Fig. 3.

The rate-distortion optimization intercepting built-in code block coding structure of above-mentioned bit plane parallel, wherein the location point number of each band is four wavelet coefficient points and up-and-down boundary sum, be 4+2, the state variable of each location point needs five bits, i.e. and significance state position (σ), the amplitude position is (v), sign bit (χ), visit position (η) and refinement mode bit (σ '), this significance state position (σ) and refinement mode bit (σ '), each bar has 30 state variables.

The rate-distortion optimization of above-mentioned bit plane parallel intercepting built-in code block coding structure, wherein the significance state (σ) in five state variables is relevant with the bit-planes position with refinement state (σ '), that is:

${\mathrm{\σ}}_p=\underset{i=p+1}{\overset{\mathrm{MSB}}{\mathrm{\Σ}}}{\mathrm{\ν}}_i[m,n],{\mathrm{\σ}}_p^{\′}={\mathrm{\σ}}_{p+1}$

In the formula, p is bits of encoded plane number

σ _pIt is the significance state that p bit-planes location point [m, n] is located

ν _i[m, n] is the amplitude of location point [m, n] at i bit-planes place

σ ' _pIt is the refinement state that p bit-planes location point [m, n] is located

σ _P+1It is the significance state that p+1 bit-planes location point [m, n] is located

The amplitude position of each bit-planes (is determined at the numerical value of this bit-planes by wavelet coefficient that v) sign bit (χ) is determined that by the symbol of wavelet coefficient visit position (η) is determined when coding.

The present invention is owing to adopt coded-bit plane parallel processing to reach the structure that is realized coding module by combinational logic, not only made full use of the degree of parallelism between bit-planes, and overcome the complicacy of state machine control, avoided producing the phenomenon of clock waste, so coding rate and efficient have had and have significantly improved at single pixel position.Table 1 has provided the clock periodicity of actual measurement Lena and Barbara two first code blocks of width of cloth image actual needs under serial and parallel mode, the code fetch block size is 32 * 32, wherein the parallel mode of Lena image has reduced 86.42% than the execution time of serial mode, and the parallel mode of Barbara image has reduced 86.36% than the execution time of serial mode.By the Lena image is estimated, entire image needs 128000 clock period, the height as a result that efficiency ratio Taiwan's scholars Chung-Jr Lian provides at the most.The results of running shows that system's maximum clock frequency can reach 52.247MHz.Table 2 provides and adopts bit plane parallel structure JPEG2000-BP algorithm and based on the JPEG2000 algorithm of wavelet transformation spiht algorithm and standard, the result that three width of cloth test patterns of different resolution are obtained under different code checks, from table 2 as seen, although the present invention has improved about order of magnitude on speed, and basic and existing rest image compresses new standard JPEG2000 and suitable based on the wavelet transformation spiht algorithm on Y-PSNR (PSNR) performance.Therefore, the present invention has huge using value in a plurality of fields such as image retrieval, Internet transmission, network browsing, text image, digital camera, medical image, remote sensing images and desktop printings.Especially showing its high-quality aspect the Network Transmission of video data, big ratio of compression, remarkable advantages such as anti-error code capacity.The present invention simultaneously also can be used for the severals biography system of reconnaissance satellite, reaches the military fields such as monitoring in battlefield.

The execution time of table 1 parallel mode and serial mode relatively

Gray level image (512 * 512)	Execution time
				Serial mode	Parallel mode	Reduction
	????Lena	????36430	????4947				?31483(86.42％)
????Barbara				????37519	????5116	?32403(86.36％)

Table 2 Y-PSNR

Image	Bit rate (bpp)	????SPIHT	??JPEG2000	??JPEG2000-BP
					Lena (512× 512)	????1.0	????40.41	????40.61	????40.05
????0.5	????37.21	????37.43	????37.14
				????0.25		????34.11	????34.28	????34.10
????0.125	????31.10	????31.22	????31.05
				????0.0625		????28.38	????28.30	????28.07
Barbara (512× 512)	????1.0	????36.41	????37.37						????36.94
				????0.5	????31.39	????32.48	????32.28
	????0.25	????27.58	????28.55					????28.39
				????0.125	????24.86	????25.55	????25.30
	????0.0625	????23.35	????23.45					????23.33
				Airport (1024× 1024)	????1.0	????-	????33.23		????33.09
????0.5	????-	????30.42	????30.40
					????0.25	????-	????28.27	????28.25
????0.125	????-	????26.44	????26.44
					????0.0625	????-	????24.70	????24.62

Description of drawings:

Fig. 1 is the bit-plane coding system construction drawing that the present invention walks abreast

Fig. 2 is a bit-plane coding device structural drawing of the present invention

Fig. 3 is the bar tape handling location drawing of the present invention

Fig. 4 is a mode bit register map of the present invention

Fig. 5 is the band scanning sequency figure of the present invention to regular (Regular) mode

Fig. 6 (a) is that the present invention is to Lena video bits number of planes-Y-PSNR curve map

Fig. 6 (b) is that the present invention is to Barbara video bits number of planes-Y-PSNR curve map

Embodiment:

Structure of the present invention is to adopt XILINX ISE 5.1 integrated developing software and VHDL, Verilog HDL language, realizes on the XCV600e-6BG432 of XILINX company programmable chip.

With reference to Fig. 1, parallel bit plane coding system architecture of the present invention comprises wavelet transformer, external memory storage (not drawing among the figure), wavelet coefficient follower, parallel bit surface encoder, parallel buffer, final election device, arithmetic encoder.Wavelet transformer is at first carried out the wavelet coefficient that wavelet transform obtains frequency field to original image, is deposited into external memory storage.This small echo is selected integer 5/3 small echo of JPEG2000 suggestion, and the quantization step of wavelet coefficient is 1, and wavelet series is 3.By the wavelet coefficient follower according to the progressive requirement of resolution, wavelet coefficient read by the sum of series frequency band give each parallel bit-plane coding device, according to the value of wavelet coefficient at each bit-planes, organize the state variable value of this coefficient, and this state variable value is stored in the interior dual-ported memory of corresponding sheet at corresponding flat.Each bit-plane coding device reception wavelet coefficient and state variable generate corresponding context and data message at the numerical value on this plane according to coding requirement.Context that generates and deposit data are in the parallel context buffer of each plane correspondence, and context in each impact damper and data are selected to output to arithmetic encoder by the final election device and carried out compressed encoding.The compressed bit stream that is produced by arithmetic encoder offers the next code device and is optimized intercepting, finally forms the standard code stream.

With reference to Fig. 2, bit-plane coding device structure of the present invention is mainly by status register, status register, and the context generator, the context follower, context buffer, controller, the stage counter is formed.Wherein status register is the interior dual-ported memory of sheet of depositing the status information of all bands of code block; Status register is made as three of left, center, right (LEFT, MIDDLE, RIGHT), 30 bit status registers of three bands in these three status registers difference corresponding diagram 3, the enable signal of squeezing into of these three status registers is respectively LEFT_EN, MID_EN and RIGHT_EN; The context generator adopts the combinational logic gate array that produces context and data, is the nucleus module of whole encoder; Context that the context follower generates the context generator and data are read and are written in the context buffer; Controller mainly is the control signal that produces state of a control storer and three band registers, is the control module of whole encoder; The stage counter is the counting module of cataloged procedure, produces indication cataloged procedure signal, and promptly present located such as importance are propagated, and amplitude refinement and cleaning renewal wait the specific coding process.The output of left side register LEFT is connected to the input end of status register, the last state variate-value that the context generator is produced when encoding writes back in the status register, finish renewal process to state variable, can make by upgrading that employed state variable value is up-to-date in the next code process, with the correctness of guaranteeing to encode.The output of register LEFT simultaneously also is connected to the context generator and participates in contextual formation.The input of middle register MIDDLE is connected to the output of right register RIGHT, and the output of middle register MIDDLE is connected to the context generator and participates in contextual formation.The output of right register RIGHT is connected to the context generator and participates in contextual formation, the input of register MIDDLE in being connected to simultaneously, and in order to register MIDDLE in upgrading, the input of right register RIGHT is connected to the output terminal of status register.

Cataloged procedure is as follows:

The first step is finished the importance communication process.Promptly by the enabling signal of scrambler reception from wavelet transformer, the stage counter is designated as importance and propagates, and to controller reset begin the coding, controller is read three stripe information in the status register successively and is written to three status registers respectively, after the context generator receives the numerical value of three status registers, produce corresponding context and data message by its inner combinational logic array, and pass through the context follower in context and the data message write buffer.Repeat said process then, finish the importance of all bands of a code block and propagate coding.

In second step, finish the amplitude thinning process.By carrying out amplitude refinement cataloged procedure with first step same steps as, at this moment the stage counter is designated as the amplitude refinement to above-mentioned code block.

In the 3rd step, finish the cleaning renewal process.Above-mentioned code block is cleared up renewal, and at this moment the stage counter is designated as the cleaning renewal.

So far next code block coding is carried out in code block end-of-encode, after all code block end-of-encodes, finishes the bit-plane coding to entire image.

Fig. 3 has provided the bar tape handling position of state variable tissue, each band is made up of six location points, each location point all includes significance state position (σ) at each code plane, the amplitude position (v), sign bit (χ), visit position (η) and five state variables of refinement mode bit (σ '), the state variable figure place of each location point is five, totally three ten of the state variables of each band.Location point 7,8,9,10 among Fig. 3 is illustrated in when handling each band, and the context window is considered current four positions to be processed, and location point 6 and 11 is illustrated in the adjacent ribbons position, the left and right sides that will consider when handling each band.Since to the processing sequence of coding be with the band be unit from left to right, carry out from the top down, so each band can be considered as basic processing unit, can avoid the clock waste that brings when some position does not produce context output in the band like this.

The rate-distortion optimization of above-mentioned bit plane parallel intercepting built-in code block coding structure, wherein the significance state (σ) in five state variables is relevant with the bit-planes position with refinement state (σ '), that is:

${\mathrm{\σ}}_p=\underset{i=p+1}{\overset{\mathrm{MSB}}{\mathrm{\Σ}}}{\mathrm{\ν}}_i[m,n],{\mathrm{\σ}}_p^{\′}={\mathrm{\σ}}_{p+1}$

In the formula, p is bits of encoded plane number

σ _pIt is the significance state that p bit-planes location point [m, n] is located

v _i[m, n] is the amplitude of location point [m, n] at i bit-planes place

σ ' _pIt is the refinement state that p bit-planes location point [m, n] is located

σ _P+1It is the significance state that p+1 bit-planes location point [m, n] is located

(v) different, this amplitude position is determined at the numerical value of this bit-planes that by wavelet coefficient sign bit (χ) is determined that by the symbol of wavelet coefficient visit position (η) is determined when coding in the amplitude position of each bit-planes.So far, the status information of each bit-planes can obtain simultaneously, has so just guaranteed the feasibility of bit plane parallel coding.

Referring to Fig. 4, work as the location label of pre-treatment band among first behavior Fig. 3, the pairing status information of each location point of second behavior position.

Referring to Fig. 5, band of the present invention scanning and context generation are two kinds of optional regular band scanning sequency Regular and the vertical strip scanning sequency Vertical causal that provides by JPEG2000.Adopt regular band scanning sequency Regular mode, if code block size is 32 * 32, totally 256 bands, it is according to the value of three status registers (LEFT, MIDDLE, RIGHT) that context data generates, and produces the data of four positions simultaneously with the combinational logic form.Though handle successively four of a band positions as can be seen from Fig. 4, the context that each position produces can be predicted fully simultaneously, and just all context datas that this band should generate in a clock can obtain simultaneously.When encoding, the context number that can generate at most is 15 for each band, and they are respectively: the Zero-code of position 7 (ZC), symbolic coding (SC) and amplitude refinement (MR); The Zero-code of position 8 (ZC), symbolic coding (SC) and amplitude refinement (MR); The Zero-code of position 9 (ZC), symbolic coding (SC) and amplitude refinement (MR); The Zero-code of position 10 (ZC), symbolic coding (SC) and amplitude refinement (MR); And three contexts of Run-Length Coding (RLC).These context datas can obtain by the state value of band, and can set when the context useful signal is specified this context whether effectively for output and use.For example, the Zero-code of position 7 (ZC) context is decided according to standard code by the state variable of position 0,1,2,6,8 and 11,12,13, and the status information of these 8 adjacent positions then can obtain in three status registers.So just can make context and line output in the band, save clock to a great extent.The context follower is exactly in conjunction with these 15 contextual useful signals effective context that this band generates to be exported successively.

Referring to Fig. 6, the present invention can adjust parallel bit-planes number by quantification dead band (DEADZONE) is set according to the JPEG2000 quantitative criteria, to obtain the relation between bit-planes number and the picture quality, determines required bit-planes number.Fig. 6 is the Lena that obtains with software and the bit-planes number and Y-PSNR (PSNR) curve of Barbara image, wherein Fig. 6 (a) is to Lena video bits number of planes-Y-PSNR curve map, Fig. 6 (b) is smooth to Barbara video bits number of planes-Y-PSNR curve map visible curve two ends, center section descends to some extent, and this just means that there is no need to be provided with maximum bit-planes number obtains the highest Y-PSNR (PSNR).Under the constraint of hardware resource, generally select the number of planes of upper middle point as the actual pairing coding, for example scope is between the 8-12.Through behind the wavelet transformation, the bit wide of wavelet coefficient is exactly the principal element that parallel encoding plane number is participated in decision.For integer 5/3 small echo based on lifting, general wavelet coefficient can be used 12+1 potential source representation, comprising a bit sign position.

Claims (6)

1. the rate-distortion optimization of a bit plane parallel intercepts the built-in code block coding structure, it is characterized in that comprising:

Wavelet transformer is used for raw image data is carried out wavelet transform, and conversion coefficient is write external memory storage;

External memory storage is used to store wavelet conversion coefficient;

The wavelet coefficient follower is used for reading wavelet coefficient by the resolution incremental order, and per four points are a band, and outputs to each parallel bit surface encoder;

The parallel bit surface encoder is used for each band of wavelet coefficient follower output is carried out simultaneously the tissue of bit-plane coding and state variable, and state variable is upgraded simultaneously;

Parallel buffer is used to deposit the contextual information from each parallel bit surface encoder input, and reads this contextual information successively;

The final election device is used for selecting output from a plurality of context informations of each parallel buffer input;

Arithmetic encoder is used for the contextual information from the input of final election device is carried out compressed encoding and exports compressed bit stream.

2. coding structure according to claim 1 is characterized in that each parallel bit surface encoder mainly by status register, the context generator, and the context follower, context buffer, controller, the stage counter, status register is formed; This status register adopts dual-ported memory in the sheet, is used to deposit the status information of each all band of code block; This context generator adopts the combinational logic gate array, is used for producing context and data and is sent to the context follower; This context follower is used to read context and the data that the context generator generates, and is written in the context buffer; This controller is used to produce the control signal of state of a control storer and status register; This stage counter is used for producing indication cataloged procedure signal, and promptly present located such as importance are propagated, and amplitude refinement and cleaning renewal wait the specific coding process; This status register adopts the status register (LEFT, MIDDLE, RIGHT) of three 30 bit wides in left, center, right, is used for the stripe information of temporary status register.

3. coding structure according to claim 1 and 2, the output that it is characterized in that left status register (LEFT) is connected with the context generator with status register respectively, be used to finish to the renewal of state variable and participate in contextual formation, the input of right status register (RIGHT) is connected to the output terminal of status register, the output of right status register (RIGHT) is connected respectively to the input end of context generator and middle status register (MIDDLE), in order to status register (MIDDLE) in participating in contextual formation and upgrading, the output of middle status register (MIDDLE) is connected to the context generator and participates in contextual formation.

4. coding structure according to claim 1 and 2, it is characterized in that the status values of context generator according to three status registers in left, center, right (LEFT, MIDDLE, RIGHT), produce 15 data-signals of four positions simultaneously with the combinational logic form, promptly (7), position (8), position (9), position (10) produce Zero-code (ZC) in the position respectively, symbolic coding (SC) and amplitude refinement (MR), and three context data signals of Run-Length Coding (RLC).

5. coding structure according to claim 1 and 2, the location point number that it is characterized in that each band is four wavelet coefficient points and up-and-down boundary sum, be 4+2, the state variable of each location point needs five bits, i.e. and significance state position (σ), the amplitude position is (v), sign bit (x), visit position (η) and refinement mode bit (σ '), this significance state position (σ) and refinement mode bit (σ '), each bar has 30 state variables.

6. coding structure according to claim 5 is characterized in that five significance states (σ) in the state variable are relevant with the bit-planes position with refinement state (σ '), promptly ${\mathrm{\σ}}_p=\underset{i=p+1}{\overset{\mathrm{MSB}}{\mathrm{\Σ}}}{v}_i[m,n]$ σ′ _p＝σ _p+1，

In the formula, p is bits of encoded plane number

σ _pIt is the significance state that p bit-planes location point [m, n] is located

v _i[m, n] is the amplitude of location point [m, n] at i bit-planes place

σ ' _pIt is the refinement state that p bit-planes location point [m, n] is located

σ _P+1It is the significance state that p+1 bit-planes location point [m, n] is located

The amplitude position of each bit-planes (is determined at the numerical value of this bit-planes by wavelet coefficient that v) sign bit (x) is determined that by the symbol of wavelet coefficient visit position (η) is determined when coding.

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