CN1241391C - Channel parallel realizing method for down position plane coder under JPEG 2000 range associated mode - Google Patents
Channel parallel realizing method for down position plane coder under JPEG 2000 range associated mode Download PDFInfo
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- CN1241391C CN1241391C CN 200410026017 CN200410026017A CN1241391C CN 1241391 C CN1241391 C CN 1241391C CN 200410026017 CN200410026017 CN 200410026017 CN 200410026017 A CN200410026017 A CN 200410026017A CN 1241391 C CN1241391 C CN 1241391C
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Abstract
The present invention discloses a channel parallel realizing method for a bit plane coder under the JPEG 2000 column associated mode. The processing speed of the method is about 3 times as fast as that of a serial method, the control logic is simple, and the memory requirement is low. A 4*5 sliding window coder designed by the present invention can generate the context data of three channels parallelly, and realizes coding between bands and bit planes continuously and sequentially by using the method of inserting zero at an edge. As showed in experiments, the coding efficiency of the present invention is higher than that of the Jen-Shiun Chiang multi-window parallel method, the speed bottleneck problem of the EBCOT is solved, and under the condition that the frequency does not exceed 100Mh, the present invention can make the JPEG2000 realize real-time coding, and the present invention has wide application prospect in the multimedia field.
Description
Technical field
The invention belongs to the VLSI design field, relate to row association (Vertical Causal) pattern among the Joint Photographic Experts Group JPEG2000, particularly utilize the channel parallel implementation method of bit plane encoder under a kind of JPEG2000 row association mode that single sliding window controls.
Background technology
JPEG2000 is a still image compression standard of new generation, compares with JPEG, and it is supported higher compression ratio and has abundant more compression function.The big characteristics of JPEG2000 are EBCOT (the Embedded Block Coding with Optimized Truncation) algorithms that adopted D.Taubman to propose, and promptly have the embedded code block coding that ideal is blocked.This algorithm is encoded to the basis with counting of generating based on context, the integrated notion of passage scanning, for JPEG2000 constant bit rate compression control provides advantage, the compressed file size that finally obtains accurately, decoding reduction effect ideal.Yet in of the introducing of Bit-Plane Encoding part owing to the passage notion, make EBCOT in the context generative process, need bitplanes to carry out repeatedly scanning encoding, need in time to pay a high price, this shortcoming causes JPEG2000 coding whole efficiency to reduce, and is difficult to that high quality image is carried out Real Time Compression and handles.
The general frame structure of EBCOT algorithm comprises the two large divisions: Tier1 and Tier2.Tier1 part completion bit plane coding and arithmetic coding, Tier2 then are responsible for code stream is blocked and packs.Bit-Plane Encoding adopts the context generating mode based on passage: be split into three passages after each bit plane scans through three times:
1) the validity propagation ducts (passage 1, Significance Propagation Pass, Pass1)
The condition that quantization parameter enters Pass1 is: the state of validity is 0 on the present bit plane, and its 8 neighborhood the state of validity is not 0 entirely.Because the state of validity constantly refreshes, therefore can think that the cataloged procedure of this passage promptly is the communication process of coefficient validity in cataloged procedure;
2) the amplitude refinement (passage 2, Magnitude Refinement Pass, Pass2)
The state of validity is 1 point behind the last Bit-Plane Encoding, will be included into the Pass2 coding on the present bit plane;
3) remove passage (passage 3, Cleanup Pass, Pass3)
Do not enter the point of Pass1 and Pass2 in the present bit plane, will enter the Pass3 coding.
In the passage scanning process, need to bring in constant renewal in following state variable:
δ: validity before the coding.If coefficient had become before entering the present bit plane effectively (being that MSB occurs), then the δ value is 1, otherwise is 0;
δ ': coding back validity.δ '=δ before the present bit plane coding, through becoming effectively as if coefficient after the channel coding, it is 1 that δ ' is worth, otherwise keeps; Exist relatedly between δ ' and other states, need not deposit, can directly generate by combinational logic.
π: coding complement mark.If coefficient is encoded on the present bit plane, π=1 then, otherwise π=0;
ξ: amplitude refinement complement mark.If coefficient once entered the amplitude refinement, ξ=1 then, otherwise ξ=0.
The problem of Bit-Plane Encoding is that scanning times is too much, efficient is low, is difficult to be applied to the VLSI design.The key of raising speed is to improve the channel scanning method of this serial, and the whole bit plane of disposable traversal so just might reach real-time on hardware.Present existing speed-raising scheme has two kinds:
People such as Kuan-fu Chen are at document " Analysis and Architecture Design of EBCOTfor JPEG2000 " (The 2001 IEEE International Symposium on Circuits andSystems (ISCAS 2001) [C] .Sydney, Australia:IEEE Circuits and SystemsSociety Press 2001.5 (2): point out 765-768) that the distribution of three coding pass quantization parameters has lack of uniformity.Judge that by adopting the coding necessity (NBC, Need-Block-Coding) with group (GOCS, the Group-of-column Skipping) mode of jumping, can directly skip does not need the point and the group (i.e. 8 adjacent column) of encoding, thereby cuts down invalid traversal.The shortcoming of this method is serial from the whole structure cataloged procedure also clearly: each bit plane still needs sequential scanning three times.Found through experiments, even adopt NBC and GOCS, it is real-time that coding rate still can't reach.
Jen-Shiun Chiang, Yu-sen Lin etc. are at " Efficient Pass-Parallel Architecture ForEBCOT In JPEG2000 " (IEEE International Symposium on Circuits andSystems (ISCAS 2002) [C] .Arizona:IEEE Circuits and Systems Society Press, 2002 (1): propose a kind of multi-channel parallel sweeping scheme 773-776), use a plurality of sliding window encoders that three passages are carried out scanning encoding simultaneously, arithmetic encoder carries out process switching at different interchannels.This structure speed is very fast, does not also need to carry out unnecessary inquiry computing.But after adopting the multiwindow design, the control complexity increases.And the strict structure of this scheme employing in fact is accurate parallel: do not have two contextual situations of same clock cycle output, when arithmetic coding adopted three to go on foot the flowing water design, the processing speed of this structure still was apparent not enough.
Summary of the invention
At defective or deficiency that above-mentioned prior art exists, the detail bit plane coding is still having researching value and room for improvement aspect the hardware realization.Therefore the objective of the invention is to, under the channel parallel mode, propose faster, the required storage resources of a kind of speed still less, and control the channel parallel implementation method of bit plane encoder under the lower JPEG2000 row association mode of complexity.
The technical solution that realizes the foregoing invention purpose is, employing meets the bit plane encoder of JPEG2000 standard, it is characterized in that, this surface encoder works in related (Vertical Causal) pattern of row, adopt 4 * 5 single sliding windows to slide and generate neighborhood states information, state value by band (previous stripe) last point (4th pixel) before SRS, CRS and three N+1 positions of the SignRS row register holds, wherein N is the code block width, and the quantization parameter of three passages is implemented parallel encoding; Last row of each band or first row carry out the edge zero insertion to be handled, and makes sliding window cross over two bands on the bit plane simultaneously, realizes continuous programming code whereby between interband and bit plane.
Sliding window directly reads in and calculates when sliding and quantizes pairing each state value of coefficient memory, removes status register from.
The present invention is a kind of improvement to the channel parallel Bit-Plane Encoding method of people such as Jen-Shiun Chiang proposition.By related (Vertical Causal) pattern of the peculiar row of JPEG2000, adopt single sliding window to encode, the control complexity reduces greatly, and parallel efficiency is further enhanced.Experiment showed, that the present invention can carry out VLSI fully and realize that coding rate is higher than existing prioritization scheme.
The present invention shows the technical characterstic of following several respects:
1) adopts related (Vertical Causal) pattern of the peculiar row of JPEG2000
Related (Vertical Causal) pattern of row requires when carrying out the context generation, has a mind to isolate the correlation between line direction band (stripe) and the band, and last point of each row is only judged 5 neighborhoods when judging neighborhood validity, rather than 8 neighborhoods.Its advantage is the neighborhood relevance is limited within the band, and the band that is not scanned does not influence current some coding.Though adopt this pattern to reduce compression efficiency (about 2%), easier realization concurrent operation slightly.
2) single sliding window control logic
The parallel scheme that people such as Jen-Shiun Chiang adopt need use respectively corresponding 3 coding passes of two sliding windows.The present invention only need adopt a sliding window (window size 4 * 5) just can reach identical effect, has reduced the interaction logic between the multiwindow, and the control complexity reduces.
3) need not the user mode memory
The present invention adopts the instant determining method of encoding state, can save status register fully.Required storage resources has reduced 5N than existing structure
2Bits (N is the code block width).
4) the parallel encoding neighborhood combinational logic of Jian Huaing
Need in the Bit-Plane Encoding process at any time with reference to neighborhood states variable (the state of validity δ and sign condition S).Owing to adopt parallel scheme to handle 3 coefficients in the coding pass simultaneously, so the required neighborhood states variable of these 3 passages also must generate simultaneously.The present invention has designed a cover combinational logic and has generated 12 neighborhood of a point state informations simultaneously; The state of validity is divided into δ and two kinds of situations of δ ' to simplify computing, and character-coded processing procedure is also optimized to a certain extent.
1) interband continuous programming code
When adopting the sliding window computing, because the outside validity of code block is 0, therefore the marginal position of band (stripe) need carry out special processing usually.This algorithm need not to increase extra hardware logic and can realize the interband continuous programming code by solving at window end zero insertion.For width is the code block of N, is N+3 according to the actual treatment columns of each band of conventional method, and can be optimized for N+1 after adopting this programme.
Description of drawings
Fig. 1 is the neighborhood explanation under the row association mode;
Fig. 2 is 4 * 5 sliding window encoders and the row register declaration, among the figure the 0th～4 of the corresponding all the time SRS of sliding window, CRS and SignRS, finish a row coding after, sliding window moves to right and 1 is listed as, SRS, CRS and SignRS move to left 1 respectively;
Fig. 3 is each vertex neighborhood combinational logic relation in the channel parallel coding, and h represents left and right sides neighborhood available point summation, 0≤h≤2 among the figure; V represents neighborhood available point summation up and down, 0≤v≤2; D represents diagonal neighborhood available point summation, 0≤d≤4; N represents whether validity is 0 to coefficient 8 neighborhoods entirely, and "Yes" is n=0 then, otherwise n=1;
Fig. 4 is that the edge zero insertion is handled schematic diagram, and wherein black box is represented 4 * 5 sliding window, crosses over two bands simultaneously and encodes;
Fig. 5 is the EBCOT coder structure figure that adopts 4 * 5 channel parallel schemes.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
1) code block input
Need to read in advance the code block data before the Bit-Plane Encoding, it is write the quantization parameter memory so that visit at any time in cataloged procedure.Its prime is code block cutting (Code-block Division) device, behind the output start starting impulse quantization parameter is sent line by line.Each clock cycle of bit plane encoder can be finished the reception of a coefficient and be write, and carries out current coefficient maximum simultaneously and judges.Can calculate the significance bit plane number m of this code block after all quantization parameter writes and finishes.Concrete steps are as follows:
1.. make p
Max=0;
2.. receive the quantization parameter p that prime is sent, if | p|＞p
Max, p then
Max=| p|, write amplitude position and the sign bit of p to coefficient memory, if all coefficient processing of code block finish, forward to 3., otherwise change 2.;
3.. significance bit plane number
2) channel parallel scanning encoding
A) introduce the row status register
After finishing quantization parameter and writing, will carry out scanning encoding to all significance bit planes from top to bottom.The present invention adopts row association (vertical causal) pattern among the JPEG2000.Because this pattern has only been isolated middle band (current stripe) and the correlation of time being with between (next stripe), still there is related (see figure 1) between middle band and preceding band (previous stripe).Be with interior parallel encoding, must overcome this situation.The present invention is by the prestore state information of last point of every row of row status register structure.
The renewal of the state of validity only may occur in Pass1 and Pass3, and the present invention adopts two capable registers to write down the state of validity value of last point of every row among Pass1 and the Pass3 respectively; In addition symbolic coding is carried out need using preceding tape symbol when neighborhood is judged, also need to use capable register to store, we remember respectively and make SRS, CRS and SignRS.Why distinguishing SRS and CRS, is because passage scanning has sequencing in the JPEG2000 standard, the effective point that in Pass3, becomes, and the context that will not influence Pass1 and Pass2 generates.During parallel processing, preceding two passages must use SRS to disturb to avoid the available point in the passage 3, then must use CRS during passage 3 codings.Can strict the coefficient neighborhood be limited within the current band by 3 capable status registers, for first point of every row, only need read SRS, CRS and SignRS just can obtain top three neighborhood states information, thereby have avoided the redundant access of preceding band data.
If the code block width is N, SRS then, CRS and SignRS all adopt N+1 position circular shift register structure, and reason will be explained below.
B) 4 * 5 sliding window encoder design
The key of Bit-Plane Encoding is that neighborhood generates.The present invention has designed the sliding window of a size 4 * 5, and each unit bit wide is 5, deposits v, s, δ, π and the ξ value of corresponding points respectively, and the neighborhood states (structure is seen Fig. 2) of 3 passages of generation that can walk abreast is to carry out context coding.Window covers the row of 5 on the bit plane simultaneously: wherein the 2nd～4 row generate Pass1, Pass2 and all required neighborhood values of Pass3 coding respectively according to combinational logic relation table shown in Figure 3.After coding is finished, the sliding window row that move to right, SRS, CRS also carry out a step cyclic shift with the capable register of SignRS simultaneously, and last point of the 5th row is expert at and is carried out validity and sign condition renewal on the register, up to whole code block cataloged procedure end.Notice that under this structure, each bit plane only needs run-down, processing speed improves greatly.
C) state variable generates immediately
Design of the present invention need not the additivity memory, quantizes coefficient memory by visit when window slides and directly calculates pairing each state value of first row.If the quantization parameter symbol is sign, amplitude is mag, and present bit plane sequence number is p, then:
v＝mag[p]
s＝sign
δ＝(mag＞2
P+1)？1:0
π＝0
ξ＝(mag＞2
p+2)？1:0
D) the edge zero insertion is handled
In position, the edge of band (first row or last row), left and right sides neighborhood may drop on the code block outside.According to JPEG2000 agreement regulation, the state of validity of external point is zero without exception.The present invention adopts the edge zero insertion to handle, and does not need to change any neighborhood formation logic, can solve edge problem, realizes interband sliding window continuous programming code.Detailed process when window slides into last row of each band, is inserted a row null value (line shift register also needs pre-slotting 0, and is just in time corresponding with the window's position) referring to Fig. 4 more, immediately reads time first row quantization parameter of band.To width is the code block of N, window each with on the slip number of times be N+1.Adopting this scheme, do not need the buffer time of encoding between interband, bit plane, is the code block of m to big or small N * N, significance bit plane number, can realize the free of discontinuities continuous programming code, and scanning total columns is mN (N+1)/4.
3) context data output
Because the present invention adopts the channel parallel sweeping scheme, the context of three passages is exported simultaneously, and therefore the back level needs the corresponding different respectively passage of 3 arithmetic encoders with coupling context formation speed.If arithmetic coding adopts 3 steps flowing water design (handle a context and only need a clock under this design), then and do not need between the bit plane encoder to use fifo to carry out metadata cache, storage resources also can be saved.See Fig. 5.
Have any to it may be noted that under the parallel mode, arithmetic coding must be selected " probability tables initialize mode " and " channel end pattern ".This can bring slight influence (the lossless compress rate approximately reduces by 2%) to compression efficiency, but exchanges the realization of High Speed of hardware for, and cost is worth.
Claims (3)
1. the channel parallel implementation method of bit plane encoder under the JPEG2000 row association mode, employing meets the bit plane encoder of JPEG2000 standard, it is characterized in that, this encoder works in the row association mode, adopt 4 * 5 single sliding windows to slide and generate neighborhood states information, by the state value of band end point before SRS, CRS and three N+1 positions of the SignRS row register holds, wherein N is the code block width, and the quantization parameter of three passages is implemented parallel encoding; Last row of each band or first row carry out the edge zero insertion to be handled, and makes sliding window cross over two bands on the bit plane simultaneously, realizes continuous programming code whereby between interband and bit plane.
2. the channel parallel implementation method of bit plane encoder is characterized in that under the JPEG2000 row association mode as claimed in claim 1, and sliding window directly reads in and calculates when sliding and quantizes pairing each state value of coefficient memory, removes status register from.
3. the channel parallel implementation method of bit plane encoder under the JPEG2000 row association mode as claimed in claim 1, it is characterized in that, the step that described edge zero insertion is handled is, sliding window is at the edge of band, and promptly first row or last column position inserts a row null value more, when sliding window slides into last row of each band, immediately reading time the first row quantization parameter of band, is the code block of N to width, window each with on the slip number of times be N+1.
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| CN101820549B (en) * | 2010-03-19 | 2011-10-19 | 西安电子科技大学 | High-speed real-time processing arithmetic entropy coding system based on JPEG2000 |
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