WO2020215193A1 - Coder, coding system, and coding method - Google Patents

Abstract

Provided are a coder, a coding system, and a coding method. The coder comprises a Tier-1 coding unit for performing Tier-1 coding on a code block of an image block of an image to be coded to obtain a code stream of the code block. The Tier-1 coding unit comprises: a bit plane coding unit, the bit plane coding unit comprising a first channel and a second channel, and the first channel and the second channel being used for performing bit plane coding on multiple bit planes of the code block in parallel to obtain the code stream of the code block; and an arithmetic coding unit used for performing arithmetic coding on the code stream of the code block to obtain a target code stream. In the present application, by means of the first channel and the second channel, a code stream consisting of a coding result output by the first channel and a coding result output by the second channel can be obtained, so that the arithmetic coding unit can adopt arithmetic coding modes having different compression rates and coding speeds for the bit plane coding results, and thus, both the compression rate and coding speed of the code block can be taken into consideration.

Description

Encoder, encoding system and encoding method

Copyright statement

The content disclosed in this patent document contains copyrighted material. The copyright belongs to the copyright owner. The copyright owner does not object to anyone copying the patent document or the patent disclosure in the official records and archives of the Patent and Trademark Office.

Technical field

This application relates to the field of image decoding, and more specifically, to an encoder, an encoding system, and an encoding method.

Background technique

Joint Photographic Experts Group (JPEG) and JPEG 2000 are commonly used image coding standards.

JPEG 2000 uses wavelet transform and performs entropy coding based on optimized interception of embedded block coding (embedded block coding with optimized truncation, EBCOT), which has a higher compression ratio than JPEG, and supports progressive download and display.

The traditional JPEG 2000 encoder is not compatible with compression rate and encoding rate.

Summary of the invention

This application provides an encoder, an encoding system, and an encoding method, which can effectively be compatible with the compression rate and the encoding rate.

In the first aspect, an encoder is provided, including:

The Tier-1 coding unit performs tier-1 coding on the code block of the image block of the image to be coded to obtain the code stream of the code block;

Wherein, the Tier-1 coding unit includes:

A bit-plane encoding unit, the bit-plane encoding unit includes a first channel and a second channel, the first channel and the second channel are used to perform bit-plane encoding on multiple bit-planes of the code block in parallel, Obtain the code stream of the code block;

The arithmetic coding unit is used to perform arithmetic coding on the code stream of the code block to obtain the target code stream.

In the second aspect, an encoding system is provided, including:

The encoder described in the first aspect.

In the third aspect, an encoding method is provided, including:

Bit-plane encoding is performed in parallel on multiple bit-planes of the code block of the image block of the image to be coded through the first channel and the second channel to obtain the code stream of the code block;

Perform arithmetic coding on the code stream of the code block to obtain the target code stream.

Based on the above technical solutions, the encoder, the encoding system, and the encoding method of the embodiments of the present application perform bit-plane encoding on the multiple bit-planes of the code block in parallel through the first channel and the second channel, so as to obtain the A code stream composed of the encoding result output by one channel and the encoding result output by the second channel, whereby the arithmetic encoding unit can use the encoding result output by the first channel and the encoding result output by the second channel Arithmetic coding methods with different compression rates and coding speeds can also take into account the compression rate and coding speed of the code block at the same time.

Description of the drawings

Figure 1 is a coding framework diagram of JPEG 2000.

Fig. 2 is a schematic structural diagram of an encoding system provided by an embodiment of the present application.

Fig. 3 is a schematic structural diagram of the coding unit shown in Fig. 2.

Fig. 4 is a schematic structural diagram of the relationship between the bit plane and the coding channel of the present application.

Fig. 5 is a schematic diagram of the scanning sequence of SPP, MRP and CUP in the bit-plane coding process of the present application.

FIG. 6 is a schematic diagram of the neighborhood of the pixel of the bit plane of the present application.

Fig. 7 is an example of scanning windows of SPP, MRP and CUP of the present application.

Fig. 8 is another example of scanning windows of SPP, MRP and CUP of the present application.

Fig. 9 is a schematic structural diagram of a decoder provided by an embodiment of the present application.

Detailed ways

This application can be applied to the field of image coding and decoding, video coding and decoding, hardware video coding and decoding, dedicated circuit video coding and decoding, and real-time video coding and decoding.

The encoder provided in this application can be used to perform lossy compression (lossy compression) on images, and can also be used to perform lossless compression (lossless compression) on images. The lossless compression can be a visually lossless compression (visually lossless compression) or a mathematically lossless compression (mathematically lossless compression).

To facilitate understanding, first briefly introduce the coding framework of JPEG 2000.

As shown in FIG. 1, the coding framework of JPEG 2000 may include a preprocessing module 12, a transformation module 14, a quantization module 16, and an EBCOT module 18.

The preprocessing module 12 may include a component transformation (component transformation) module 122 and a direct current level shift module 124.

Each image is composed of different components. The component transformation module 122 may perform a certain transformation on the components of the image to reduce the correlation between the components. For example, the component transformation module 122 may convert each component of the image from the current color domain (for example, red, blue and green (RGB)) to another color domain.

The component transformation module 122 may support multiple color transformation modes. Therefore, the component transformation module 122 may sometimes be referred to as a multi-mode color transform (MCT) module. For example, the component transform module 122 may support irreversible color transform (ICT) or reversible color transform (RCT). It should be noted that the component transformation module 122 is optional. In the actual encoding process, it is also possible to directly perform subsequent processing without performing component transformation on the image.

The DC level shift module 124 can be used to perform a center shift (also referred to as a DC level shift) on the component values, so that the component values are symmetrically distributed with respect to 0, so as to facilitate subsequent transformation operations of the transformation module 14.

The transform module 14 uses wavelet transform to transform each tile in the image to obtain sub-band wavelet coefficients of different resolution levels. After n-level wavelet transform, there are n+1 resolutions. Level, each resolution level has 3 subbands (except for the lowest resolution, only 1 subband).

It should be noted that when the resolution r is not the lowest resolution, the four subbands HH, HL, LH, and LL are actually included, but because LL is allocated to the next resolution, only HH, HL, and LH are processed. Three sub-bands.

It should be understood that the embodiment of the present application does not specifically limit the size of the image block, for example, it may be 512×512 (unit is pixel). For another example, the entire image can be regarded as an image block.

The quantization module 16 may be used to quantize the wavelet coefficients of the subbands to obtain the quantized wavelet coefficients of the subbands.

The EBCOT module 18 is the entropy coding module of JEPG 2000, and belongs to the core module of JEPG 2000.

The EBCOT module 18 may include a tier-1 encoding module 182, a tier-2 encoding module 184, and a rate control module 186. The tier-1 encoding module 182 can be used to perform tier-1 encoding on a code block (the subband can be further divided into multiple independent code blocks). Tier-1 coding can include bit-plane coding and arithmetic coding. The tier-2 encoding module 184 is mainly responsible for the organization of the code stream. For example, the code stream of the code block can be truncated according to the target code rate provided by the code rate control module 186.

The encoder in this application will be described below in conjunction with FIG. 2.

As shown in FIG. 2, the encoder 7 may include a first interface circuit 71, a transform circuit 72, a quantization circuit 73, a first encoding circuit 74, a rate control circuit 75, a second encoding circuit 76 and a code stream writing circuit 77.

The encoder 7 may be a hardware encoder supporting the JPEG 2000 standard.

The first interface circuit 71 may be used to obtain an image to be coded, and after obtaining the image to be coded, divide the image to be coded into multiple image blocks. Of course, the first interface circuit 71 can also be used to directly obtain the divided image blocks. The image to be encoded may be an image subjected to component transformation. The format of the image to be encoded may be any image format with 4 or 3 components. Among them, the image format with 4 components includes but is not limited to Bayer pattern RAW format or YUVGb format or YDgCoCg format converted from Bayer pattern RAW format. Image formats with 3 components include but are not limited to RGB format and YUV format.

The first interface circuit 71 can be used to receive the image to be encoded collected by the sensor, can also be used to read the image to be encoded or the image block of the image to be encoded from the memory, and can also use image signal processing (ISP) The system acquires an image that has undergone component transformation. The ISP includes but is not limited to a digital signal processor (DSP) and a graphics processing unit (GPU).

Taking the image block of the image to be encoded by the first interface circuit 71 from the memory as an example, the image to be encoded can be stored in the memory in row order or column order. At this time, the first interface circuit 71 can be based on the position of the image to be encoded in the memory. , Calculate the storage location of each image block, and then read the corresponding image block according to the jump addressing mode. Of course, the image to be encoded can also be stored in the memory in units of image blocks, and the first interface circuit 71 can read the image blocks according to the storage order of the image blocks. Specifically, the first interface circuit 71 can use a specific addressing mode to read the image blocks of the image to be coded stored in the memory without segmenting the image to be coded. The first interface circuit 71 may also directly read image blocks from the memory in a direct memory access (DMA) manner, so as to improve the access efficiency and speed.

In some embodiments, the first interface circuit 71 may include a calculation circuit.

The calculation circuit can be used to calculate the statistical information of the image to be encoded. Of course, the calculation circuit can also be provided separately from the first interface circuit 71 or the encoder 7. For example, in other alternative embodiments, the calculation circuit may also be set in an image signal processing (image signal processing, ISP) system.

The statistical information of the image to be encoded may be information that can be used to control the rate of the tile in the image to be encoded. Therefore, in some embodiments, the statistical information of the image to be encoded may also be referred to as the image to be encoded. Block rate control information. The statistical information of the image to be encoded may include one or more of the following information of the image blocks in the image to be encoded: complexity, activity, and texture.

There can be multiple calculation methods for the statistical information of the image to be encoded.

Taking the statistical information of the image to be encoded as the complexity of the image block in the image to be encoded as an example, the calculation circuit may define or calculate the complexity of the image block based on the amplitude of the high frequency components of the pixels in the image block. For example, the complexity of the image block may be the cumulative sum of the high frequency information of the location of each pixel in the image block area. When the texture of the image block is more complex, the cumulative sum of the amplitudes of the corresponding high-frequency components will be correspondingly larger, and it can be considered that the complexity of the image block is higher. According to the image coding theory, the coded code stream (or the number of bits consumed for coding) corresponding to the image block area with higher complexity will be correspondingly larger. Specifically, the calculation circuit may obtain high frequency components through filtering operations based on the pixel values of the pixels in the image block area, and then calculate the complexity of the image block. In other alternative embodiments, the calculation circuit may also define or calculate the complexity of the image block based on the mean-square error (MSE) of the pixel value of the image block. The larger the MSE of the pixel value of the image block, the larger the It is considered that the complexity of the image block is higher. It should be understood that the complexity of the image block may also be defined in other ways, or a combination of the above definitions, which is not limited in the embodiment of the present application. The first interface circuit 71 can also be used to read the pre-generated statistical information of the image to be encoded from an external memory. This application does not impose specific restrictions on this.

The first interface circuit 71 may transmit the statistical information of the image to be encoded as rate control information to the rate control circuit 75 for the rate control circuit 75 to perform rate control on the encoding process.

The transform circuit 72 can be used to perform the operation performed by the transform module 14 above, that is, perform wavelet transform on the image block. After the image block undergoes wavelet transformation, many subbands can be obtained. After wavelet transformation, the wavelet coefficients of the image block can be obtained, and the wavelet coefficients of the image block can refer to the wavelet coefficients of these sub-bands.

The quantization circuit 73 may be used to quantize the wavelet coefficients to obtain quantized wavelet coefficients or quantized wavelet coefficients of subbands.

The first encoding circuit 74 may include one or more EBCOT encoding modules 742. The EBCOT encoding module 742 may be used to perform tier-1 encoding on the code blocks of the image block (the subband can be further divided into multiple independent code blocks) to obtain the code The code stream of the block. The code streams of all code blocks of the image block constitute the code stream of the image block.

Referring to the previous description, it can be seen that the transform circuit 72 receives the image block, and the transform circuit 72 transforms and the quantization circuit 73 quantizes the subbands with wavelet coefficients. A subband can be divided into independently coded one or Multiple code blocks, that is, code blocks of image blocks, may refer to code blocks of subbands of the image block.

The EBCOT encoding module 742 may be used to perform operations performed by the tier-1 encoding module 182 in FIG. 1, such as bit-plane encoding and arithmetic encoding on the code block. Optionally, before the first encoding circuit 74 encodes the code block, the code block may also be preprocessed, for example, the sign bit and the absolute value of the wavelet coefficient are separated. In addition, in some embodiments, after the first encoding circuit 74 encodes the code block into a code stream, it can also perform post-processing on the code block. For example, the code stream can be spliced together for use by the second encoding circuit 76.

The code rate control circuit 75 may be used to determine the target code rate (target size) of the image block in the image to be encoded according to the statistical information of the image to be encoded.

Taking the statistical information of the image to be encoded as the complexity of the image block in the image to be encoded as an example, the rate control circuit 75 may assign weights to each image block according to the complexity of each image block. The higher the complexity of the image block, the greater the weight. The code rate control circuit 75 may calculate the target code rate of each image block according to the weight of each image block and current network conditions (such as network bandwidth), so that the larger the weight of the image block, the higher the target code rate. Optionally, the statistical information of the image to be encoded output by the calculation circuit may include the weight of each image block, and the code rate control circuit 75 may directly use the weight of the image block to calculate the target code rate.

The second encoding circuit 76 can be used to implement the function of the tier-2 encoding module 184 mentioned above. For example, the second encoding circuit 76 may be used to perform tier-2 encoding on the bit stream of the image block according to the target bit rate, so as to cut the bit stream of the image block. Specifically, after the second encoding circuit 76 receives the code stream of each code block sent by the first encoding circuit 74, it can combine the code streams of each code block according to the output code rate requirements (for example, the output target code rate). , Carry out optimization truncation sorting, packing and other processing on the code stream of all code blocks to obtain the JPEG2000 code stream.

The second encoding circuit 76 may include a rate-distortion calculation circuit 762 (or slopemaker) and a truncation circuit 764 (or truncator).

The rate-distortion calculation circuit 762 can be used to calculate the rate-distortion slope of the code stream output by the first encoding circuit 74. For example, the rate-distortion calculation circuit 762 may calculate the rate-distortion slope (distortion) based on the rate and distortion of each code stream (that is, the code stream (pass) of each code block) output by the first encoding circuit 74. slope). The rate-distortion slope can be used to evaluate the contribution of each segment of the current code block to the entire image block. The rate-distortion slope can be used for subsequent code stream organization, such as code stream layering and truncation. Specifically, in the encoding process, the current code block will be divided into several bit planes, and each bit plane will generate 3 bit streams after encoding (3-pass encoding, except for the highest bit plane, only 1 bit stream will be generated. Outside), where each segment of the code stream corresponds to a slope value.

That is, the rate-distortion slope corresponding to the current code block may include the slope value corresponding to each segment of the code stream generated after the current code block is bit-plane encoded.

The truncation circuit 764 can be used to process the bit stream of the image block according to the target bit rate and the rate-distortion slope. For example, the truncation circuit 764 can be used to cut the bit stream of the image block according to the target bit rate and the rate-distortion slope. Further, the truncation circuit 764 can also be used to reorganize the code stream, layer the code stream, and so on. In addition, in some embodiments, the truncation circuit 764 may also be used to generate header information of the code stream, and transmit the header information together with the code stream to the subsequent code stream write circuit 77.

The code stream write circuit 77 can be used to receive the organized code stream output by the truncation circuit 764 and write the code stream to an external memory. For example, it can be written to an external memory via the bus. The bus may be, for example, an advanced extensive interface (AXI) bus. The code stream writing circuit 77 may also add information such as a tile header to the code stream.

In some embodiments, the rate control circuit 75 may also be used to generate the state information of the rate control buffer (or buffer size) according to the statistical information of the image block. The first encoding circuit 74 can also be used to control the tier-1 encoding according to the state information of the code rate control buffer. The status information of the buffer can be used by the first encoding circuit 74 to pre-truncate the code stream. For example, the first encoding circuit 74 may delete code streams that exceed a predetermined size according to the status information of the buffer, or delete code streams that do not meet the requirements. Therefore, the status information of the buffer can also be called pre-truncation information. Further, in some embodiments, the rate control circuit 75 may also receive feedback of the size of the code stream actually encoded by the first encoding circuit 74, and update the pre-truncation information of the image block corresponding to the wavelet subband.

In some embodiments, the encoder 7 may also include an interface circuit (not shown in the figure) for software configuration, through which the information in the register inside the encoder 7 can be configured or changed, thereby controlling the encoder 7 Encoding method.

The embodiment of the present application calculates the statistical information of the image blocks in the image to be encoded, and cuts the code stream of the image blocks according to the statistical information, thereby performing relatively independent bit rate control on each image block without taking the code block of each image block as The unit is optimized to avoid generating a large amount of intermediate data. Therefore, the embodiment of the present application can reduce the requirement of the encoder on the system bandwidth. The entire encoding process of the image to be encoded can even be carried out completely on the chip.

In some embodiments, a buffer (on-chip buffer) may be set inside the conversion circuit 72 or at the output terminal, for buffering the intermediate results output by the conversion circuit 72.

In some embodiments, a buffer (on-chip buffer) may be set inside or at the output end of the truncation circuit 764 for buffering the intermediate results output by the truncation circuit 764.

In some embodiments, rate matching can be performed on adjacent two-stage circuits in the encoder 7 to improve the encoding efficiency of the encoder 7. For example, circuits with slower processing speeds in adjacent two-stage circuits can be set to a multi-channel parallel structure; then, a certain mechanism can be used to control the data transmission between the two, so that the two-stage circuits are fully streamlined.

As an example, the rates of the quantization circuit 73 and the first encoding circuit 74 may be matched. Specifically, as shown in FIG. 2, when the first encoding circuit 74 includes multiple EBCOT encoding modules 742, the multiple EBCOT encoding modules 742 can be used to perform tier-1 encoding on each code block output by the quantization circuit 73 in parallel, that is, The first encoding circuit 74 may adopt a multi-path parallel structure to perform tier-1 encoding. Since the code blocks output by the quantization circuit 73 to the first encoding circuit 74 may be code streams corresponding to multiple frequency components (for example, code blocks corresponding to LL, HL, LH, and HH), the quantization circuit 73 and multiple EBCOT encoding modules Group arbitration or free arbitration can be adopted between 742 to determine the EBCOT encoding module 742 corresponding to the intermediate result output by the quantization circuit 73. Among them, group arbitration refers to always assigning the code block corresponding to a certain frequency component output by the quantization circuit 73 to a fixed group of coding units (each group of coding units can be composed of several coding units), while free arbitration refers to quantization Each code block output by the circuit 73 may be received by one of the multiple parallel encoding units. The advantage of the packet arbitration method is that the circuit connection is relatively simple in hardware implementation, while the free arbitration method can improve the utilization efficiency of the coding unit in some cases.

As another example, the rates of the first encoding circuit 74 and the rate-distortion slope calculation circuit 762 may be matched. For example, the rate-distortion calculation circuit 762 may include a plurality of rate-distortion slope calculation units. The multiple rate-distortion slope calculation units can be used to calculate the rate-distortion slope of the code stream output by the first encoding circuit 74 in parallel. The first encoding circuit 74 and the rate-distortion calculation circuit 762 may also adopt a group arbitration or free arbitration method to determine the rate-distortion slope calculation unit corresponding to the intermediate result output by the first encoding circuit 74. Taking packet arbitration as an example, one rate-distortion slope calculation unit can correspond to a group of coding units in the first coding circuit 74. A rate-distortion slope calculation unit corresponding to a group of encoding units can make the design of the entire circuit easier.

FIG. 3 is a schematic structural diagram of the EBCOT encoding module 742 shown in FIG. 2.

As shown in FIG. 3, the EBCOT encoding module 742 may include a preprocessing unit 64, a tier-1 encoding unit 6, and a post-processing unit 65.

Before the tier-1 encoding unit 6 encodes the code block, the preprocessing unit 64 may be used to preprocess the code block, for example, to separate the sign bit and the absolute value of the wavelet coefficient. After the tier-1 encoding unit 6 encodes the code block into a code stream, the post-processing unit 65 can be used to perform post-processing on the code stream of the code block. For example, the code streams can be spliced together for use by the second encoding circuit 76.

The preprocessing module 64 may include a first memory 641 and a second memory 642, and the tier-1 encoding unit 6 can read the code blocks preprocessed by the preprocessing unit 64 through the first memory 641 and the second memory 642.

The post-processing module 65 may include an access instruction generation unit 651, a third memory 652, and a fourth memory 653. The post-processing module 65 may be used to receive the code stream output by the tier-1 encoding unit 6, and generate a memory based on the received code stream. The instruction is fetched, and then the code stream output by the tier-1 encoding unit 6 is stored based on the access instruction. The access instruction generating unit 651 is specifically configured to receive the code streams output by the first arithmetic encoder 621 and the code stream organizing unit 63, and store these code streams in the third memory 652 and/or the fourth memory 653. Corresponding address.

The tier-1 coding unit 6 may include a bit-plane coding unit 61, an arithmetic coding unit 62, and a code stream organizing unit 63, which are used for specific compression of data.

Wherein, the bit-plane coding unit 61 may perform multi-channel bit-plane coding on each code block to generate context information and a decision result. The decision result is used to generate a code stream, and the context information is used for the arithmetic coding unit 62 to establish a probability model. Furthermore, arithmetic coding is performed on the code stream output by the bit-plane coding unit 61.

The preprocessing module 64 decomposes the wavelet coefficients of the code block into bit planes (also called bit planes), reorganizes the decomposed bit planes and sends them to the bit plane encoding unit 61, and the bit plane encoding unit 61 receives the preprocessing module 64 transmitted organized bit planes are bit plane encoded. Stored on the bit plane is the bit value of the binary corresponding bit of the coefficient. The bit-plane encoding unit 61 scans and encodes the bits on each bit-plane, and then sends the generated context information and code stream to the arithmetic encoding unit 62 or the code stream organizing unit 63, so that the arithmetic encoding unit 62 performs arithmetic encoding and coding. The stream organization unit 63 performs code stream organization.

Specifically, the bit-plane encoding unit 61 scans and encodes the bits on part of the bit-plane (the upper-level plane and the 3 planes below the upper-level plane), and then sends the generated context information and code stream to the distribution unit 613. The first arithmetic encoder 621 performs arithmetic encoding by the first arithmetic encoder 621, and the first arithmetic encoder 621 sends the encoded bit stream to the post-processing module 65. In addition, after the bit-plane encoding unit 61 scans and encodes the bits on the remaining part of the bit-plane, the distribution unit 613 sends the generated context information and code stream to the second arithmetic encoder 622, and the second arithmetic encoder 622 performs arithmetic coding, and the second arithmetic encoder 622 sends the encoded bitstream to the bitstream organizing unit 63, which is reorganized by the bitstream organizing unit 63 and then sent to the post-processing module 65. The post-processing module 65 stores the code streams output by the first arithmetic encoder 621 and the code stream organizing unit 63 to the corresponding addresses of the third memory 652 and/or the fourth memory 653.

The bit-plane coding unit 61 can perform multi-channel bit-plane coding for each code block, and the multi-channel bit-plane coding can include significance propagation pass (significance propagation pass, SPP or SP) coding, amplitude refinement pass (magnitude refinement pass, MRP) Or MR) encoding and clean up pass (CUP or SP) encoding.

Among them, the saliency propagation channel is the first encoding channel of each bit plane (except for the highest bit plane, in the highest bit plane, there is only one encoding channel, that is, the clear encoding channel), which is used to encode currently not significant coefficients, but The 8 neighborhoods have been marked as significant coefficients. For example, for the data X to be encoded that is not marked as important, as long as at least one of the surrounding 8-bit data has been marked as a significant coefficient, the data X to be encoded will be encoded in this channel. Each coefficient in the bit plane can correspond to a binary state variable s[j] used to represent a "significant state", where j represents the coefficient scan coordinate. The saliency state is initialized to 0, and the s state value will be updated in each bit plane. When a coefficient becomes significant in the current bit plane, the corresponding s[j] = 1 (once the coefficient becomes significant, the next corresponding The significant state s[j]=1 will not change), and it will be conducted from the highest bit plane to the lowest bit plane that needs to be coded.

The amplitude refinement channel is the second encoding channel of each bit plane (except for the highest bit plane, in the highest bit plane, there is only one encoding channel, that is, the clear encoding channel), which is used for encoding when the previous bit plane has been marked Is a significant coefficient.

The clear channel is the third encoding channel of each bit plane (except for the highest bit plane, in the highest bit plane, there is only one encoding channel, that is, the clear encoding channel), which is used to encode the remaining coefficients. To clear the coding channel, run-length coding and zero coding can be added. Specifically, the four bits in a row can be judged simultaneously in this channel. For example, when four bits have no adjacent data that has been marked as significant, run-length coding is used for them, otherwise zero coding is used for each bit.

In the three encoding channels described above, the bit-plane encoding unit 61 may use different encoding methods to perform bit-plane encoding on the bit-plane in different encoding channels. Among them, the coding methods used in the coding channel include but are not limited to: Significance Coding (ZC), Symbol Coding (SC), Magnitude Refinement Coding (MRC) and run length coding ( Run Length Encoding, RLC).

For example, in the saliency propagation channel, ZC encoding and SC encoding can be performed on the bits on the bit plane; in the amplitude refinement channel, the bits on the bit plane can be MRC encoded; in the clear channel, the bit plane The above bits can be ZC coded, SC coded and RLC coded. After the bits on the bit plane are coded by the above-mentioned multi-channel bit plane, the arithmetic coding unit 62 performs arithmetic coding on its output.

After the bit-plane encoding unit 61 performs bit-plane encoding on the bit-plane, it can obtain three sets of binary sequences for each bit-plane, that is, each channel corresponds to a set of binary sequences.

Please continue to refer to FIG. 3, the bit-plane encoding unit 61 may include a first channel 611 and a second channel 612. The arithmetic encoding unit 62 may include a first arithmetic encoder 621 and a second arithmetic encoder 622. The first arithmetic encoder 621 and the second arithmetic encoder 622 may be the same type of arithmetic encoder or different types of arithmetic encoders. The first channel 611 and the second channel 612 may correspond to the first arithmetic encoder 621 and the second arithmetic encoder 622, respectively. The arithmetic coding unit 62 may also include only one arithmetic encoder or other number of arithmetic encoders, which is not specifically limited in this application.

Wherein, the first arithmetic encoder 621 and the second arithmetic encoder 622 may be multiple quantization (MQ) arithmetic encoders. MQ arithmetic encoders include, but are not limited to, context-based adaptive arithmetic coding and traditional arithmetic encoders.

When the arithmetic encoder performs encoding, the source symbol sequence enters the encoder continuously, and the continuous output is obtained through the operation of the encoder. Arithmetic coding is to map a source symbol sequence into a code sequence (also called a codeword).

The working principle of the traditional arithmetic encoder is described below.

The traditional arithmetic encoder maps a source information sequence to a sub-interval in the [0, 1) interval. This mapping is a one-to-one correspondence to ensure unique decoding, and then take a point in this sub-interval The value represented is used as a codeword.

For example, suppose that the source symbols are {A, B, C, D}, and the probabilities of these symbols are {0.1, 0.4, 0.2, 0.3} respectively. According to these probabilities, the interval [0, 1] can be divided into 4 sub Interval: [0, 0.1) for symbol A, [0.1, 0.5) for symbol B, [0.5, 0.7) for symbol C, and [0.7, 1] for symbol D. If the input of the binary message sequence is: CADACDB. When encoding, the first input symbol is C, and the encoding range it belongs to is [0.5, 0.7]. Since the coding range of the second symbol A in the message is [0, 0.1], its interval takes the first tenth of [0.5, 0.7] as the new interval [0.5, 0.52]. By analogy, the new interval is [0.514, 0.52] when encoding the third symbol D, and the new interval is [0.514, 0.5146] when encoding the fourth symbol A, and so on. The encoded output of the message can be any number in the last interval.

The arithmetic coding process of the traditional arithmetic encoder is based on the known probability of each symbol. Only when the probability of each symbol is known can the probability interval be divided according to it.

The working principle of the adaptive binary arithmetic encoder is described below.

Adaptive arithmetic coding can complete two processes in one scan, namely the probability model establishment process and the scan coding process. Adaptive arithmetic coding does not know the statistical probability of each symbol before scanning the symbol sequence. At this time, it is assumed that the probability of each symbol is equal, and the interval [0, 1] is evenly allocated. Then continuously adjust the probability of each symbol in the process of scanning the symbol sequence.

For example, suppose that what is to be encoded is a symbol sequence consisting of five symbols from a four-symbol source {A, B, C, D}: ABBCD. Before encoding starts, the interval [0,1] is divided into four sub-intervals, corresponding to the four symbols A, B, C, and D. Scan the symbol sequence, the first symbol is A, the corresponding interval is [0,0.25], and then change the statistical probability of each symbol, the probability of symbol A is 2/5, the probability of symbol B is 1/5, and the probability of symbol C The probability of symbol D is 1/5, and the interval [0,0.25] is divided into five equal parts, A occupies two parts, and the rest occupies one part each. Next, encode the second symbol B, the corresponding interval is [0.1,0.15], and then repeat the previous probability adjustment and interval division process.

Adaptive arithmetic coding first needs to know the probability of each symbol sent by the source, and then scan the symbol sequence, divide the corresponding interval in turn, and finally obtain the codeword corresponding to the symbol sequence.

From the input of the arithmetic encoder, the input of the arithmetic encoder may include the to-be-encoded bit D and the context vector (CX) generated by the bit-plane encoding unit 61. CX is a probability statistical model summarized by the bit-plane coding unit 61 based on neighborhood correlation, and there are 19 types in total. That is, for different CX, the symbol probability is not the same. In this embodiment, both the first arithmetic encoder 621 and the second arithmetic encoder 621 can be adaptive arithmetic encoders, that is, both the first arithmetic encoder 621 and the second arithmetic encoder 621 can use CX to determine the symbol probability.

Continuing to refer to FIG. 3, the first channel 611 and the second channel 612 may each include SPP, MRP, and CUP, and SPP, MRP, and CUP all correspond to at least one encoder.

Using the characteristics of the selective mode algorithm specified by the standard protocol, the probability of the first 4-layer bit plane and the subsequent bit plane is interrupted. Therefore, consider extracting the saliency state of the 4-level bit-plane in advance, so that the subsequent bit-plane can start scanning and encoding. In this application, the first 4 bit planes are set to be encoded on the first channel 611, and the subsequent bit planes are set to be encoded on the second channel 612. That is, the bit plane encoding unit 61 includes the first channel 611 and the second channel 612, and the first channel 611 and the second channel 612 divide the multiple bit planes of the code block into two groups of bit planes. And perform bit-plane coding on the two sets of bit-planes in parallel to obtain the code stream of the code block.

In addition, since the bit depth of the encoded image is large (such as 12bit/pixel or 14bit/pixel or 16bit/pixel), the subsequent bit planes of the code block will be many (far more than 4, that is, the first channel 611 processing The number of bit planes). Based on this consideration, the present application can set the computing power of the second channel 312 to the three scan channels of SPP, MRP, and CUP in parallel. Optionally, the three scan channels scan for the same bit plane in parallel, and the first channel 611 It can only be SPP and MRP two scanning channels in parallel or CUP single scanning channel. For example, corresponding to processing a bit plane, the ratio of the processing rate of the first channel 611 to the processing rate of the second channel 612 is 1:2 (except that the highest bit plane only performs CUP scanning), thus, the two channels can be balanced. Processing rate and reducing the parallelism of the first channel 611 also help to reduce the hardware resources and peak power consumption of the implementation.

Specifically, when the first channel 611 processes the first 4 bit planes of the code block, the first time is configured to scan the highest bit plane using CUP, and the second time is configured to scan the second bit plane using SPP+MRP ( Among them, due to the update and transfer of the significant information s, SPP and MRP need to be staggered by several clock cycles, such as 2 clock cycles), the third time is configured to scan the second bit plane with CUP, and the fourth time is configured to Use SPP+MRP to scan the third bit plane, the fifth time is configured to use CUP to scan the third bit plane, and so on.

It should be understood that the "one moment" mentioned above can refer to the time for a scan channel to complete the scanning process of a bit plane. Taking the bit plane scan rate of 4bit/cycle as an example, taking the bit plane size of 32x32bit as an example, one moment is 256 cycle (actually It is also necessary to consider data scheduling and several cycles of pipeline).

The second channel 612 is configured to process subsequent bit planes, where the first time is configured to scan the fifth bit plane using SPP+MRP+CUP (wherein due to the update and transfer of the significant information s, SPP and MRP +CUP needs to be staggered by several clock cycles, such as 2 clock cycles), the second time is configured to scan the 6th bit plane with SPP+MRP+CUP, and the third time is configured to scan with SPP+MRP+CUP The seventh bit plane, and so on until the lowest bit plane that needs to be scanned and coded.

In the embodiment of the present application, the first channel 611 may be configured as SPP, MRP, or CUP. That is, the first channel 611 may also be called an x-pass (pass), where x represents SPP, MRP, or CUP. The first channel 611 may include or be configured with 1 RLC encoder, 4 MRC encoders, 4 ZC encoders, and 4 SC encoders. As a result, not only can bit-plane coding be performed on the bit-plane passing through the first channel 611, but also the hardware structure can be effectively simplified, thereby reducing the cost.

In other words, the first channel 611 may include SPP, MRP, and CUP. At this time, SPP and CUP are configured with 4 ZC encoders and 4 SC encoders in common, MRP is configured with 4 MRC encoders, and CUP is also configured with an RLC encoder. In this embodiment, SPP and CUP share 4 ZC encoders and 4 SC encoders, which can simplify the hardware structure of the EBCOT encoding module 742, and further, can ensure the utilization of each encoder in the EBCOT encoding module 742.

The second channel 612 can also be called lazy pass, which can include SPP, MRP, and CUP, where SPP can include or be configured with 4 ZC encoders and 4 SC encoders, and MRP can include or be configured with 4 MRC encoders. CUP can include or be configured with 1 RLC encoder, 4 ZC encoders, and 4 SC encoders.

When the EBCOT encoding module 742 encodes the bit plane of the code block through the first channel 611 and the second channel 612, the first channel 611 can simultaneously perform SPP, MRP scan encoding, or bit alignment on a bit plane The plane performs CUP scan coding, and the second channel 612 can simultaneously perform SPP, MRP, and CUP scan coding on a bit plane.

That is, the code block bit plane is processed in parallel through the first channel 611 and the second channel 612, which can effectively improve the coding efficiency.

Of course, alternatively, in other embodiments, the first channel 611 and the second channel 612 may also include or be configured with other numbers of ZC encoders, SC encoders, and MRC encoders, which are not specifically limited in this application. .

In summary, in the embodiment of the present application, the bit plane carry plane of the code block can be coded in parallel through the first channel 611 and the second channel 612, which can effectively improve the coding efficiency. In addition, separately configuring the encoder in the first channel 611 and the encoder in the second channel 612 can simplify the hardware structure of the EBCOT encoding module 742, and further, can ensure the performance of each encoder in the EBCOT encoding module 742. Utilization rate.

Continuing to refer to FIG. 3, the bit-plane encoding unit 61 may further include a distributing unit 613.

The distributing unit 613 may be used to distribute the output result of the encoding channel to the corresponding arithmetic encoder and other unit modules. For example, the distribution unit 613 may be used to distribute the context information and code stream of the first channel 611 to the first arithmetic encoder 621, and distribute the context information and code stream of the second channel 612 to the second arithmetic encoder 622, and /Or directly distribute the output context information and code stream of the second channel 612 to the code stream organizing unit 63.

The code stream organizing unit 63 may be used to organize the code stream output by the arithmetic coding unit 62, and output the organized code stream to the storage instruction generating unit 651, so that the storage instruction generating unit 651 generates a storage instruction based on the storage instruction The code stream output by the code stream organizing unit 63 is stored in the third memory 652 and the fourth memory 653.

In this application, the highest bit plane and the k planes below the highest bit plane can be bit-plane encoded through the first channel 611, and the remaining bit planes can be bit-plane encoded through the second channel 622. Where k can be any positive integer less than n, and n is the total number of bit planes corresponding to the code block.

The highest bit plane may be the first non-zero bit plane composed of all coefficients in the code block. For example, according to the select encoding mode specified by the standard, the probability of the first 4 bit planes used for arithmetic coding will be transferred to the following bit planes, and the probability of the latter bit planes used for arithmetic coding will not be transferred. This application can Use this feature to deploy a set of hardware for the first 4 bit planes and subsequent bit planes to process the bit planes of the code block in parallel to increase the coding rate. That is, the above k is equal to 3. Of course, this application is not limited to this. In other embodiments, the k may also be other positive integers.

Fig. 4 is a schematic structural diagram of the relationship between the bit plane and the coding channel of the present application.

As shown in FIG. 4, the n-4th bit plane to the n-1th bit plane are subjected to bit plane coding through the first channel 611, and the n-5th bit plane to the 0th bit plane are performed through the second channel 612. Bit plane coding. Since the first channel 611 and the second channel 612 respectively correspond to different encoders in the arithmetic coding unit 62, different arithmetic coding can be performed on different bit planes.

Specifically, the probability of the first arithmetic encoder 621 corresponding to the first channel 611 is transmitted bit plane by channel (pass), and its coding efficiency is good; the probability of the second arithmetic encoder 622 corresponding to the second channel 612 is Each bit plane and each pass are independent of each other, that is, by deploying multiple parallel bit plane encoders + arithmetic encoders to greatly improve the encoding speed, the encoding efficiency is poor (because the probability is not transmitted, the second arithmetic encoder The compression rate of the code stream of 622 is lower than that of the first arithmetic encoder 621).

In the embodiments of the present application, the probability of important (for example, the first 4) bit-planes for arithmetic coding is transmitted bit-plane and channel-by-channel, and the unimportant bit-planes (for example, the latter bit-plane) are not transmitted for arithmetic coding. The probability of arithmetic coding can take into account both coding speed and coding efficiency.

It should be noted that the above-mentioned number is only an example and should not be construed as a limitation of the application. In other words, the first channel 611 can be used to encode a preset number of bit-planes, and the second channel 612 can be used to encode planes other than the preset number of bit-planes. The probability of arithmetic coding is sent and passed, and the probability of arithmetic coding between other bit planes is not passed.

Please continue to refer to FIG. 4, the arithmetic encoding unit 62 may include a first arithmetic encoder 621 and a second arithmetic encoder 622. Wherein, the first arithmetic encoder 621 may be configured to transmit the probability of arithmetic coding bit-plane-by-channel (for example, in the order of SPP, MRP, and CUP). The coding efficiency is high, but the coding speed is too high. slow. The second encoder 622 can be configured such that the probability for arithmetic coding is independent of each bit plane and each channel (for example, SPP, MRP, and CUP), so that multiple parallel channels can be deployed. The bit-plane encoder+arithmetic encoder improves its encoding speed, but its encoding efficiency is poor (because the probability is not transmitted, the compression rate of the code stream is not as large as that of the first arithmetic encoder 612).

In other words, the first arithmetic encoder 621 is configured to transfer probabilities for arithmetic coding between the multiple bit planes encoded by the first channel 611, and transfer the probabilities between channels in the first channel 611. The probability used for arithmetic coding; the second arithmetic encoder 622 is configured such that the probabilities used for arithmetic coding among the multiple bit planes encoded by the second channel 612 are independent of each other, and the The probabilities used for arithmetic coding between channels are independent of each other. For example, the first arithmetic encoder 621 is configured to use the first 4 bit-planes of the first channel 611 to perform bit-plane coding for probability transfer of arithmetic coding; the second arithmetic encoder 622 is configured to be used by the The second channel 612 performs bit-plane coding with a probability that the subsequent bit-plane is used for arithmetic coding is not transmitted.

In the embodiment of the present application, by combining the first arithmetic encoder 611 and the second arithmetic encoder 612, a parallel encoder structure (that is, the arithmetic encoder 62) is formed, so as to take into account both encoding speed and encoding efficiency.

In some embodiments, the tier-1 encoding unit 6 may also be provided with one or more buffers (on-chip buffers) for storing the encoding results output by each unit module.

For example, the first channel 611 and the second channel 612 are respectively provided with buffers (on-chip buffers) for storing code streams encoded by the first channel 611 and the second channel 612.

Please continue to refer to FIG. 4, the distribution unit 613 may also be provided with an xP first input first output (FIFO) memory corresponding to the first channel 611 inside or at the output end, and the xPFIFO memory may be the SPP code in the first channel 611 The buffer corresponding to the SPP encoder may also be the buffer corresponding to the CUP encoder in the first channel 611 for buffering the encoding results of the SPP encoder and the CUP encoder, that is, the context and decision information output by the SPP encoder and the CUP encoder. As mentioned above, since the first channel 611 is used as SPP+MRP or CUP at the same time, the SPP encoder and the CUP encoder can share a buffer, which not only can effectively simplify the structure of the tier-1 encoding unit 6, but also improve The utilization of the cache is improved.

For another example, the distribution unit 613 may also be provided with an MR random access memory (RAM) corresponding to the MRP encoder in the first channel 611 inside or at the output terminal, for buffering the encoding result of the MRP encoder.

It should be noted that setting the corresponding MR RAM for the MRP encoder can effectively control the volume of the distribution unit 613 and avoid the distribution unit 613 from being too large. Of course, the embodiment of the present application is not limited to this. In other alternative embodiments, a corresponding FIFO may also be set for the MRP encoder, so as to read and write the encoding result of the MRP encoder at the same time. Specifically, the type of cache can be determined according to actual needs.

That is, the FIFO mentioned above or below can be replaced with RAM, or the RAM mentioned above or below can also be replaced with FIFO, which is not specifically limited in this application.

For another example, an MP RAM corresponding to the MRP encoder in the second channel 612 may also be provided in the distribution unit 613 or at the output end, for buffering the encoding result of the MRP encoder. Further, the MP RAM can also be used to buffer the encoding result of the SPP encoder in the second channel 612.

For another example, the distribution unit 613 may also be provided with a CP FIFO corresponding to the CUP encoder in the second channel 612 inside or at the output end, for buffering the encoding result of the CUP encoder.

4, the distribution unit 613 may also include an original encoder 6131, which is connected to the SPP encoder in the second channel 612, and is used to receive the code stream output by the SPP encoder in the second channel 612, and perform the The code stream output by the SPP encoder in 612 is raw coded and output to the code stream organization unit 63. For example, the original encoder 6131 supplements and/or packs the code stream output by the SPP encoder in the second channel 612, and then sends it to the code stream organizing unit 63, so that the code stream organizing unit 63 calculates the number of codes corresponding to one code block. Each code stream is organized into code streams.

Bit-plane coding refers to SPP/MRP/CUP coding. The result of bit-plane scanning and coding is context and decision information. The bit-plane encoding unit 61 sends the encoding result to the arithmetic encoding unit 62 or the raw encoder 6131, and the arithmetic encoding unit 62 or the raw encoder 6131 performs encoding. For each bit plane, as shown in FIG. 5, the bit plane encoding unit 61 can divide it into a stripe every 4 rows, and scan the stripe in the order from top to bottom, from left to right. The order of scanning the bits in each strip, starting from the highest bit plane, and then coding to the lowest bit plane.

Specifically, SPP scanning and coding are performed first, then MRP scanning and coding are performed, and finally CUP scanning and coding are performed. In order to speed up, three channels (SPP, MRP and CUP) can be deployed in parallel scanning and coding.

When SPP, MRP, and CUP are scanned and coded in parallel, they can be coded based on the coding state of the bit-plane's saliency information, and the state of the neighboring coefficients of the coefficient to be scanned. The coding result obtained after scanning and coding the coefficient to be scanned That is, the context and decision information output by the SPP encoder, MRP encoder and CUP encoder. The coefficient to be scanned can be used to determine the status of the neighborhood coefficient of the coefficient through the 8 neighborhoods around it. Among them, these 8 neighborhoods can be divided into 3 categories: horizontal (h), vertical (v) and diagonal (d). For example, as shown in FIG. 6, assuming that the coefficient P is the coefficient to be scanned, the eight neighborhoods of the coefficient P are D0, V0, D1, H0, H1, D2, V1, and D3.

It should be noted that if the coefficient becomes significant in the SPP encoding channel, the significant status is immediately updated to 1. Therefore, when SPP, MRP and CUP are scanned and coded in parallel, there is a gap between the scanning time of MRP and CUP and the scanning time of SPP.

Fig. 7 is an example of scanning windows of SPP, MRP and CUP of the present application.

As shown in Figure 7, taking one column of the stripe as a scanning window, when SPP scans p4, p5, p6, and p7 in the T+1 scan window, MRP and CUP scan p1, p2 in the T scan window , P3 and p4, that is, the scanning window T of MRP and CUP lags behind the scanning window T+1 of SPP to ensure that when MRP and CUP are scanning, the coefficients to be scanned have been updated in the SPP encoding channel, thereby ensuring that MRP and CUP The correctness of the CUP encoding.

In the scanning window shown in Figure 7, when SPP, MRP and CUP are scanned and coded in parallel, the scanning and coding sequence is p0, p1, p2, p3, p4, p5, p6, p7,.... The coding of p1 needs to know the importance information of p0 (p0 is the top neighbor of p1), and the coding of p2 needs to know the importance information of p1. By analogy, bit-plane coding at a rate of 4bit/cycle can be realized with the longest logic The path is p0-p3.

SPP, MRP, and CUP all use one column of a stripe as a scanning window, and the scanning and encoding of 4 coefficients (also called bits) can be realized in one scanning window.

But because at the end of p1 scan, the neighbors of p4 can already be determined, so p4 can start scanning and coding at the same time as p2; similarly, at the end of p2 scanning, the neighbors of p5 can be determined, and p5 can start scanning and coding at the same time as p3. .

It can be seen that by setting the number of coefficients (for example, 6) included in the scan windows of SPP, MRP, and CUP, the bit-plane coding rate (6bit/cycle) can be further increased without changing the logical longest path.

Fig. 8 is another example of scanning windows of SPP, MRP and CUP of the present application.

As shown in Figure 8, therefore, taking the 6 coefficients (also called bits) of the stripe as a scanning window, taking the T-th scanning window as an example, at the end of the p1 scan, the neighbors of p4 can be determined at the same time, and then P4 and p2 can be scanned and coded at the same time; similarly, at the end of the p2 scan, the neighbors of p5 can be determined, and then p5 and p3 can be scanned and coded at the same time. As a result, the bit-plane coding at a rate of 6bit/cycle is realized, and the longest logical path is still p0-p3.

The structure of the encoder 7 provided in the embodiment of the present application has been exemplified above in conjunction with FIGS. 3 to 8. The structure of the decoder 8 provided by the embodiment of the present application will be illustrated below with reference to FIG. 9.

As shown in FIG. 9, the decoder 8 may include one or more of the following circuits: code stream reading circuit 81, code stream analysis circuit 82, decoding circuit 83, inverse quantization circuit 84, inverse transform circuit 85, output circuit 86.

The code stream reading circuit 81 can be used to read the code stream to be decoded. The code stream reading circuit 81 can, for example, use an advanced extensible interface (AXI) to read the code stream to be decoded from an external memory (such as a memory).

The code stream parsing circuit 82 may also be referred to as a code stream header parser circuit (header parser). The code stream analysis circuit 82 can parse various types of header information in the code stream, and separate parameters and code stream data related to decoding therefrom for use by the decoding circuit 83 at a later stage.

The decoding circuit 83 may include one decoding unit or parallel multiple decoding units (the specific number can be configured according to actual needs, for example, 8 parallel decoding units can be configured). Each decoding unit in the decoding circuit 83 can independently decode a code block.

In some embodiments, before the decoding circuit 83, a preprocessing circuit may also be provided. The preprocessing circuit can be used to distribute the decoding parameters, code stream data, etc. output by the code stream analysis circuit 82 to parallel multiple decoding units.

In some embodiments, after the decoding circuit 83, a post-processing circuit may also be provided. The post-processing circuit can be used to reorganize the decoded data output by the decoding circuit 83 and output the organized data to the subsequent circuit.

The inverse quantization circuit 84 can be used to inverse quantize the data decoded by the decoding circuit 83.

The inverse transform circuit 85 can be used to inversely transform the data output by the inverse quantization circuit 84. The inverse transform can be discrete wavelet inverse transform.

The output circuit 86 can be used to write the data output by the inverse conversion circuit 85 into an external memory. For example, the data output from the inverse conversion circuit 85 can be written into an external memory through AXI.

In some embodiments, the decoder 8 may also include a software configuration interface. The software configuration interface can configure or change the information in the internal registers of the decoder 8 to control the decoding mode of the decoder 8.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc. .

A person of ordinary skill in the art may realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this document can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (35)

1. An encoder, characterized in that it comprises:

   The Tier-1 coding unit performs tier-1 coding on the code block of the image block of the image to be coded to obtain the code stream of the code block;

   Wherein, the Tier-1 coding unit includes:

   A bit-plane encoding unit, the bit-plane encoding unit includes a first channel and a second channel, the first channel and the second channel are used to perform bit-plane encoding on multiple bit-planes of the code block in parallel, Obtain the code stream of the code block;

   The arithmetic coding unit is used to perform arithmetic coding on the code stream of the code block to obtain the target code stream.
2. The encoder according to claim 1, wherein the first channel is used to perform bit plane encoding on the highest bit plane of the plurality of bit planes and three planes below the highest bit plane, and The second channel is used to perform bit plane encoding on the planes other than the highest bit plane and the three planes below the highest bit plane among the multiple bit planes.
3. The encoder according to claim 1 or 2, wherein the first channel and the second channel are both configured with a saliency propagation channel SPP, an amplitude refinement channel MRP, and a clear channel CUP.
4. The encoder according to claim 3, wherein the SPP and MRP in the first channel are used for scanning and encoding in parallel, and the CUP in the first channel is used for scanning and encoding separately, and The SPP, MRP and CUP in the second channel are used to scan and encode in parallel.
5. The encoder according to claim 3, wherein the first channel is configured with 1 run-length encoding RLC encoder, 4 amplitude refinement encoding MRC encoders, 4 saliency encoding ZC encoders, and 4 A symbol encoding SC encoder, wherein the SPP and CUP in the first channel share the 4 ZC encoders and 4 SC encoders.
6. The encoder according to claim 3, wherein the SPP, MRP and CUP in the first channel are scanned and encoded in units of 6 bits, and the SPP, MRP and CUP in the second channel are Scanning and encoding are performed in units of 6 bits.
7. The encoder according to claim 3, wherein the bit-plane coding unit further comprises:

   The distribution unit is configured to distribute the coding result output by the first channel and the coding result output by the second channel to the arithmetic coding unit.
8. The encoder according to claim 7, wherein the distributing unit further comprises:

   The original encoder, which is used to pack the encoding result of the SPP output and the result of the MRP output in the second channel.
9. The encoder according to claim 7, wherein the distributing unit comprises:

   The first buffer is used to buffer the encoding result output by the first channel;

   The second buffer is used to buffer the encoding result output by the second channel.
10. The encoder according to claim 9, wherein the first buffer comprises:

    The third buffer is used to buffer the encoding results output by the SPP and CUP in the first channel;

    The fourth buffer is used to buffer the encoding result output by the MRP in the first channel.
11. The encoder according to claim 9, wherein the second buffer comprises:

    The fifth buffer is used to buffer the encoding result output by the MRP in the second channel;

    The sixth buffer is used to buffer the coding result output by the CUP in the second channel.
12. The encoder according to claim 11, wherein the bit-plane coding unit further comprises:

    A code stream organizing unit, the code stream organizing unit is used to organize the encoding result output by the fifth buffer and the encoding result output by the sixth buffer and subjected to arithmetic coding.
13. The encoder according to claim 12, wherein the code stream organization unit comprises:

    The seventh buffer is used to buffer the code stream organized by the code stream organization unit.
14. The encoder according to any one of claims 1 to 13, wherein the arithmetic coding unit comprises:

    A first arithmetic encoder, configured to perform arithmetic coding on the code stream output by the first channel according to the context information output by the first channel;

    The second arithmetic encoder is configured to perform arithmetic coding on the code stream output by the second channel according to the context information output by the second channel.
15. The encoder according to claim 14, wherein the first arithmetic encoder is configured such that the first 4 bit planes of the bit plane encoding performed by the first channel are used for probability transfer of arithmetic encoding; The two arithmetic encoders are configured such that the probability that a subsequent bit plane is used for arithmetic coding by bit plane coding by the second channel is not transmitted.
16. The encoder according to any one of claims 1 to 15, wherein the encoder further comprises:

    The post-processing module is used to store the code stream formed by encoding the code block.
17. The encoder according to any one of claims 1 to 16, wherein the encoder further comprises:

    The preprocessing module is used to decompose the wavelet coefficients of the code block into multiple bit planes, and reorganize the multiple bit planes after decomposing and send them to the bit plane coding unit.
18. An encoding and decoding system, characterized in that it comprises:

    The encoder according to any one of claims 1 to 17;

    And a decoder corresponding to the encoder.
19. An encoding method, characterized by comprising:

    Bit-plane encoding is performed in parallel on multiple bit-planes of the code block of the image block of the image to be coded through the first channel and the second channel to obtain the code stream of the code block;

    Perform arithmetic coding on the code stream of the code block to obtain the target code stream.
20. The method according to claim 19, wherein said performing bit-plane coding in parallel on multiple bit-planes of the code block of the image block of the image to be coded through the first channel and the second channel comprises:

    Performing bit plane encoding on the highest bit plane of the plurality of bit planes and the three planes below the highest bit plane through the first channel;

    Bit-plane coding is performed on the planes other than the highest bit plane and the three planes below the highest bit plane among the multiple bit planes through the second channel.
21. The method according to claim 19 or 20, wherein the first channel and the second channel are both configured with a saliency propagation channel SPP, an amplitude refinement channel MRP, and a clear channel CUP.
22. The method according to claim 21, wherein the SPP and MRP in the first channel are used for scanning and encoding in parallel, and the CUP in the first channel is used for scanning and encoding individually, and the The SPP, MRP and CUP in the second channel are used to scan and encode in parallel.
23. The method according to claim 21, wherein the first channel is configured with 1 run-length encoding RLC encoder, 4 amplitude refinement encoding MRC encoders, 4 saliency encoding ZC encoders, and 4 Symbol encoding SC encoder, wherein SPP and CUP in the first channel share the 4 ZC encoders and 4 SC encoders.
24. The method according to claim 21, wherein the SPP, MRP and CUP in the first channel are scanned and coded in units of 6 bits, and the SPP, MRP and CUP in the second channel are scanned and encoded in units of 6 bits. Scanning and encoding are performed in units of bits.
25. The method of claim 21, wherein the method further comprises:

    Distribute the encoding result output by the first channel and the encoding result output by the second channel to the arithmetic coding unit.
26. The method of claim 21, wherein the method further comprises:

    Packing the encoding result of the SPP output and the result of the MRP output in the second channel.
27. The method of claim 26, wherein the method comprises:

    Buffering the encoding result output by the first channel in the first buffer;

    The encoding result output by the second channel is buffered in the second buffer.
28. The method according to claim 27, wherein the first cache includes a third cache and a fourth cache;

    Wherein, the buffering the encoding result output by the first channel to the first buffer includes:

    Buffering the encoding results output by the SPP and CUP in the first channel in the third buffer;

    Buffer the encoding result output by the MRP in the first channel to the fourth buffer.
29. The method according to claim 28, wherein the second cache includes a fifth cache and a sixth cache:

    Wherein, the buffering the encoding result output by the second channel to the second buffer includes:

    Buffering the encoding result output by the MRP in the second channel to the fifth buffer;

    Buffer the coding result output by the CUP in the second channel to the sixth buffer.
30. The method according to claim 29, wherein the method further comprises:

    Organize the encoding result output by the fifth buffer and the encoding result output by the sixth buffer and subjected to arithmetic coding.
31. The method of claim 30, wherein the method comprises:

    Buffer the code stream organized by the code stream organization unit.
32. The method according to any one of claims 19 to 31, wherein the method further comprises:

    Using a first arithmetic encoder to perform arithmetic coding on the code stream output by the first channel according to the context information output by the first channel;

    According to the context information output by the second channel, a second arithmetic encoder is used to perform arithmetic coding on the code stream output by the second channel.
33. The method according to claim 32, wherein the first arithmetic encoder is configured to use the first 4 bit planes of the first channel to perform bit plane coding for probability transfer of arithmetic coding; the second The arithmetic encoder is configured such that the probability of the subsequent bit-plane encoded by the second channel for the arithmetic encoding is not transmitted.
34. The method according to any one of claims 19 to 33, wherein the method further comprises:

    Store a code stream formed by encoding through the code block.
35. The method according to any one of claims 19 to 34, wherein the multiple bit planes of the code block of the image block of the image to be coded through the first channel and the second channel are subjected to bit-plane encoding in parallel , The method further includes:

    The wavelet coefficients of the code block are decomposed into multiple bit planes, and the decomposed multiple bit planes are reorganized and sent to the bit plane coding unit.

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