CN1564200A - VLS realizing method for position plane coder of 0 redundancy coded clock - Google Patents

Abstract

Three dedicated circuits are provided in VLSI design for bit plane coder in JPEG2000. Fetching out pixel point to be decoded from code block storage, meanwhile the 'MSB' detect circuit and state variable generation circuit generates state variable needed in coding context so as to save memory for state variable and save clock timing. In PASS1 coding, since column NBC index determination and generation circuit with no redundancy timing is utilized, the determining clock and coding clock only expend one timing cycle. In PASS3 coding, since column NBC index determination and generation circuit as well as control signal generation circuit of realizing pipeline for RLC, ZC and SC are utilized, the determining clock and coding clock only expend one timing cycle. In coding procedure, the two circuits provide quickest coding speed without waste timing.

Description

A kind of VLSI implementation method of bit plane encoder of 0 redundancy encoding clock

Technical field

The invention belongs to the VLSI design field.Be specifically related in JPEG2000 hardware is realized, the part Key Circuit be adopted special designs, obtain efficiently (low status register), and have the VLSI implementation method of the bit plane encoder of 0 redundancy encoding clock.

Background technology

JPEG2000 mainly is made up of two parts: wavelet transform (DWT) and EBCOT.Wavelet transformation is frequency field with image from space field transformation, and the coefficient that conversion produces is carried out entropy coding through quantizing the back by EBCOT.Bit-Plane Encoding among the EBCOT provides context (CX) and D (resolution) for arithmetic encoder.But in the process that context generates, the context of each sampled point is by the state decision of its field sampled point.Each sampled point comprises five state variable: v (amplitude), s (symbol), δ (validity), π (coding complement mark), ξ (whether entering for the first time the amplitude refinement).If code block size is 64 * 64 o'clock, need 20K state variable storer altogether, the writing and reading and writing of status register simultaneously, the streamline when having interrupted realizing greatly reduces coding rate, and has increased the complicacy of control circuit.In the context generative process, need bitplanes to carry out repeatedly scanning encoding in addition, paid very big cost in time.These two shortcomings make JPEG2000 scrambler whole efficiency very low, high quality graphic is difficult to carry out Real Time Compression handles.

Summary of the invention

At defective that exists in the above-mentioned background technology and deficiency, the objective of the invention is to, in the design of bit plane encoder, introduce 3 special circuits, realize (stateless storer) efficiently, and the VLSI method of 0 redundancy encoding clock.

For achieving the above object, the technical solution that the present invention adopts, carry out in the following manner:

1) by " MSB " testing circuit and state variable generative circuit

Described " MSB " testing circuit and state variable generative circuit be: each pixel, we are referred to as msb the highest significance bit plane, suppose that A is 16 integers, as A=0X0A00, msb (A)=12 then; Suppose that current bit plane of encoding is currentbp, the pixel to be encoded in when output is A from code block, then when currentbp＜msb (A), and δ (A)=1, otherwise δ (A)=0.

2) the row NBC index of irredundant clock is judged and generative circuit

The row NBC index of described irredundant clock is judged and the generative circuit technology is: Bit-Plane Encoding in the process of implementation, four data of each scanning one row, yet these four points are not all to need to encode, utilize the window treatments function, find the point that to encode, its information is input in the NBC index circuit.The index of the point that the output of this circuit need be encoded when the prostatitis, so just having skipped does not need the picture element of encoding, and has saved the clock period.When the point of needs codings all be encoded finish after, row (change column) request signal next column data are changed in the output of NBC index circuit.

3) RLC, the control signal generative circuit of the continuous programming code of ZC and SC

Described RLC, the control signal generative circuit technology that the continuous programming code of ZC and SC realizes is: at the PASS1 passage, ZC and SC coding need be carried out,, RLC need be carried out at the PASS3 passage, ZC, the SC coding at the PASS1 passage, need carry out ZC and SC coding; At the PASS3 passage, need carry out RLC, ZC and SC coding; When PASS1 encodes, judge and generative circuit by the row NBC index of irredundant clock, make that the clock consumption when coding only is 1 judgement clock and encoded clock; When PASS3 encodes, use RLC, control signal generative circuit that the flowing water of ZC and SC is realized and row NBC index are judged and generative circuit, make that the clock consumption when coding only is 1 judgement clock and encoded clock, can when encoding, obtain the fastest coding rate by these two circuit, no clock waste.

During the VLSI that the present invention is directed to bit plane encoder realized, the Several Key Problems that institute must processing had provided its special circuit implementation structure.In the design based on the related bit plane encoder of row realizes, wherein the utilization of MSB testing circuit can be saved whole status registers, the row NBC index of irredundant clock judges and generative circuit technology and RLC, the control signal generative circuit technique guarantee that the continuous programming code of ZC and SC realizes the irredundant clock design realization during coding.

Description of drawings

Fig. 1 is a coded scanning synoptic diagram in the code block;

Fig. 2 is signal of channel parallel encryption algorithm and window synoptic diagram;

Fig. 3 is inspection 0 circuit diagram of pixel A;

Fig. 4 is a NBC index generative circuit.

Fig. 5 is RLC, ZC, the SC sequential chart of encoding.

Fig. 6 provides one and comprises the MSB testing circuit, NBC circuit and RLC, and ZC, the PASS3 coding that SC flowing water is realized is realized figure.

Fig. 7 is 8 fields of an X, wherein H ₀, H ₁The expression horizontal direction, D represents the diagonal angle, V represents vertical direction.

Embodiment

The present invention is described in more detail below in conjunction with embodiment that accompanying drawing and inventor provide, but the present invention is not limited to this embodiment.

The embodiment algorithm of 1 couple of this paper is done simple declaration at first in conjunction with the accompanying drawings, and the order of Bit-Plane Encoding is from MSB to LSB, and each bit plane comprises three coding passes:

PASS1: validity propagation ducts (Significant Propagation Pass)

PASS2: amplitude refinement (Magnitude Refinement PASS)

PASS3: remove passage (Cleanup Pass)

Sole exception be the MSB bit plane, include only PASS3 coding.In the coding mode of JPEG2000 acquiescence, remaining bit plane passes through the PASS1 passage in proper order when coding, the PASS2 passage, and the PASS3 passage is encoded.Each picture element judges that according to the state in its field entering which passage encodes.In the process of flat scanning on the throne, need the state variable of each pixel be refreshed: δ (validity), π (whether being encoded), ε (whether entering for the first time the amplitude refinement).

The channel parallel pattern is one of pattern of JPEG2000 agreement support, and last pixel of each row only needs to judge 5 neighborhoods when generating context; But first pixel still needs to judge 8 neighborhoods.Adopt a kind of status register structure of going to prestore that each is listed as the state of validity of last point.S working storage and C working storage, these two capable state working storages write down the state of validity value of last point of every row among PASS1 and the PASS3 respectively, after last picture element coding of each row is finished, need upgrade the value of row working storage.

According to Key Circuit of the present invention, the inventor has provided an exemplary embodiments.Use in the present embodiment be in the JPEG2000 standard based on the related channel parallel Bit-Plane Encoding of row.In the present embodiment, at first introduce MSB testing circuit and state variable generative circuit:

In the JPEG2000 agreement, the state variable of each pixel is exactly validity variable δ, whether enter for the first time amplitude refinement variable ξ, amplitude v, symbol s, coding is finished variable π, when carrying out bit plane scanning each time, can obtain v and s variable easily, coding is finished variable π need be according to the decision of the data after the front passage displacement, and validity δ and whether for the first time enter amplitude refinement variable ξ and need frequent updating is during the employing storage operation, data access and read operation make the control program complexity, and have wasted the time cycle.The MSB circuit is judged δ and ξ by combinational logic in a clock, do not need to upgrade.Its ultimate principle is: each pixel, and the highest significance bit plane is msb, supposes that current bit plane of encoding is currentbp, when currentbp＜msb, δ=1, otherwise δ=0; If msb＜2 ξ=0 of this pixel; Otherwise, if currentbp＜and during msb-2, ξ=1, other situations ξ=0.

In design, suppose when small echo carries out 9/7 wavelet transformation that output data is 16 through the bit depth after quantizing, wherein most significant digit is a sign bit, other 15 is data bit.In Fig. 1, only provided shiftbit[3:1] realization, similarly, can obtain shiftbit[0], A represents the data exported behind the wavelet transformation, passes through combinational logic, the shiftbit[3:0 that obtains] for the most significant digit of A zero number before the msb, so msb=15-shift[3:0].And then relatively can obtain the state variable of A with currentbp, these operations are combinational logic, can finish in a clock period, use in the time of can reading row (stripe) data during specific implementation from code block.Reached and both saved storer and saved the spent clock of access status variable simultaneously.

The row NBC index of described irredundant clock is judged and generative circuit technology and RLC, the control signal generative circuit technology that the flowing water of ZC and SC is realized is: because of both have correlativity, the argumentation of putting together, at the PASS1 passage, need carry out ZC and SC coding, at the PASS3 passage, need carry out RLC, ZC, SC coding, normally adopt state machine to realize, when the state redirect, can produce the clock redundancy, utilization this method, efficiently realize the stream line operation of three kinds of coded systems, do not produced the clock redundancy.

At Bit-Plane Encoding in the process of implementation, four data of each scanning one row, yet these four points are not all to need to encode, according to the window treatments function, at first calculate the field material information of 4 pixels of current row to be encoded, its information is input in the NBC index circuit, the index of the point that need encode in the prostatitis is worked as in this circuit output, so just having skipped does not need the picture element of encoding, and has saved the clock period.When the point of needs codings all be encoded finish after, row (change column) request signal next column data are changed in the output of NBC index circuit.

Classify example explanation PASS1 coding as with P1,, calculate its h, v earlier for P10, the validity value of d, as shown in Table 1, as h, v, arbitrary in the d value is 1, represents that then this point needs coding in PASS1, is judging P11 whether when PASS1 encodes, usefulness δ ' in the calculating of window logic ₁₀=(h ₁₀| v ₁₀| d ₁₀) ﹠amp; v ₁₀Replace δ ₁₀NBCflag[3:0] be 4 line variable, be used for representing P10, P11, P12, whether four points of P13 encode in PASS1, like this NBCflag[0]=h ₁₀| v ₁₀| d ₁₀

Nbccounter is illustrated in counting that the P1 row need be encoded among the PASS1.

Nbccounter＝NBCflag[3]+NBCflag[2]+NBCflag[1]+NBCflag[0]

Pixelcounter: expression is since 0 counting, when its value equals nbccounter, NBC index generative circuit is the combinational logic that MUX is formed, at Fig. 3, indicate 1～7 and have seven nodes altogether, be designated as temp1-temp7 respectively, wherein temp1-temp6 is respectively the output of the MUX of 6 alternatives

Use se11 respectively, sel2, sel3, sel4, sel5, sel6 represent the selecting side condition of 6 multiselects, for example: at nbcflag[2]=1 o'clock, temp1=2 ' b10, otherwise temp1=2 ' b11 then like this in conjunction with Fig. 3, can be expressed as:

sel1＝nbcflag[2]

sel2＝nbcflag[1]

sel3＝nbcflag[0]

sel6＝nbcflag[2]&nbcflag[1]&nbcflag[0]

Temp3, temp4, temp5, temp7 are one four output of selecting one MUX, the selection termination pixelcounter of selector switch wherein, and when pixelcounter=01, nbcindex=temp5.

Like this when PASS1 encodes, as 1≤pixelcount er≤nbccounter, should carry out the ZC coding, simultaneously according to the value of nbcindex with corresponding h _Nbcindex, v _Nbcindex, d _NbcindexValue deliver in the context formation logic of ZC, generate the ZC context under each encoded point.

As v[nbcindex]=1 the time, after the ZC coding, also need carry out the SC coding, at this moment, the value of pixelcounter need keep two clocks, producing a clock ZC coding respectively in proper order enables to enable with the SC coding, nbcindex keeps two clocks simultaneously, with corresponding h, v, d and S signal value are delivered to the context formation logic of ZC and the context formation logic of SC, like this when the coding of PASS1 the number of required clock for only being window logical timer (1)+encoded clock, promptly utilize the row NBC index of irredundant clock to judge and generative circuit technology and RLC, the control signal generative circuit technology that the flowing water of ZC and SC is realized has realized that the nothing of PASS1 coding holds surplus clock realization.

To PASS3 coding, because RLC may take place, three kinds of codings of ZC and SC, specifically can be according to the following steps when realizing:

At first the column data to input carries out the RLC judgement, if satisfy the RLC encoding condition, enters the RLC channel coding.

If V ₅₀, V ₅₁, V ₅₂, V ₅₃Be 0 entirely, then only need an encoded clock, as not being 0 entirely, as 1010, correct coding should be 100S010, is the RLC coding to 100S, need carry out ZC to 010 and encode, so temporary variable nbcflagtemp=4 ' b0111 represents that back three numbers in these row need be carried out the ZC coding.The 3rd clock period, need data to send into SC context formation logic, the 4th clock period, output SC coding context, (be located at before this simultaneously, by the coloumn_change signal with ZC coding counter pixelcounter clear 0), the value of NBCflagtemp is composed NBCflag to the NBC circuit, as describing among the PASS1, in the contextual output of the 5th clock output ZC, the output that produces ZC when needed simultaneously, required clock number only judges for RLC or ZC judges (1 clock)+RLC coding, the ZC coding, the SC encoded clock, realized the irredundant clock flowing water realization of PASS3 channel coding, one shown in Figure 4 comprises the RLC coding, ZC coding, the sequential chart of SC coding, only provide the RLC in the reality among the figure, the enable signal of ZC or SC (en).Fig. 6 provides one and comprises the MSB testing circuit, NBC circuit and RLC, and ZC, the PASS3 coding that SC flowing water is realized is realized figure, PASS1 is only encoding with no RLC with the different of PASS3.The coding of PASS2 is fairly simple, so do not discuss in this facility example.

Following table is the calculating of window logic

Alphabetical implication in the table is explained:

At first: v (amplitude), s (symbol), δ (validity), π (coding complement mark), ξ (whether entering for the first time the amplitude refinement).P ₁₁Represent the point in the accompanying drawing 2, Figure 7 shows that 8 fields of an X, wherein H ₀, H ₁The expression horizontal direction, D represents the diagonal angle, V represents vertical direction.

Therefore: $h={\mathrm{\&delta;}}_{P_{20}}+{\mathrm{\&delta;}}_{{\mathrm{<figure-callout\; id="00"\; label="P"\; filenames="A200410026018.500111.png"\; state="\{\{state\}\}">P</figure-callout>}}_{00}},$ Expression point P ₁₀The horizontal direction validity contribution h of expression can be by δ _P20+ δ _P00, i.e. P ₀₀, P ₂₀The validity sum of point represents, V as can be known in like manner, and the implication of d, δ is illustrated in P ₁₀After the coding, the updating value of validity.

Claims (1)

1. the VLSI implementation method of the bit plane encoder of a redundancy encoding clock is characterized in that, carries out according to the following steps:

1) by " MSB " testing circuit and state variable generative circuit

By " MSB " testing circuit and state variable generative circuit, when picture element to be encoded takes out from the code block storer, generate its state variable required in context coding by " MSB " testing circuit, for each pixel, the highest significance bit plane is called msb, suppose that A is 16 integers, as A=0X0A00, msb (A)=12 then; Suppose that current bit plane of encoding is currentbp, the pixel to be encoded in when output is A from code block, then when currentbp＜msb (A), and δ (A)=1, otherwise δ (A)=0;

2) the row NBC index of irredundant clock is judged and generative circuit

Bit-Plane Encoding scans four data of row in the process of implementation at every turn, yet these four points are not all to need to encode, and utilize the window treatments function, find the point that need encode, and its information is input in the NBC index circuit; The index of the point that the output of this circuit need be encoded when the prostatitis, skipping does not need the picture element of encoding, to save the clock period; When the point of needs codings all be encoded finish after, column signal request next column data are changed in the output of NBC index circuit;

3) the control signal generative circuit of the flowing water of RLC, ZC and SC realization

At the PASS1 passage, need carry out ZC and SC coding; At the PASS3 passage, need carry out RLC, ZC and SC coding; When PASS1 encodes, judge and generative circuit by the row NBC index of irredundant clock,, make that the clock consumption when coding only is 1 judgement clock and encoded clock; When PASS3 encodes, use RLC, control signal generative circuit that the flowing water of ZC and SC is realized and row NBC index are judged and generative circuit, make that the clock consumption when coding only is 1 judgement clock and encoded clock, can when encoding, obtain the fastest coding rate by these two circuit, no clock waste.

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