CN1717049A - Wavelet changeable VLSI structure based on line - Google Patents
Wavelet changeable VLSI structure based on line Download PDFInfo
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- CN1717049A CN1717049A CN 200510042864 CN200510042864A CN1717049A CN 1717049 A CN1717049 A CN 1717049A CN 200510042864 CN200510042864 CN 200510042864 CN 200510042864 A CN200510042864 A CN 200510042864A CN 1717049 A CN1717049 A CN 1717049A
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Abstract
This invention discloses a super large scale IC VLSL structure of a small wave transformation based on lines including a first stage line transformer, a column transformer, a middle buffer, a multiple-stage small wave factor output controller and an external storage, among which, said first stage line transformer carries out small transformation of a first line direction, the second and above the second stage line transformers carry out line direction small wave transformation to the first stage small wave transformed low frequency sub-band system and writes the result into the middle buffer, a column transformer fetches the data of the buffer to finish the column direction small wave transformation and outputs the result to the multiple-stage factor output the result to the multiple-stage factor output controller, which re-selects and buffer stores the column transformed factors of each stage and the sub-band factors of each stage are output to the next stage line transformer, the rest factors are output to the external storage.
Description
Technical field:
The present invention relates to the image compression encoding field, particularly a kind of very lagre scale integrated circuit (VLSIC) (VLSI) structure based on the wavelet transformation of going is used for various digital image codings.
Technical background:
Along with multimedia and development of internet technology and application, people increase day by day to the demand of image information.And therefore the huge data volume that image comprised, need utilize the image compression encoding technology that image is efficiently compressed to adapt to the requirement of real-time Transmission and efficient storage to transmission channel with a constant volume with storage medium is exerted heavy pressures on and difficulty.Method for encoding images in the past mainly comprises entropy coding, differential pulse code modulation DPCM method, based on the compression method of discrete cosine transform DCT etc., especially the compaction coding method based on DCT has formed based on JPEG and international standard H.261, and is widely used in the every field of image compression and Video processing.But these methods all exist certain limitation, such as, the compression efficiency of entropy coding and DPCM is not high, and compression ratio is paced up and down between 1.5～3; And based on the JPEG method of dct transform, though can remove the data redundancy in the piece to a great extent, but the structural redundancy that is difficult to removal of images integral body, under the situation of high compression ratio, quantizing distortion is bigger, can cause the tangible collimation error, produce serious blocking artifact and edge gibbs Gibbs effect, can't satisfy the demand of practical application.
With respect to method for encoding images in the past, overcome the intrinsic blocking artifact of DCT with the wavelet transformation fully by the method for compressing image of core, have that compression ratio height, compression speed are fast, can inhibit signal after the compression constant, recovery signal noise ratio (snr) of image height with the feature of image, can realize progressive transmission and can be anti-interference in transmission etc. advantage, thereby be with a wide range of applications.What adopt among the up-to-date Joint Photographic Experts Group JPEG2000 is exactly small wave converting method.Traditional wavelet transformation adopts the method for Mallat bank of filters, and this method computation complexity is far above the DCT algorithm, and therefore wavelet transformation all fails to be applied in the realtime graphic compressibility for a long time.The notion of Lifting Wavelet has been proposed up to people such as Wim.Sweldens in 1994, compare with traditional wavelet transformation, Lifting Wavelet greatly reduces required amount of calculation of wavelet transformation and memory space, have computation complexity low, can realize that former bit arithmetic, inverse transformation form are simple and can realize advantage such as integer quotient wavelet transformation.So, just can in real-time system, realize wavelet transformation, make based on the image compression encoding technology of wavelet transformation and really move towards to use with lower cost.
Comprise three steps by promoting the structure small echo: at first being " Lazy " wavelet transformation, promptly data being divided into two subclass, is respectively even number set and odd number set; Second step was that antithesis promotes, promptly gather and predict the odd number set with even number, the error of generation as the high pass wavelet coefficient; Be original lifting at last, promptly upgrade the even number set as low pass scaling function coefficient with these wavelet coefficients.
The core of wavelet transformation is to select for use different wavelet basiss to carry out wavelet transformation according to different needs, wavelet transformation commonly used has 9/7 wavelet transformation and 5/3 wavelet transformation, wherein 9/7 wavelet transformation is used for lossy compression method, its best performance, and 5/3 wavelet transformation is used for lossless compress.Concrete computing formula is as follows:
Formula (1) is 9/7 wavelet transformation computing formula, and formula (2) is 5/3 wavelet transformation computing formula, wherein d[n], s[n] be respectively the high frequency wavelet coefficient and the low frequency wavelet coefficient that obtain through one-dimensional wavelet transform.By above-mentioned formula as seen, one dimension 9/7 wavelet transformation need carry out for four steps and promote, and promptly calculated wherein d successively according to formula 1
1, s
1, d, s; One dimension 5/3 wavelet transformation then only need carry out the lifting of two steps, promptly calculates d and s according to formula 2.
Because picture signal is a 2D signal, then needs it is carried out two-dimensional wavelet transformation.Two-dimensional wavelet transformation can be decomposed into two one-dimensional wavelet transforms on the row, column direction.One time 2-d wavelet decomposes a low frequency subgraph LL of generation and three high frequency subgraphs, promptly horizontal subgraph LH, vertical subgraph HL and diagonal angle subgraph HH.The next stage wavelet transformation is to carry out on the basis of the low frequency subgraph LL that prime produces.So repeat repeatedly, just can obtain exploded view through the multilevel wavelet conversion.
Hardware for lifting wavelet transform realizes that conventional method is to adopt the table tennis storage means, and its structured flowchart comprises a wavelet transformation module and a plurality of static random access memory SRAM as shown in Figure 5.This method at first reads the entire image data, earlier to all row, more all row is carried out wavelet transformation respectively, thereby obtains the wavelet conversion coefficient of entire image then.If the time of input piece image is T, each static random access memory SRAM can both store the data of an entire image, if will do 4 grades of wavelet transformations, and to guarantee the requirement of real-time, and then the 1st grade of line translation needs time T, and data are according to line direction input, line direction output, transformation results is buffered among the SRAM1, the 1st grade of rank transformation also needs time T, data according to the direction of row read in, line direction output, transformation results is buffered among the SRAM2.It is T/4 that the 2nd grade of line translation needs the time, data according to the direction of row read in, line direction output, transformation results is buffered among the SRAM3, the 2nd grade of rank transformation also needs time T/4, data according to the direction of row read in, column direction output, intermediate object program is stored among the SRAM4.As seen, do the one-level wavelet transformation, data just in two memories table tennis formula transfer once.The total time of 4 grades of wavelet transformations is 2T nearly, and external memory space is 8, and this method has expended a large amount of memory spaces and operation time.
The content of invention
The purpose of this invention is to provide a kind of VLSI structure, to overcome the prior art excessive deficiency of memory space that hardware resource utilization is low, view data is used when being applied to the Real Time Compression coding of rest image and video image based on the wavelet transformation of going.
The key problem in technology of realizing the object of the invention is the characteristic that makes full use of wavelet transform filter, make the line translation and the rank transformation parallel processing of each grade wavelet decomposition, promptly when reading the new data of delegation, do capable wavelet transformation earlier, after obtaining the row of some, begin to be listed as to wavelet transformation, this quantity is determined by filter length.Wavelet decomposition parallel processings at different levels by the spatial cache of effective management intermediate data, are finished the real-time wavelet decomposition to image, have reduced the requirement to the image data storage space simultaneously.
Structure of the present invention comprises one-level line transformer and rank transformation device, intermediate buffer, multilevel wavelet coefficient o controller, external memory storage at least.Wherein:
Line transformer is used to carry out the wavelet transformation of line direction, and transform data is write in the intermediate buffer; The one-level line transformer carries out the wavelet transformation of first order line direction to the raw image data of input, and the low frequency sub-band LL coefficient of line transformer reaching or above grade two after to the previous stage wavelet transformation carries out the wavelet transformation of line direction again;
The rank transformation device is used for finishing the wavelet transformation of column direction from middle buffer sense data, and the wavelet coefficient that rank transformation obtains is outputed to multilevel wavelet coefficient o controller;
Intermediate buffer is used to cushion the output factor of line transformer and the intermediate object program that the rank transformation device produces;
Multilevel wavelet coefficient o controller is used for the coefficient of small echo rank transformations at different levels is carried out final election, buffer memory, and the LL sub-band coefficients of small echos at different levels outputs to next stage small echo line transformer, and all the other sub-band coefficients output to external memory storage in order;
External memory storage, each sub-band coefficients that is used to store the wavelet transformations at different levels that obtain after multilevel wavelet decomposes.
The above line converter is finished the one-dimensional wavelet transform of line direction, comprise one-level lifter and line translation controller at least, each step that lifters at different levels are finished wavelet transformation promotes, the progression of this lifter is relevant with the wavelet transformation of employing, for 5/3 small echo, progression is 2, for 9/7 small echo, progression is 4, promptly need promote through level Four; The line translation controller is given pending data the processing of each lifter, control boundary extension and conversion coefficient is write intermediate buffer according to certain time sequence.
Above-mentioned rank transformation device is finished the wavelet transformation of column direction, comprise one-level lifter and rank transformation controller at least, each step that lifters at different levels are finished wavelet transformation promotes, the progression of this lifter is relevant with the wavelet transformation of employing, for 5/3 small echo, progression is 2, for 9/7 small echo, progression is 4, promptly need promote through level Four; The rank transformation controller is given the processing of each lifter, control boundary extension with pending data according to certain time sequence and is read and write data from middle buffer.
Above-mentioned intermediate buffer comprises a plurality of fifo fifo memories, and the N step that is used for the buffer memory rank transformation promotes the intermediate data that the computing one-level is produced to N-1 level lifter, promotes computing to offer next step.
Above-mentioned multilevel wavelet o controller comprises wavelet coefficient final election device and wavelet coefficient buffer, and wherein the wavelet coefficient buffer comprises output priority controller, read-write controller, data final election device, address generator and each sub-band coefficients corresponding cache space; Wavelet coefficient final election device carries out exporting after the final election to wavelet coefficients at different levels and useful signal thereof, wherein low frequency sub-band LL
1, LL
2... LL
N-1The data of subband and useful signal thereof output to two, three respectively ... N level line transformer, other each subband data and useful signal thereof all output to the wavelet coefficient buffer, and are stored among the FIFO of corresponding cache space; The output priority controller produces the control signal of read-write controller, data final election device and address generator respectively, and exports wavelet coefficients at different levels successively by wavelet coefficient priority order from high to low.
Compared with prior art, the present invention is when carrying out wavelet transformation, with line translation and rank transformation parallel processing, need not to read in simultaneously all line data, and row are to the direction dateout of wavelet transformation according to row, switch reading in proper order of data in the middle of noting be used in each row-column transform, make the next stage line translation can directly begin to tap into row.The present invention has simultaneously not only guaranteed the real-time processing of image with wavelet transformation parallel processings at different levels, has significantly reduced the demand of memory space simultaneously, and can finish the wavelet transformation of an entire image in the time of a T, has saved the processing time.Table 1 is the comparison of the present invention and prior art memory property when carrying out wavelet transformation.
Table 1 the present invention and table tennis storage realize the comprehensive comparison of performance
| The present invention | Prior art | |
| Synthesis tool | Synplify Pro | Synplify Pro |
| Target devices | Xilinx Virtex-II XC2V3000 BG728 | Xilinx Virtex-II XC2V3000 BG728 |
| Design complexities | High | Low |
| Maximum clock | 115MHz | 120MHz |
| The logical block utilization rate | 29％ | 14％ |
| BLOCK RAM utilization rate | 28％ | 0％ |
| External SRAM is used | 1 | 8 |
| Handle the piece image required time | T | 8T |
By table 1 as seen, though the present invention has increased certain design complexities and hardware spending when handling small echo sequential relationship at different levels, but saved external memory space greatly and to processing time of piece image, guaranteed the real-time processing of image, having improved hardware resource utilization, is a kind of implementation of small echo efficiently.
Description of drawings
Fig. 1 the present invention is based on capable wavelet transformation structured flowchart
Fig. 2 is the line transformer structured flowchart that the present invention adopts 9/7 small echo
Fig. 3 is rank transformation device and the intermediate buffer structured flowchart that the present invention adopts 9/7 small echo
Fig. 4 is a multilevel wavelet o controller structured flowchart of the present invention
Fig. 5 is the structured flowchart of existing table tennis storage wavelet transformation
Embodiment
Present embodiment adopts 9/7 small echo as wavelet basis, with XILINX ISE 5.1 integrated developing software and VHDL, Verilog HDL language, finishes 4 grades of wavelet transformations based on row on the XC2V3000-6BG728 of XILINX company programmable chip.
Referring to Fig. 1, the structured flowchart of present embodiment comprises one-level line transformer, secondary line transformer, three grades of line transformers, level Four line transformer, rank transformation device, intermediate buffer, multilevel wavelet coefficient o controller and external memory storages.The one-level line transformer at first carries out the line translation of first order small echo to the raw image data of input, and the first order line translation coefficient that conversion obtains is divided into two-way output, and one the tunnel is input to intermediate buffer with the required intermediate data of buffer memory, and another road is input to the rank transformation device.The rank transformation device is connected with intermediate buffer is two-way, the operation that middle buffer is read or write by the rank transformation controller in the rank transformation device.The rank transformation device is general to small echos at different levels, finishes the small echo rank transformation.Send into the multilevel wavelet o controller through the coefficient behind the first order rank transformation.Through isolating first order low frequency sub-band coefficient LLl sub-band coefficients behind the multilevel wavelet o controller, directly export to the secondary line transformer and carry out second level line translation.The detailed process of one-level small echo row, column conversion is when first order line translation proceeds to the 3rd row, to begin to carry out the 1st step and the lifting computing of the 2nd step of rank transformation.If the wavelet filter length that design is adopted is 2L+1, then when carrying out the capable line translation of L+1, the 3rd step of begin column conversion and the lifting of the 4th step.For 9/7 small echo L=4, promptly rank transformation begins the 3rd step and the lifting of the 4th step when carrying out the line translation of the 5th row.Rank transformation need not to wait until that whole line translation finishes, as long as accumulating certain row much of that according to filter length just can begin, this is based on the most basic characteristics that capable wavelet transformation is different from the traditional wavelet mode.Second and third, the level Four wavelet transformation can be analogized by first order wavelet transformation, when the LL of upper level wavelet transformation sub-band coefficients input next stage line transformer, just begin the small echo line translation of next stage, to have run up to L+1 capable of the begin column conversion when this line translation coefficient.Output in the external memory storage behind the final election of the coefficient process multilevel wavelet o controller that the level Four wavelet transformation obtains and the buffer memory.
Referring to Fig. 2, the small echo line transformers at different levels of present embodiment have identical structure, mainly comprise one-level lifter, two-stage hoisting device, three grades of lifters, level Four lifter, final election device and line translation controllers.Wherein the line translation controller produces the BORDER PROCESSING that signal sel-1, sel-2, sel-3, sel-4 control 4 lifters by counter, and generation and the synchronous dateout useful signal of dateout.The input data are sent into the two-stage hoisting device through a part after the suitable delay, and another part is sent into the one-level lifter, promote through the first step and obtain intermediate data d
1d
1Through suitable delay, a part is sent into three grades of lifters, and another part is sent into the two-stage hoisting device, promotes through second step and obtains intermediate data s
1s
1Through suitable delay, a part is sent into the level Four lifter, and another part is sent into three grades of lifters, promotes through the 3rd step and obtains the high frequency wavelet coefficient d; Coefficient d one tunnel is sent into the final election device, and the level Four lifter is sent into through certain delay in another road, obtains low frequency wavelet coefficient s and sends into the final election device after promoting through the 4th step, obtains dateout through the final election device at last.
Referring to Fig. 3, the intermediate buffer of present embodiment provides five memory spaces for each grade wavelet transformation, i.e. five FIFO, and the original level resolution of establishing image is N, then the FIFO degree of depth of n level wavelet transformation is N/2
N-1The rank transformation device comprises one-level lifter, two-stage hoisting device, three grades of lifters, level Four lifter and rank transformation controllers.Wherein the rank transformation controller comprises the BORDER PROCESSING device, reads effective controller, enables controller, data final election/remove final election device, write data generator, promotes data processor, read data processor with effect controller, lifting; Border extension when the BORDER PROCESSING device is used for wavelet transformation is handled, and the result after the processing sends into respectively and reads effective controller, enables controller with imitating controller and lifting; Read effective controller and produce 5 read and write useful signals respectively with imitating controller, control is to the read and write operation of the corresponding spatial cache of middle buffer; Lifting enables controller and produces 4 lifting enable signals, corresponds respectively to one to the level Four lifter; Data final election/go final election device carries out final election/go final election to handle to the input data; The write data generator will need the intermediate data of buffer memory to write intermediate buffer after will handling through data final election/go final election device; Promote data processor; The read data processor reads in the data cached of intermediate buffer, is used for the lifting conversion of next stage; The final election device is two-way to be connected for an end that promotes data processor and data final election/go, the other end is connected to the level Four lifter is two-way with one respectively, on the one hand with the dateout of data final election/remove the final election device as the lifter that promotes data input respective stages, the coefficient after will promoting is on the other hand sent into data final election/go final election device again.
The process of rank transformation is: at first the coefficient that line translation is obtained is sent into data final election/go final election device, process final election/go final election to handle, the intermediate data that needs is carried out buffer memory outputs to the write data generator, these data are write five spatial cache: FIFO1 that are used for this grade wavelet transformation in the intermediate buffer respectively by the write data generator, FIFO2, FIFO3, FIFO4, FIFO5, simultaneously with imitate controller produce corresponding to each spatial cache FIFO with imitating signal, being used to control the write data generator writes the data of middle buffer, when with imitating signal when effective, write data to intermediate buffer by the write data generator.When needs read data cached when exporting to lifter and promoting from spatial cache FIFO, read useful signal by reading effective controller generation, when this signal is effective, read required intermediate data and send into the read data processor from middle buffer, the data of reading in are successively through read data processor, data final election/after removing the final election device and promoting data processor, export to the one-level lifter as promoting data, promote simultaneously and enable the enable signal of controller generation corresponding to this grade lifter.When this enable signal is effective, carry out the one-level lifting to promoting data, output to again in the lifting data processor through the data after the one-level lifting, through data final election/go final election device, to need data in buffer to output among the FIFO, the data that needs are exported output in the multilevel wavelet o controller.The said process that circulates then carries out secondary, three grades, level Four successively and promotes.Promote through above-mentioned level Four, finish one-level small echo rank transformation, and the data after the conversion are outputed to the multilevel wavelet o controller.
Referring to Fig. 4, the multilevel wavelet o controller comprises wavelet coefficient final election device and wavelet coefficient buffer.Wherein the wavelet coefficient buffer comprises output priority controller, read-write controller, data final election device, address generator and each sub-band coefficients corresponding cache space.Wavelet coefficients at different levels and useful signal thereof are exported each subband data and useful signal thereof through wavelet coefficient final election device, wherein, the data of LL1, LL2, LL3 subband and useful signal thereof output to two, three respectively, the level Four line transformer, other each subband data and useful signal thereof all output to the wavelet coefficient buffer, and are stored among the FIFO of corresponding cache space.The read-write useful signal of FIFO is produced by read-write controller.The output priority controller is used for controlling the priority of each subband data output, to solve the subband data outputs at different levels problem of conflict in time, produce control signal corresponding by a state machine and output to read-write controller, data final election device and address generator, set the priority of wavelet coefficient simultaneously, higher wavelet coefficient is set higher priority.In coefficient when output,, at first reading of data outputs to external memory storage from the FIFO of the highest subband correspondence of priority, reads behind the sky that reading of data outputs to external memory storage from the FIFO of time high subband correspondence of priority again.Data final election device is write in the external memory storage after with the data final election among each FIFO, and address generator produces the corresponding memory address.
For those skilled in the art, after having understood content of the present invention and principle, all may be under the situation that does not deviate from the principle of the invention, structure, carry out various corrections and change on form and the details, can make the VLSI structure that is not limited to based on 4 grade of 9/7 wavelet transformation of row, for example, VLSI structure to based on 3 grade of 5/3 wavelet transformation of going comprises one-level line transformer, secondary line transformer, three grades of line transformers, rank transformation device, intermediate buffer, multilevel wavelet coefficient o controller and external memory storages; Each line transformer comprises one-level lifter, two-stage hoisting device, final election device and line translation controller; Each rank transformation device comprises one-level lifter, two-stage hoisting device and rank transformation controller.When carrying out the conversion of one-level row, column, when first order line translation proceeds to the 3rd row, begin to carry out the 1st step and the lifting computing of the 2nd step of rank transformation, line translation is simultaneously proceeded.But these are based on the correction of inventive concept and change still within claim protection range of the present invention.
Claims (5)
1. VLSI structure of wavelet transformation based on row is characterized in that comprising one-level line transformer and rank transformation device, intermediate buffer, multilevel wavelet coefficient o controller, external memory storage at least.Wherein:
Line transformer is used to carry out the wavelet transformation of line direction, and transform data is write in the intermediate buffer; The one-level line transformer carries out the wavelet transformation of first order line direction to the raw image data of input, and the low frequency sub-band LL coefficient of line transformer reaching or above grade two after to the previous stage wavelet transformation carries out the wavelet transformation of line direction again;
The rank transformation device is used for finishing the wavelet transformation of column direction from middle buffer sense data, and the wavelet coefficient that rank transformation obtains is outputed to multilevel wavelet coefficient o controller;
Intermediate buffer is used to cushion the output factor of line transformer and the intermediate object program that the rank transformation device produces;
Multilevel wavelet coefficient o controller is used for the coefficient of small echo rank transformations at different levels is carried out final election, buffer memory, and the LL sub-band coefficients of small echos at different levels outputs to next stage small echo line transformer, and all the other sub-band coefficients output to external memory storage in order;
External memory storage, each sub-band coefficients that is used to store the wavelet transformations at different levels that obtain after multilevel wavelet decomposes.
2. wavelet transformation structure according to claim 1, it is characterized in that line transformer comprises one-level lifter and line translation controller at least, each step that lifters at different levels are finished wavelet transformation promotes, the progression of this lifter is relevant with the wavelet transformation of employing, for 5/3 small echo, progression is 2, for 9/7 small echo, progression is 4, promptly need promote through level Four; The line translation controller is given pending data the processing of each lifter, control boundary extension and conversion coefficient is write intermediate buffer according to certain time sequence.
3. wavelet transformation structure according to claim 1, it is characterized in that each rank transformation device comprises one-level lifter and rank transformation controller at least, each step that lifters at different levels are finished wavelet transformation promotes, the progression of this lifter is relevant with the wavelet transformation of employing, for 5/3 small echo, progression is 2, for 9/7 small echo, progression is 4, promptly need promote through level Four; The rank transformation controller is given the processing of each lifter, control boundary extension with pending data according to certain time sequence and is read and write data from middle buffer.。
4. wavelet transformation structure according to claim 1, it is characterized in that intermediate buffer, comprise a plurality of fifo fifo memories, the N step that is used for being buffered in rank transformation promotes the intermediate data result that the computing one-level is produced to N-1 level lifter, to offer next step lifting computing.
5. wavelet transformation structure according to claim 1, it is characterized in that the multilevel wavelet o controller comprises wavelet coefficient final election device and wavelet coefficient buffer, wherein the wavelet coefficient buffer comprises output priority controller, read-write controller, data final election device, address generator and each sub-band coefficients corresponding cache space; Wavelet coefficient final election device carries out exporting after the final election to wavelet coefficients at different levels and useful signal thereof, wherein low frequency sub-band LL
1, LL
2... LL
N-1The data of subband and useful signal thereof output to two, three respectively ... N level line transformer, other each subband data and useful signal thereof all output to the wavelet coefficient buffer, and are stored among the FIFO of corresponding cache space; The output priority controller produces the control signal of read-write controller, data final election device and address generator respectively, and exports wavelet coefficients at different levels successively by wavelet coefficient priority order from high to low.
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| CN102289828A (en) * | 2011-06-10 | 2011-12-21 | 中国科学院空间科学与应用研究中心 | Wavelet transformation system and method for satellite borne image compression based on field programmable gate array (FPGA) |
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| CN101106719B (en) * | 2006-07-14 | 2013-03-27 | 索尼株式会社 | Wavelet transformation device, wavelet inverse transformation device and method, program, and recording medium |
| CN101404772B (en) * | 2008-11-19 | 2010-09-22 | 中国科学院光电技术研究所 | VLSI image compression encoder based on wavelet transformation |
| CN101754017B (en) * | 2008-12-08 | 2012-12-12 | 索尼株式会社 | Information processing apparatus and method |
| CN102289828A (en) * | 2011-06-10 | 2011-12-21 | 中国科学院空间科学与应用研究中心 | Wavelet transformation system and method for satellite borne image compression based on field programmable gate array (FPGA) |
| CN102289828B (en) * | 2011-06-10 | 2013-04-24 | 中国科学院空间科学与应用研究中心 | Wavelet transformation system and method for satellite borne image compression based on field programmable gate array (FPGA) |
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| CN104053011A (en) * | 2014-06-13 | 2014-09-17 | 哈尔滨工业大学 | Two-dimensional discrete inverse wavelet transform device applied to JPEG 2000 decoder |
| CN104053011B (en) * | 2014-06-13 | 2017-03-01 | 哈尔滨工业大学 | It is applied to the 2-d discrete wavelet inverse converter in JPEG2000 decoder |
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