CN1527404A - Film transistor structure with lightly doped drain area and its manufacture - Google Patents
Film transistor structure with lightly doped drain area and its manufacture Download PDFInfo
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- CN1527404A CN1527404A CNA031068561A CN03106856A CN1527404A CN 1527404 A CN1527404 A CN 1527404A CN A031068561 A CNA031068561 A CN A031068561A CN 03106856 A CN03106856 A CN 03106856A CN 1527404 A CN1527404 A CN 1527404A
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Abstract
The present invention discloses one kind of film transistor structure for planar display and its manufacture process. The structure includes the first film transistor in the drive circuit area of the planar display with grid conductor structure in the length equal to or greater than the length of the lightly doped drain area plus the length of the channel area; and the second film transistor set in the active matrix of the planar display and grid conductor structure in the length approximately equal the length of the channel area.
Description
Technical field
The present invention relates to a kind of thin-film transistor structure and manufacture method thereof, relate in particular to the thin-film transistor structure and the manufacture method thereof that are applied to tool light-doped drain region territory on the flat-panel screens.
Background technology
See also Fig. 1 (a) and 1 (b), it is the function block schematic diagram of a Thin Film Transistor-LCD, and it mainly is made up of two parts, and first is an active matrix 10, and second portion then is an one drive circuit 11.And in traditional amorphous silicon technology, active matrix 10 is independently finished on a glass substrate 1, and after drive circuit 11 must finish with the form of one or more integrated circuits in addition, be connected (shown in Fig. 1 (a)) with active matrix 10 by outside line 12 again.
But after the low temperature polycrystalline silicon technology is applied to the manufacture process of Thin Film Transistor-LCD, above-mentioned active matrix 10 just can same technology be finished on glass substrate 1 (shown in Fig. 1 (b)) simultaneously with drive circuit 11, and then realizes the improvement that cost reduces.
See also Fig. 2 (a) and (b), (c), (d), (e), (f), it finishes the step schematic diagram of the various thin-film transistor that is in respectively in active matrix and the drive circuit with low temperature polycrystalline silicon technology.Fig. 2 (a) expresses on glass substrate 2 in the laser tempering mode; under low temperature environment, form the structure of polysilicon layer 21; Fig. 2 (b) then expresses the ion that forms the N raceway groove and injects (boron ion for example; B+), wherein P channel thin-film transistor zone is protected by the formed mask 22 of photoresist.Subsequently again under the protection of finishing with gate mask that photoresist is formed 23, the ion that carries out source/drain region injects that (hydrogenation phosphonium ion for example PHx+), and then forms the source/drain region 24 of the N channel thin-film transistor shown in Fig. 2 (c).And after being both the formed mask of photoresist 22 and being removed with gate mask 23, define gate insulator 25 and gate metal structure 26 (for example finishing) again with molybdenum, and then be that the ion that mask carries out low concentration injects (phosphonium ion for example with this gate metal structure 26, P+), use the slight doped-drain structure of finishing in the N channel region 241, and can find out by Fig. 2 (d), the length of gate metal structure 26 is less than original gate mask 23, utilize this gap just definable go out this slight doped-drain structure 241.Fig. 2 (e) expresses then that (boron hydride ion for example, B2Hx+), wherein N channel thin-film transistor zone is protected by the formed mask 27 of photoresist in order to the ion injection that forms source/drain electrode in the P channel region.Then express the panel construction of having finished protective layer 28 and having formed contacting metal lead connector 29 as for Fig. 2 (f).
Owing to the N channel thin-film transistor can be because shorten the generation that raceway groove causes thermoelectronic effect, therefore mask count must be increased and processing step is set up slight doped-drain structure 241, and then suppress the influence that thermoelectronic effect produced, in order to the stability that increases element and reduce leakage current.But, in order to save mask count and processing step as far as possible, usually slight doped-drain structure 241 is all finished with self-aligned manner, and the slight doped-drain structure 241 that Gu Qisuo finishes will not have overlapping region (shown in Fig. 2 (d)) with the gate metal structure 26 of top.But, result according to reality shows, when 26 on the gate metal structure of slight doped-drain structure 241 and top has an overlapping region, the effect of improving of element stability will be best, produce a parasitic capacitance but so also will attach, and this parasitic capacitance can make this pixel when closing, and storage capacitors in the pixel cell and liquid crystal capacitance are produced a bias voltage, makes original voltage level-shift.And how in above-mentioned condition, to find out a preferred solution, be development main purpose of the present invention.
Summary of the invention
The present invention is a kind of thin-film transistor structure, be applied on the flat-panel screens, it comprises: a first film transistor, be arranged at the one drive circuit zone of this flat-panel screens, the length that the length of the transistorized gate conductor structure of this first film is equal to or greater than its light-doped drain region territory adds the length of channel region; And one second thin-film transistor, being arranged at an active matrix zone of this flat-panel screens, the length of the gate conductor structure of this second thin-film transistor approximates the length of its channel region.
According to above-mentioned conception, thin-film transistor structure of the present invention, this flat-panel screens that it was applied thereon is a LCD.
According to above-mentioned conception, thin-film transistor structure of the present invention, its this second thin-film transistor of this first film transistor AND gate is finished on same substrate.
Another aspect of the present invention is a kind of method for fabricating thin film transistor, is applied to a flat-panel screens, and it comprises the following steps: to provide a substrate; Form a polysilicon layer and define one first polysilicon structure and one second polysilicon structure in this substrate top; After in those polysilicon structures, forming the N channel region, on those polysilicon structures, respectively cover one first mask arrangement, and the part N channel region that exposes is carried out a slight dopant ion inject; Form length one second mask arrangement bigger again after removing this first mask arrangement on this first polysilicon structure than this first mask arrangement, and the part N channel region that exposes is carried out a severe dopant ion again inject, and then in this first polysilicon structure, form an at least one light-doped drain region territory and a severe doped source/drain region, and in this second polysilicon structure, form at least one severe doped source/drain region; And form a gate insulator and a gate conductor layer after removing those mask arrangements, and respectively this gate conductor layer above this first polysilicon structure and this second polysilicon structure is defined a first grid conductor structure and a second grid conductor structure, and the length of this first grid conductor structure is equal to or greater than the length that the length in corresponding this light-doped drain region territory adds this channel region, and the length of this second grid conductor structure approximates the length of corresponding this channel region.
According to above-mentioned conception, method for fabricating thin film transistor of the present invention wherein also comprises the following steps: to define one the 3rd polysilicon structure in the time of this first polysilicon structure of definition and this second polysilicon structure; In this first, second polysilicon structure, form before the N channel region, cover one the 3rd mask arrangement at the 3rd polysilicon structure; When respectively this gate conductor layer above this first polysilicon structure and this second polysilicon structure being defined a first grid conductor structure and a second grid conductor structure, this gate conductor layer in the 3rd polysilicon structure top defines one the 3rd gate conductor structure; And after covering one the 4th mask arrangement in the top of this first, second polysilicon structure, utilize the 3rd gate conductor structure to inject, and then form a P channel thin-film transistor for mask comes that the 3rd polysilicon structure is carried out the severe dopant ion.
According to above-mentioned conception, method for fabricating thin film transistor of the present invention, wherein the material of those mask arrangements is a photoresist.
According to above-mentioned conception, method for fabricating thin film transistor of the present invention, wherein this first polysilicon structure and this second polysilicon structure adhere to the one drive circuit zone and an active matrix zone in this flat-panel screens separately.
Another aspect of the present invention is a kind of method for fabricating thin film transistor, is applied to a flat-panel screens, and it comprises the following steps: to provide a substrate; Form a polysilicon layer in this substrate top; After in this polysilicon layer, forming the N channel region, on this polysilicon layer, cover a mask arrangement, and the part N channel region that exposes is carried out a slight dopant ion inject, and then form at least one light-doped drain region territory; Form a gate insulator and a gate conductor layer after removing this mask arrangement on this polysilicon layer, and this gate conductor layer is defined a gate conductor structure, and this gate conductor structure overlaps with this light-doped drain region territory partly; And utilize this gate conductor structure to inject for mask carries out a severe dopant ion again to this light-doped drain region territory of part of exposing, and then in this polysilicon layer, form at least one severe doped source/drain region, and the length of this gate conductor structure approximates the length that the length in remaining this light-doped drain region territory adds channel region.
According to above-mentioned conception, method for fabricating thin film transistor of the present invention, wherein the material of those mask arrangements is a photoresist.
According to above-mentioned conception, method for fabricating thin film transistor of the present invention, its this thin-film transistor of finishing belongs to the one drive circuit zone in this flat-panel screens.
Description of drawings
The present invention can be able to more in depth understand by following accompanying drawing and detailed description, among the figure:
Fig. 1 (a) and 1 (b) are the function block schematic diagrams of a Thin Film Transistor-LCD;
Fig. 2 (a), 2 (b), 2 (c), 2 (d), 2 (e) and 2 (f) are the step schematic diagrames of finishing the various thin-film transistor that is in respectively in active matrix and the drive circuit in the prior art with low temperature polycrystalline silicon technology;
Fig. 3 is the structural representation of Thin Film Transistor-LCD of the present invention;
Fig. 4 (a), 4 (b), 4 (c), 4 (d), 4 (e), 4 (f) and 4 (g) are the step schematic diagrames of finishing the first preferred embodiment of the invention of the thin-film transistor that is in two kinds of different structures in active matrix and the drive circuit respectively with low temperature polycrystalline silicon technology; And
Fig. 5 (a), 5 (b), 5 (c), 5 (d), 5 (e) and 5 (f) are the step schematic diagrames of second preferred embodiment of the invention.
Description of reference numerals in the accompanying drawing is as follows:
1 glass substrate, 10 active matrixs
11 drive circuits, 12 outside lines
2 glass substrate, 21 polysilicon layers
22 masks, 23 gate mask
24 sources/drain region 241 slight doped-drain structures
25 gate insulators, 26 gate metal structures
27 masks, 28 protective layers
29 contacting metal lead connectors, 30 slight doped-drain structures
31 gate metal structures, 32 slight doped-drain structures
33 gate metal structures, 4 glass substrate
41 polysilicon layers, 42 masks
43 gate mask, 431 photoresist gate mask
44 sources/drain region 441 slight doped-drain structures
442 slight doped-drain structure 45 gate insulators
46 gate metal structures, 47 masks
48 protective layers, 49 contacting metal lead connectors
5 glass substrate, 51 polysilicon layers
52 masks, 53 gate mask
54 gate insulators, 551 gate metal structures
552 gate metal structures, 56 sources/drain region
57 masks, 571 gate metal structures
58 masks, 59 sources/drain region
591 slight doped-drain structure 60 protective layers
61 contacting metal lead connectors
Embodiment
Be on a substrate, to finish simultaneously active matrix and drive circuit owing to make the advantage of Thin Film Transistor-LCD with the low temperature polycrystalline silicon technology.And as shown in the above description, there is double-edged influence the interstructural overlapping region of gate metal of slight doped-drain structure and top for element characteristic, can improve the element stability on the one hand, but make data voltage level produce drift but then because of attaching generation leakage current and parasitic capacitance.Yet active matrix has different requirements with drive circuit for the transistorized performance of its internal membrane, wherein the thin-film transistor in the active matrix is for the having relatively high expectations of voltage level, and the thin-film transistor in the drive circuit is having relatively high expectations for element stability then.Therefore, for meeting above-mentioned two kinds of circuit simultaneously for the different requirement of element characteristic, the present invention just develops the LCD Structure of thin film transistor schematic diagram that as shown in Figure 3, and from figure, can know and find out, be manufactured on the slight doped-drain structure 30 of the N channel thin-film transistor in the drive circuit area and 31 on the gate metal structure of top and will have overlapping areas, thus, can effectively improve the element stability of thin-film transistor in the drive circuit area, and the parasitic capacitance of deriving there is no too much influence for drive circuit.And in the active matrix zone, the slight doped-drain structure 32 of N channel thin-film transistor and 33 on the gate metal structure of top will not have overlapping areas, thus, can effectively suppress the influence of leakage current parasitic capacitance for voltage level offset.
See also Fig. 4 (a) again to 4 (g), it is a step schematic diagram of finishing the first preferred embodiment of the invention of the thin-film transistor that is in two kinds of different structures in active matrix and the drive circuit respectively with low temperature polycrystalline silicon technology.Fig. 4 (a) expression on the glass substrate 4 in the laser tempering mode; under low temperature environment, form the structure of polysilicon layer 41; Fig. 4 (b) then expresses the ion that forms the N raceway groove and injects (boron ion for example; B+), wherein P channel thin-film transistor zone is protected by the formed mask 42 of photoresist.Subsequently again under the protection of finishing with gate mask that photoresist is formed 43, carry out low concentration ion shown in Fig. 4 (c) inject (hydrogenation phosphonium ion for example, PHx+).Shown in Fig. 4 (d) then for after N channel thin-film transistor place in drive circuit forms a larger-size photoresist gate mask 431 again, the ion that carries out one source/drain region again injects (hydrogenation phosphonium ion for example, and then form the source/drain region 44 of N channel thin-film transistor as shown in the figure and the slight doped-drain structure 441 at the N channel thin-film transistor place in the drive circuit PHx+).And after being both the formed mask of photoresist 42 and being removed with gate mask 431, define gate insulator 45 and gate metal structure 46 (for example finishing) again with molybdenum, and then be that the ion that mask carries out low concentration injects (hydrogenation phosphonium ion for example with this gate metal structure 46, PHx+), use the slight doped-drain structure 442 of finishing N channel thin-film transistor in the active matrix, and can find out by Fig. 4 (e), the length of the gate metal structure 46 in the active matrix is less than original gate mask 43, utilize this gap just definable go out this slight doped-drain structure 442 in the active matrix.Fig. 4 (f) expresses then that (boron hydride ion for example, B2Hx+), wherein N channel thin-film transistor zone is protected by the formed mask 47 of photoresist in order to the ion injection that forms source/drain electrode in the P channel region.As for Fig. 4 (g), then express and finished protective layer 48 and the panel construction that forms contacting metal lead connector 49.And can know the schematic structure after finishing and find out, be manufactured between the gate metal structure of the slight doped-drain structure of the N channel thin-film transistor in the drive circuit area and top and will have overlapping areas, thus, can effectively improve the element stability of thin-film transistor in the drive circuit area, and the parasitic capacitance of deriving there is no too much influence for drive circuit.And in the active matrix zone, will not have overlapping areas between the slight doped-drain structure of N channel thin-film transistor and the gate metal structure of top, thus, can effectively suppress of the influence of leakage current parasitic capacitance for voltage level offset.
In addition, have the spirit of the N channel thin-film transistor manufacturing step of overlapping region according to above-mentioned slight doped-drain structure and its upper gate metal structure, the present invention also develops at a complementary metal-oxide semiconductor (CMOS) thin film transistor (TFT) separately and following technology.See also Fig. 5 (a) to 5 (f); it is the step schematic diagram of second preferred embodiment of the invention; Fig. 5 (a) expression on the glass substrate 5 in the laser tempering mode; under low temperature environment, form the structure of polysilicon layer 51; Fig. 5 (b) then expresses the ion that forms the N raceway groove and injects (boron ion for example; B+), wherein P channel thin-film transistor zone is protected by the formed mask 52 of photoresist.Subsequently again under the protection of finishing with gate mask that photoresist is formed 53, carry out low concentration ion shown in Fig. 5 (c) inject (hydrogenation phosphonium ion for example, PHx+).And be after forming a gate insulator 54 shown in Fig. 5 (d), form the gate metal structure 552 (for example available molybdenum is finished) of a larger-size gate metal structure 551 (for example available molybdenum is finished) and normal size again respectively at N channel thin-film transistor and P channel thin-film transistor place, and then the ion that carries out the source/drain region of P channel thin-film transistor injects (boron hydride ion for example, and then form the source/drain region 56 of P channel thin-film transistor as shown in the figure B2Hx+).And utilize the formed mask 57 of photoresist; define the gate metal structure 571 of normal size in the N channel thin-film transistor; and P channel thin-film transistor zone is protected by the formed mask 58 of photoresist; and then with the formed mask 57 of photoresist; 58 ions that carry out high concentration inject (hydrogenation phosphonium ion for example; PHx+); use source/drain region 59 and the slight doped-drain structure 591 of finishing the N channel thin-film transistor shown in Fig. 5 (e); and by finding out among the figure; the length of its gate metal structure 571 is greater than original gate mask 53, utilize this gap just definable go out this slight doped-drain structure 591 in the active matrix.Fig. 5 (f) then expresses and has finished protective layer 60 and the panel construction that forms contacting metal lead connector 61.And can know from above-mentioned explanation and to find out, it finishes the N channel thin-film transistor that slight doped-drain structure and its upper gate metal structure have the overlapping region with the method that does not increase the technology mask count, thus, can effectively improve the element stability of the thin-film transistor of finishing.
In sum, under the situation that does not break away from the scope that claims ask for protection, those skilled in the art can do various changes and retouching to the present invention.
Claims (10)
1. thin-film transistor structure, it is applied on the flat-panel screens, and it comprises:
One the first film transistor is arranged at the one drive circuit zone of this flat-panel screens, and the length that the length of the transistorized gate conductor structure of this first film is equal to or greater than its light-doped drain region territory adds the length of channel region; And
One second thin-film transistor is arranged at an active matrix zone of this flat-panel screens, and the length of the gate conductor structure of this second thin-film transistor approximates the length of its channel region.
2. thin-film transistor structure as claimed in claim 1, this flat-panel screens that it was applied thereon is a LCD.
3. thin-film transistor structure as claimed in claim 1, its this second thin-film transistor of this first film transistor AND gate is finished on same substrate.
4. a method for fabricating thin film transistor is applied to a flat-panel screens, and it comprises the following steps:
One substrate is provided;
Form a polysilicon layer and define one first polysilicon structure and one second polysilicon structure in this substrate top;
After in those polysilicon structures, forming the N channel region, on those polysilicon structures, respectively cover one first mask arrangement, and the part N channel region that exposes is carried out a slight dopant ion inject;
Form length one second mask arrangement bigger again after removing this first mask arrangement on this first polysilicon structure than this first mask arrangement, and the part N channel region that exposes is carried out a severe dopant ion again inject, and then in this first polysilicon structure, form an at least one light-doped drain region territory and a severe doped source/drain region, and in this second polysilicon structure, form at least one severe doped source/drain region; And
Form a gate insulator and a gate conductor layer after removing those mask arrangements, and respectively this gate conductor layer above this first polysilicon structure and this second polysilicon structure is defined a first grid conductor structure and a second grid conductor structure, and the length of this first grid conductor structure is equal to or greater than the length that the length in corresponding this light-doped drain region territory adds this channel region, and the length of this second grid conductor structure approximates the length of corresponding this channel region.
5. method for fabricating thin film transistor as claimed in claim 4 wherein also comprises the following steps:
In the time of this first polysilicon structure of definition and this second polysilicon structure, define one the 3rd polysilicon structure;
In this first, second polysilicon structure, form before the N channel region, cover one the 3rd mask arrangement at the 3rd polysilicon structure;
When respectively this gate conductor layer above this first polysilicon structure and this second polysilicon structure being defined a first grid conductor structure and a second grid conductor structure, this gate conductor layer in the 3rd polysilicon structure top defines one the 3rd gate conductor structure; And
After covering one the 4th mask arrangement in the top of this first, second polysilicon structure, utilize the 3rd gate conductor structure to inject, and then form a P channel thin-film transistor for mask comes that the 3rd polysilicon structure is carried out the severe dopant ion.
6. method for fabricating thin film transistor as claimed in claim 4, wherein the material of those mask arrangements is a photoresist.
7. method for fabricating thin film transistor as claimed in claim 4, wherein this first polysilicon structure and this second polysilicon structure adhere to the one drive circuit zone and an active matrix zone in this flat-panel screens separately.
8. a method for fabricating thin film transistor is applied to a flat-panel screens, and it comprises the following steps:
One substrate is provided;
Form a polysilicon layer in this substrate top;
After in this polysilicon layer, forming the N channel region, on this polysilicon layer, cover a mask arrangement, and the part N channel region that exposes is carried out a slight dopant ion inject, and then form at least one light-doped drain region territory;
Form a gate insulator and a gate conductor layer after removing this mask arrangement on this polysilicon layer, and this gate conductor layer is defined a gate conductor structure, and this gate conductor structure overlaps with this light-doped drain region territory partly; And
Utilize this gate conductor structure to inject for mask carries out a severe dopant ion again to this light-doped drain region territory of part of exposing, and then in this polysilicon layer, form at least one severe doped source/drain region, and the length of this gate conductor structure approximates the length that the length in remaining this light-doped drain region territory adds channel region.
9. method for fabricating thin film transistor as claimed in claim 8, wherein the material of those mask arrangements is a photoresist.
10. method for fabricating thin film transistor as claimed in claim 8, its this thin-film transistor of finishing belongs to the one drive circuit zone in this flat-panel screens.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031068561A CN100391008C (en) | 2003-03-05 | 2003-03-05 | Film transistor structure with lightly doped drain area and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031068561A CN100391008C (en) | 2003-03-05 | 2003-03-05 | Film transistor structure with lightly doped drain area and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1527404A true CN1527404A (en) | 2004-09-08 |
| CN100391008C CN100391008C (en) | 2008-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031068561A Expired - Fee Related CN100391008C (en) | 2003-03-05 | 2003-03-05 | Film transistor structure with lightly doped drain area and its manufacture |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113820894A (en) * | 2021-08-30 | 2021-12-21 | 厦门天马微电子有限公司 | Array substrate, mask plate, active structure preparation method and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3948034B2 (en) * | 1995-09-06 | 2007-07-25 | セイコーエプソン株式会社 | Semiconductor device, manufacturing method thereof, and active matrix substrate |
| US6362507B1 (en) * | 1999-04-20 | 2002-03-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical devices in which pixel section and the driver circuit are disposed over the same substrate |
| JP3643025B2 (en) * | 2000-10-20 | 2005-04-27 | シャープ株式会社 | Active matrix display device and manufacturing method thereof |
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2003
- 2003-03-05 CN CNB031068561A patent/CN100391008C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113820894A (en) * | 2021-08-30 | 2021-12-21 | 厦门天马微电子有限公司 | Array substrate, mask plate, active structure preparation method and display panel |
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| CN100391008C (en) | 2008-05-28 |
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