CN1518115A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1518115A
CN1518115A CNA2003101027253A CN200310102725A CN1518115A CN 1518115 A CN1518115 A CN 1518115A CN A2003101027253 A CNA2003101027253 A CN A2003101027253A CN 200310102725 A CN200310102725 A CN 200310102725A CN 1518115 A CN1518115 A CN 1518115A
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mentioned
supporting substrate
layer
semiconductor device
soi
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һ��ʦ¡־
一法师隆志
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

A semiconductor device on a semiconductor substrate, which provides for effective use of characteristics of the semiconductor substrate, is provided. A supporting substrate (1) having a crystal direction.

Description

Semiconductor device
Technical field
The semiconductor device that the present invention relates on semiconductor substrate, form.
Background technology
As one of conventional semiconductor device example, P channel MOS (Metal-oxide-semicondutor) transistor that forms is arranged on SOI (silicon on the insulator or the semiconductor on the insulator) substrate.
In the SOI substrate, supporting substrate, oxidation film layer and soi layers such as silicon substrate have been stacked gradually.In addition, the P channel MOS transistor has gate electrode, gate insulating film and P type source/leakage active layer.
Form the occasion of P channel MOS transistor on the SOI substrate, form the laminated construction of gate electrode and gate insulating film on the surface of soi layer, the position of the lower zone of the gate electrode in clipping soi layer forms source/leakage active layer.
The conventional semiconductor device generally is configured to make crystal orientation＜110 of channel direction and semiconductor wafer between the source/leakage of MOS transistor〉parallel.
But, by channel direction being configured to not and crystal orientation＜110〉parallel, and with crystal orientation＜100 parallel, can change characteristics of transistor.Specifically, known by means of channel direction being configured to and crystal orientation＜100〉parallel, that the current driving ability of P channel MOS transistor improves is about 15%, in addition, has also reduced short-channel effect (patent documentation 1 that will address with reference to the back).
The reason that current driving ability improves be since the hole in the crystal orientation＜100 mobility ratio in the crystal orientation＜110 height, the reason that short-channel effect reduces can think since boron in the crystal orientation＜100 diffusion coefficient value than in the crystal orientation＜110 little.
Therefore, form the occasion of P channel MOS transistor on the SOI substrate, its channel direction preferably also is configured to crystal orientation＜100 with soi layer〉parallel., for example can adopt so that the crystal orientation of supporting substrate＜110 for this reason〉with crystal orientation＜100 of the soi layer of face side the SOI substrate that forms of corresponding to mode, and form device such as P channel MOS transistor in its surface.
In the occasion of (100) wafer, { 110} is a cleavage surface to crystal face.Therefore, if make crystal orientation＜100 of soi layer with wafer〉and crystal orientation＜110 of the wafer of supporting substrate as one man fit, then when the cleavage of experimental study, can cut apart entire wafer along the cleavage surface of the wafer of the most supporting substrate that has occupied wafer thickness.So, have and can both on supporting substrate, expose crystal orientation＜110〉the cross section, on soi layer, expose crystal orientation＜100 again〉the advantage in cross section.
This crystal orientation＜100 that make soi layer〉with crystal orientation＜110 of supporting substrate 1 consistent technology for example has record in patent documentation 1 or patent documentation 2.
In addition, as the former technical literature information relevant non-patent literature 1～3 is arranged with the application's invention.
Make crystal orientation＜110 of supporting substrate〉with crystal orientation＜100 of soi layer though as one man the SOI substrate of Xing Chenging also having room for improvement owing to reasons such as current driving ability raising are suitable for the formation of P channel MOS transistor aspect the current driving ability of raising P channel MOS transistor.
Patent documentation 1
The spy opens the 2002-134374 communique
Patent documentation 2
Te Kaiping 7-335511 communique
Non-patent literature 1
People such as Y.Hirano, " Bulk-Layout-Compatible 0.18 μ m SOI-CMOS Tech nologyUsing Body-Fixed Partial Trench Isolation (PTI) ", (U.S.), IEEE 1999 SOIconf., p.131-132
Non-patent literature 2
People such as S.Maeda, " Suppression of Delay Time Instability on Freq uencyusing Field Shield Isolation Technology for Deep Sub-Mi cron SOI Circuits ", (U.S.), IEDM, 1996, p.129～132
Non-patent literature 3
People such as L.-J.Huang, " Carrier Mobility Enhancement in Strained Si-On-Insulator Fabricated by Wafer Bonding ", (U.S.), 2001 Symposium onVLSI Technology, p.57-58
Summary of the invention
Therefore, problem of the present invention is: the semiconductor device that the current driving ability that can improve the MOS transistor that forms on semiconductor substrate is provided.
The described invention in the 1st aspect is to possess: the SOI substrate that has stacked gradually supporting substrate, oxidation film layer and SOI (semiconductor on the insulator) layer; And be included in the gate insulating film that forms on the above-mentioned soi layer, the gate electrode that forms on the above-mentioned gate insulating film, in above-mentioned soi layer at MIS (metal-insulator semiconductor) transistor of the source/leakage active layer that forms with above-mentioned gate electrode adjoining position place, removed the semiconductor device of the part that is positioned at the transistorized below of above-mentioned MIS at least in the above-mentioned supporting substrate.
Description of drawings
Fig. 1 is the vertical view that the semiconductor device of embodiment 1 is shown.
Fig. 2 is the profile that the semiconductor device of embodiment 1 is shown.
Fig. 3 is the vertical view of change example that the semiconductor device of embodiment 1 is shown.
Fig. 4 is the profile of change example that the semiconductor device of embodiment 1 is shown.
Fig. 5 is the vertical view of manufacture method of change example that the semiconductor device of embodiment 1 is shown.
Fig. 6 is the profile of manufacture method of change example that the semiconductor device of embodiment 1 is shown.
Fig. 7 is the vertical view of manufacture method of change example that the semiconductor device of embodiment 1 is shown.
Fig. 8 is the profile of manufacture method of change example that the semiconductor device of embodiment 1 is shown.
Fig. 9 is the vertical view of change example that the semiconductor device of embodiment 1 is shown.
Figure 10 is the profile that the semiconductor device of embodiment 2 is shown.
Figure 11 is the profile that the semiconductor device of embodiment 3 is shown.
Figure 12 is the profile that the semiconductor device of embodiment 4 is shown.
Figure 13 is the profile that the semiconductor device of embodiment 4 is shown.
Figure 14 is the profile that the semiconductor device of embodiment 4 is shown.
Embodiment
Embodiment 1
In the present embodiment, in the crystal orientation that makes supporting substrate＜110〉with crystal orientation＜100 of soi layer consistent and form the P channel MOS transistor on the SOI substrate that forms, by means of removing the supporting substrate of its underpart, channel formation region is applied strain.
The semiconductor device of present embodiment has been shown in Fig. 1 and Fig. 2.In addition, Fig. 2 is the figure that the section of the cutting line II-II among Fig. 1 is shown.
This semiconductor device is the P channel MOS transistor, and it forms on the surface of the SOI substrate that has stacked gradually soi layers 3 such as supporting substrates such as silicon substrate 1, oxidation film layer 2 and silicon layer.In addition, this P channel MOS transistor possesses gate electrode 12, gate insulating film 11 and P type source/leakage active layer 5.
The laminated construction of gate electrode 12 and gate insulating film 11 forms on the surface of soi layer 3, and P type source/leakage active layer 5 is forming with gate electrode 12 adjoining positions from the plane in soi layer 3.In addition, the outer edge of source/leakage active layer 5 is by element isolation zone 4 regulations of part isolated form.
Side wall insulating film 13 forms in the side of gate electrode 12 and gate insulating film 11, and silicide area 12b, 5a form on the surface of gate electrode 12 and source/leakage active layer 5 respectively.In addition,, form the part in the gate electrode 12 thinner from plane and source/leakage active layer 5 adjacency in order to shorten the length of grid, and the extension 12a that will be used for being connected with contact bolt (not shown) form broad.In addition, the part of gate electrode 12 belows is the lower (N of concentration in the soi layer 3 -) N type body layer 3a.
As depicted in figs. 1 and 2, in this semiconductor device, get rid of the part that is positioned at the MOS transistor below in the supporting substrate 1, form peristome HL1.
Like this,, get rid of the part that is positioned at P channel MOS transistor below in the supporting substrate 1 of SOI substrate, form peristome according to present embodiment.Form peristome by means of a part of getting rid of supporting substrate 1, the upper strata oxidation film layer 2 and the soi layer 3 of this part applied strain stress.Therefore, can apply strain, can improve the mobility of charge carrier rate in the raceway groove the soi layer 3 of the channel formation region that comprises MOS transistor.
In addition, below the mobility of charge carrier rate that improves in the raceway groove when soi layer 3 is applied strain is described.
Existence with the face side in the soi layer (channel formation region) as the lattice constant silicon strained channel layer bigger, with the remainder (adjacent area of channel formation region) of soi layer MOS transistor (with reference to non-patent literature 3) as the structure of the lattice constant germanium-silicon layer bigger than silicon than common silicon.The MOS transistor of so-called strained-channel structure that Here it is.
Be subjected to the influence of the lattice configuration of adjacent area in the value of the lattice constant of the silicon layer of also big than the silicon epitaxially grown face side in adjacent area of lattice constant, the value of the lattice constant that is substantially equal to the adjacent area of becoming has the lattice constant bigger than common silicon.Therefore, the silicon layer of face side is in the state that bears tensile stress (strain stress).So, find that the mobility of charge carrier rate in the raceway groove rises the MOS transistor of the characteristic that can be improved.
In the occasion of present embodiment, form peristome by a part of getting rid of supporting substrate 1, the upper strata oxidation film layer 2 and the soi layer 3 of this part applied strain stress.Thus, certainly obtain the identical effect of MOS transistor with above-mentioned strained-channel structure.
In addition, in the SOI of present embodiment substrate, supporting substrate 1 departs from mutually with the crystal orientation of soi layer 3.Thus, can make the cleavage surface of supporting substrate 1 different, can make the SOI substrate be difficult to isolate with the cleavage surface of soi layer 3.
In addition, owing to characteristics of transistor changes with stress, so Stress Control is very important.Particularly in the present embodiment, form peristome, the upper strata oxidation film layer 2 and the soi layer 3 of this part applied strain stress, so need more high-precision Stress Control by a part of getting rid of supporting substrate 1.By means of using this SOI substrate, the current driving ability in can improving the P channel MOS transistor, can also reduce the uncertain stress that in each manufacturing process, produces, the control that improves counter stress.
In addition, the structure of Fig. 1 and Fig. 2 can easily form.For example, in the facing surfaces of supporting substrate 1, on oxidation film layer 2 surface far away, form photoresist,, form the etching mask of peristome HL1 its body plan figure.Then, carry out etching, remove photoresist, obtain the structure of Fig. 1 and Fig. 2.
In addition, Fig. 3 and Fig. 4 are the change examples of the structure of Fig. 1 and Fig. 2.Fig. 4 is the figure that the section of the cutting line IV-IV among Fig. 3 is shown.In this becomes example, on the supporting substrate 1 under source/the leakages active layer 5 of P channel MOS transistor, be provided with and the size of source/leakage active layer 5 is roughly the same is seen as rectangular peristome HL2 from the plane.In addition, expose and the end face that is centered around the supporting substrate 1 around it all is (111) face to peristome HL2.
Because (111) face is and crystal orientation＜110〉parallel face, so if the etching that (111) are showed out can be provided with crystal orientation＜110 that have with supporting substrate 1 on supporting substrate 1〉peristome on parallel limit.Therefore, the removal part of supporting substrate 1 rectangle can be formed from the plane, can the Min. of the fixed size of part will be removed according to the size of MOS transistor in necessity.
The etching that (111) are showed out for example also can be carried out with following method.
As shown in Figure 5 and Figure 6, at first, on oxidation film layer 2 surface far away, the position under MOS transistor forms photoresist RM2, and the little opening OP1 of open area ratio peristome HL2 is set on photoresist RM2 in the facing surfaces of supporting substrate 1.In addition, Fig. 6 is the figure that the section of the hatching line VI-VI among Fig. 5 is shown.
Then, carry out wet etching with strong alkali solutions such as potassium hydroxide solutions.Like this, as shown in Figure 7 and Figure 8, on supporting substrate 1, formed by peristome HL2 as the end face regulation of the supporting substrate 1 of (111) face.Because potassium hydroxide solution etching oxidation silicon fiml hardly, thus 2 one-tenth of oxidation film layers etch stop layer.In addition, Fig. 8 is the figure that the section of the cutting line VIII-VIII among Fig. 7 is shown.
, get rid of photoresist RM2, can obtain Fig. 3 and structure shown in Figure 4 thereafter.
In addition, except that potassium hydroxide solution, also can use NaOH, tetramethylammonium hydroxide strong alkali solutions such as (Tetramethyl Ammonium Hydroxide).
Fig. 9 is illustrated in the figure that has source/leakage active layer 5 between 2 adjacent MOS transistor and form the situation of a plurality of MOS transistor.At this moment, can be to form peristome HL2 on the surface also at supporting substrate 1.Peristome HL2 also can be to cover whole form formation of total and non-total any source/leakages active layer 5.
Embodiment 2
Present embodiment is the change example of the semiconductor device of embodiment 1, is to get rid of supporting substrate 1 fully, and replaces the semiconductor device of the other supporting substrate of having fitted on the interlayer dielectric that is formed on the MOS transistor.
Figure 10 illustrates the semiconductor device of present embodiment.In this semiconductor device, supporting substrate 1 is removed fully.Therefore, 2 one-tenth of oxidation film layers the bottom surface of semiconductor device.Then, form the 1st to the 3rd interlayer dielectric IL1～IL3 that covers the MOS transistor that is formed on the soi layer 3 again.
In addition, in the 2nd interlayer dielectric IL2, form the 2nd layer of wiring LN1, in the 3rd interlayer dielectric IL3, formed the 3rd layer of wiring LN2.Also have, the 2nd layer of wiring LN1 utilizes contact bolt PG1 to be connected with source/leakage active layer 5, and the 3rd layer of wiring LN2 is connected with the 2nd layer of wiring LN1 through contact bolt PG2.
In this semiconductor device, the new other supporting substrate 100 of on the surface of the 3rd interlayer dielectric IL3 of the superiors, having fitted.About this supporting substrate 100, also can make its crystal orientation＜110〉with crystal orientation＜100 of soi layer 3 as one man fit.In addition, can adopt silicon substrate to other supporting substrate 100, but be not necessarily limited to this, so long as have the substrate of supporting role, for example the substrate beyond the semiconductor such as glass substrate, plastic base can adopt.
In the occasion of present embodiment, 1 support function of bearing in the manufacturing process of supporting substrate, it will be removed by etching or CMP (chemico-mechanical polishing) etc. after new other supporting substrate 100 is fitted.
In the present embodiment owing to get rid of supporting substrate 1 fully, so to MOS transistor and near the heat dispersion of heat of generation good.In addition, owing to possess other supporting substrate 100, so there is not the problem of intensity aspect yet.
Embodiment 3
Present embodiment also is the change example of the semiconductor device of embodiment 1, is the semiconductor device that forms metal film in the mode on surface that covering comprises the supporting substrate 1 of the end face that exposes to peristome HL1 or HL2.
Figure 11 is the figure that present embodiment is described according to the structure of Fig. 4.As shown in figure 11, in the present embodiment, in the facing surfaces of supporting substrate 1, on oxidation film layer 2 surface far away and on end face and oxidation film layer 2 that peristome HL2 exposes, for example form the metal film MT1 of Au, Al, W, Cu etc. by methods such as metal evaporations.
Like this, by means of forming metal film MT1, can realize to MOS transistor and near the good semiconductor device of heat dispersion of heat of generation.In addition, if form metal film MT1 under hundreds of ℃ high temperature, metal film MT1 shrinks severely than oxidation film layer 2 and soi layer 3 when turning back to room temperature.This is because the thermal coefficient of expansion of the metal film MT1 cause bigger than oxidation film layer 2 and soi layer 3.Therefore, this also has the effect that soi layer 3 is applied strain, can improve the mobility of charge carrier rate in the raceway groove.
Embodiment 4
Present embodiment is the change example of embodiment 3, the semiconductor device that to be the metal film MT1 that will be provided with on oxidation film layer 2 surface far away in the facing surfaces of supporting substrate 1 be electrically connected with the part of source/leakage active layer 5 in the soi layer 3.
Figure 12 shows the semiconductor device of present embodiment.Figure 12 illustrates two groups of MOS transistor.And, all be that an end that connects the contact bolt PG3 of oxidation film layer 2 is connected with for example source of source/leakage active layer 5 in their any one group.In addition, contact bolt PG3 forms in oxidation film layer 2 by means of following method: utilize photoetching technique and lithographic technique behind a part of opening of supporting substrate 1 side with oxidation film layer 2, metal film is imbedded.Then, the other end of contact bolt PG3 is connected with metal film MT1.
In view of the above, metal film MT1 is for example applied power supply potential Vdd, the current potential of the source/leakage active layer 5 of MOS transistor can be fixed.In addition, if on the whole surface of supporting substrate 1, form metal film MT1, then the resistance value of metal film MT1 can be forced down, thereby can not only suppress power consumption but also carry out current potential and fix.
In addition, the thought of present embodiment can certainly be applied to the semiconductor device of embodiment 2.Figure 13 illustrates the structure of the semiconductor device of this occasion.At this moment because supporting substrate 1 got rid of fully, 2 one-tenth of oxidation film layers the bottom surface of semiconductor device, form so metal film MT1 becomes on the surface of oxidation film layer 2.But the formation of contact bolt PG3 in addition etc. is identical with the occasion of Figure 12.
In addition, also can replace and source/leakage active layer 5 direct-connected contact bolt PG3, adopt directly not to be connected, but wait the contact bolt that source/leakage active layer 5 is electrically connected with metal film MT1 through wiring with source/leakage active layer 5.Contact bolt PG4 shown in Figure 14 is exactly the one example.This contact bolt PG4 connects oxidation film layer 2, element isolation zone 4a and the 1st interlayer dielectric IL1 and is connected with the 2nd layer of wiring LN1.In addition, element isolation zone 4a is not the part isolated form, and becomes complete isolated form.
The effect of invention
According to the described invention in the 1st aspect, get rid of in the supporting substrate of SOI substrate at least position Part in the transistorized below of MIS. Therefore, can be to comprising the transistorized channel shape of MIS Become the soi layer in district to apply strain, can improve the mobility of the carrier in the raceway groove.

Claims (6)

1. semiconductor device is characterized in that:
Possess:
Stacked gradually the SOI substrate of supporting substrate, oxidation film layer and SOI (semiconductor on the insulator) layer; And
Be included in the gate insulating film that forms on the above-mentioned soi layer, the gate electrode that forms on the above-mentioned gate insulating film, in above-mentioned soi layer with above-mentioned gate electrode below MIS (metal-insulator semiconductor) transistor of source/leakage active layer of forming of part adjoining position
Get rid of the part that is positioned at the transistorized below of above-mentioned MIS at least in the above-mentioned supporting substrate, thereby formed peristome.
2. semiconductor device as claimed in claim 1 is characterized in that:
Above-mentioned peristome is surrounded by 4 end faces of above-mentioned supporting substrate, and above-mentioned end face exposes to above-mentioned peristome, and above-mentioned end face all is (111) face.
3. semiconductor device as claimed in claim 1 is characterized in that:
Do not possess above-mentioned supporting substrate, possess and replace also:
Cover the transistorized interlayer dielectric of above-mentioned MIS; And
Be fitted in the other supporting substrate on the above-mentioned interlayer dielectric.
4. semiconductor device as claimed in claim 1 is characterized in that:
Also possesses the metal film that the mode of the above-mentioned oxidation film layer that exposes with the surface that covers the end face that exposes to above-mentioned peristome comprising of above-mentioned supporting substrate with to above-mentioned peristome forms.
5. semiconductor device as claimed in claim 4 is characterized in that:
Also possesses the above-mentioned oxidation film layer of perforation, with the above-mentioned MIS contact bolt that transistorized above-mentioned source/the leakage active layer is electrically connected with above-mentioned metal film.
6. semiconductor device as claimed in claim 1 is characterized in that:
Depart from mutually in the crystal orientation of above-mentioned supporting substrate and above-mentioned soi layer.
CNA2003101027253A 2003-01-22 2003-10-23 Semiconductor device Pending CN1518115A (en)

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US20040150013A1 (en) 2004-08-05
KR20040067786A (en) 2004-07-30

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