CN1516895A - Barrier enhancement process for copper interconnects - Google Patents

Barrier enhancement process for copper interconnects Download PDF

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Publication number
CN1516895A
CN1516895A CNA028119231A CN02811923A CN1516895A CN 1516895 A CN1516895 A CN 1516895A CN A028119231 A CNA028119231 A CN A028119231A CN 02811923 A CN02811923 A CN 02811923A CN 1516895 A CN1516895 A CN 1516895A
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technology
enhancement layer
layer
metal
alloy
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C・H・Jb
C·H·Jb
吲捣
I·伊瓦诺夫
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Mattson Technology Inc
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Mattson Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Abstract

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co-W-P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10 ANGSTROM to 100 ANGSTROM and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

Description

The barrier layer enhanced process that is used for copper-connection
Technical field
The present invention relates to the film enhancement layer is deposited to electrochemical deposition technology on the existing ultra-thin barrier layer, with repair-deficiency with strengthen the barrier properties on barrier layer.The film enhancement layer of deposit is as the barrier layer and be used for the inculating crystal layer of copper-plating technique subsequently.
The cross reference of related application
It is No.60/298 that the application requires the sequence number of application on July 25 calendar year 2001,138 U.S.. the priority of provisional application.
Background technology
Need metallization pattern to interconnect a plurality of devices to form integrated circuit.For the chip of high performance ultra-large integrated (ULSI), use six layers or more metal layers usually.Along with manufactory reduce device size and with more device package on integrated circuit (IC) chip, expectation increases the quantity of layer.
The signal propagation delays that the performance of integrated circuit (IC) chip is interconnected limits, and signal propagation delays also is called " RC " and postpones.In order to improve circuit speed, importantly reduce R (resistance) and the C (electric capacity) relevant with interconnection.Recently, having introduced the aluminum metallization in the manufacturing of copper metallization replacement integrated circuit, is that copper has lower resistivity and higher current-carrying capacity owing to compare with aluminium.
Copper metallization requires the processing different with aluminum metallization.Composition after the metal deposit that replaces using in the interconnection of formation aluminium uses mosaic technology to form copper-connection usually.In mosaic technology, conductor fig at first etches in the dielectric material.Then, fill etched figure with copper.Use chemico-mechanical polishing (" CMP ") step on zone (field), to remove excessive copper then.Use via hole (via-hole) to connect the different metal layer that forms in the integrated circuit (IC) chip.When filling and polishing conductor lines figure and via hole figure respectively, technology often is called " singly inlaying " technology.When filling conductor lines and via hole figure simultaneously, technology often is called " dual damascene " technology.
In known mosaic technology, before introducing copper, barrier layer and inculating crystal layer are deposited on the patterned dielectric layer surface successively.Need the barrier layer to be diffused in the device region to prevent copper.When contact silicon, copper loss has been gone bad the silicon device operation.Usually, select thin refractory metal or metal nitride as the barrier layer.Representational barrier material comprises tantalum, tantalum nitride, tungsten, tungsten nitride, titanium and titanium nitride.Need inculating crystal layer to be provided as nuclear location for electrochemical deposition reaction provides conductibility also to electroplate for copper subsequently.Usually, thin copper layer is deposited on the barrier layer as inculating crystal layer.
One of the most important requirement that is used for the mosaic technology of copper is to make the copper complete filling of deposit have the etched line of high depth-width ratio (degree of depth is calculated divided by width gauge) or the little geometry in groove and hole.Often use the electroplating technology cement copper to be because (" CVD " compares, and this technology has slit filling capacity preferably with physical vapor deposition (" PVD ") or chemical vapor deposition.Because the electrochemical copper depositing technics can be deposited on more copper in the little groove rather than outside the groove, therefore usually be called " the efficient filling " (super-filling).
The PVD technology for example comprises various evaporations and sputtering technology, for example DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, ion plating or ionized metal plasma sputter.PVD technology is because their anisotropy and directionality produce non-conformal deposited usually.The CVD technology comprises CVD, low pressure chemical vapor deposition, high pressure CVD and the metallorganic CVD of for example hot CVD, plasma enhancing.CVD technology usually produces the deposit of conformal, has homogeneous thickness basically on the whole surface of bottom surface that comprises zone (field) and opening and side.
At present, main by PVD technology barrier layer and inculating crystal layer as sputter and ionization sputter.Often, vacuum is not destroyed to avoid surface contamination simultaneously in barrier layer and inculating crystal layer deposit successively in two different vacuum chambers.Key factor in this depositing technics is film thickness, particularly etching line or the side of groove and path and the film thickness on the bottom in the etched figure.PVD technology forms thin rete usually in these etched figures rather than on the smooth zone (field) of dielectric material.The step coverage existing problems of these layers.Film must continuous and zero defect.Hole in the barrier layer or defective will endanger the integrated level of device.Produce hole or defective in the copper film that hole in the inculating crystal layer or defective will cause electroplating.
Improve step and cover, now attempted using CVD technology barrier layer and inculating crystal layer.But the output of CVD technology does not have PVD technology good, and CVD technology is more expensive.Often have relatively poor adhesiveness, higher impurity and relatively poor crystal orientation by the copper seed layer of CVD technology deposit, when extra copper electrochemical have problems when being deposited on this inculating crystal layer.Sometimes PVD is used in combination with CVD, passes through the independent copper seed layer of PVD technology deposit thus on the copper seed layer of CVD deposit, has further increased the expense of CVD technology.Therefore, has above-indicated step covering problem but still preferred although be used for the PVD technology of the barrier layer of copper-connection and inculating crystal layer.
Improvement to the PVD deposition technology does not solve with the barrier layer of PVD deposit and the film covering problem of inculating crystal layer.Along with device size continues to reduce, the barrier film on the trenched side-wall need be less than 10 nanometers in the future.The technology that needs combination is to satisfy stricter requirement.
U.S. patent No.6, the method that 136,707 second copper seed layer of having instructed first copper seed layer that CVD is formed and PVD to form make up.U.S. patent No.6,197,181 disclose the method that will be made up by first copper seed layer of alkali plating solution electrolytic deposition and second copper seed layer that forms by PVD.The treatment step that these two patents all need to add is to obtain PVD copper seed layer adhesiveness preferably.Yet, the problem that bad interface causes between the barrier layer that disclosed method can not fix the defect in these patents or barrier layer and the copper seed layer.
Therefore, manufacturing industry is sought cement copper electrochemically to high depth-width ratio hole and the better method in the groove.
Summary of the invention
The present invention includes the technology and the equipment that metal are applied to microelectronic workpiece, wherein microelectronic workpiece comprises the surface that is provided with one or more micro groove structures in it.More generally, microelectronic workpiece is a semiconductor wafer, for example silicon or gallium arsenide semiconductor wafer.Preferably, metal forms metal layer for the copper that use is inlayed or dual-damascene technics applies in groove in semiconductor wafer or hole or path or other structure.
In technology according to the present invention, step comprises:
(a) on the surface of microelectronic workpiece, be included on the wall of micro groove structure and form the barrier layer;
(b) form enhancement layer on the barrier layer, wherein said enhancement layer is made up of metal alloy; And
(c) plate metal on the enhancement layer to fill the micro groove structure.
Preferably, use as electrochemical deposition technologies such as electroless plating or electroplating technology formation enhancement layer, thickness is below 100 , most preferably from 10 to 100 .Alternatively, can use CVD or PVD technology to form enhancement layer.
In one embodiment, enhancement layer is formed by copper alloy, for example Cu-Al, Cu-Mg and/or Cu-Zn.In another embodiment, enhancement layer is by forming as bianry alloy compositions such as Co-P or as ternary alloy three-partalloy compositions such as Co-W-P.
Enhancement layer is covering barrier layer conformally, or even covering barrier layer has the place of seam, discontinuous part or grain boundary defects.For semiconductor silicon wafer, the barrier layer can be titanium, titanium nitride or other known barrier material.Enhancement layer has conductibility, is enough to allow depositing metal on it, preferably copper.After this, for example remove excessive metal from (field) surface, zone by chemico-mechanical polishing.Metals deposited is stayed in the microelectronic structure, forms the interconnection or the metal layer that need.
In another embodiment, processing step comprises:
(a) on the surface of microelectronic workpiece, be included on the wall of micro groove structure and form the barrier layer;
(b) enhancement layer of formation metal alloy on the barrier layer;
(c) on enhancement layer, form inculating crystal layer; And
(d) on enhancement layer plated metal to fill the micro groove structure.
In this alternative, inculating crystal layer comprises another layer of metal alloy, comprises that perhaps plan is deposited on the metal level in the microelectronic structure.Thus, inculating crystal layer can be copper alloy, as two bianry alloys of Co-P, or as the ternary alloy three-partalloy of Co-W-P.The inculating crystal layer that forms preferably has the thickness of 50 to 500 .
Can in the production line that comprises a plurality of equipment of making microelectronic circuit or parts, carry out mosaic technology, wherein use the one or more equipment in a plurality of equipment that the interconnect metallization in the mosaic technology is applied to the surface of microelectronic workpiece, be used to form microelectronic circuit or parts.Microelectronic workpiece is preferably silicon or gallium arsenide semiconductor wafer, has formed porose in wafer or groove or path, is suitable for metallization and forms microelectronic circuit or parts.At this moment, one or more devices comprise:
Use first depositing technics that the barrier layer is applied to the device on microelectronic workpiece surface, wherein the barrier layer is not suitable for the body electrochemical deposition of interconnect metallization usually;
Use second depositing technics that enhancement layer is applied to device on the barrier layer, wherein enhancement layer is formed by alloy composite, and this alloy composite is applicable to that usually electrochemistry applies the predetermined thickness metal subsequently, represents the body portion of interconnect metallization; And
On enhancement layer, electrochemically apply the device of metal.
Preferably, the device that applies enhancement layer is the equipment that is used for electrochemical deposition, for example is used for the equipment of electroless plating or electroplating technology.Perhaps, the device that applies enhancement layer can be the equipment that is used for CVD or PVD technology.The device that applies enhancement layer can conformally be applied to enhancement layer on the barrier layer, and the thickness that applies is 100 or still less, preferred 10 are thick to 100 .Enhancement layer is preferably by forming as bianry alloys such as copper alloys such as Cu-Al, Cu-Mg and/or Cu-Zn, Co-P or as ternary alloy three-partalloys such as Co-W-P, perhaps even can be the mixture of these alloys.
The device of electrochemistry metallizing to the enhancement layer can coated copper as the metal in the mosaic technology.In case copper is incorporated in metal layer or the microelectronic structure, provide surface, zone (field) to remove the device of part copper metal from microelectronic workpiece.Preferably, the device of removing the part copper metal comprises chemical-mechanical polisher.
This equipment can comprise first Room that applies the barrier layer and second Room that applies enhancement layer.In addition, optionally additional inculating crystal layer and copper metallization can be deposited on the workpiece, and in second Room to the workpiece coating enhancement layer.Thus, carry out enhancement layer, the optional electrochemical deposition of inculating crystal layer and copper metal in can the single chamber in equipment.
Description of drawings
Can understand the present invention by reference fully below in conjunction with detailed description and claims of accompanying drawing.
Figure 1A is the profile that etching forms the semiconductor silicon wafer of medium figure groove;
Figure 1B is the profile with semiconductor silicon wafer of groove, shows wherein that deposit is from the teeth outwards equably as the thin barrier layer of tantalum or tantalum nitride;
Fig. 2 is the profile with semiconductor silicon wafer of groove, and groove has been coated with thin barrier layer, and shows the blemish that is formed on usually in the thin barrier layer;
Fig. 2 A is the amplification profile of semiconductor silicon wafer groove of the coating of Fig. 2;
Fig. 3 is the profile with semiconductor silicon wafer of groove, at first applies thin barrier layer according to the present invention, then for stopping enhancement layer.
Fig. 4 is the profile of the semiconductor silicon wafer of Fig. 3, has wherein used electrochemical deposition method to fill groove with copper;
Fig. 5 is the profile of the semiconductor silicon wafer of Fig. 4, and polished surface is removed after the excessive copper, has stayed the damascene conductor figure of finishing;
Fig. 6 is the profile of alternative, and wherein semiconductor silicon wafer has the damascene conductor figure of finishing, and wherein uses before the copper filling groove, and copper seed layer has been deposited on and has stopped on the enhancement layer; And
Fig. 7 is the deposition rate of Co-W-P alloy barrier reinforcing membrane on the barrier layer of the 75C that represents with dust and curve chart with the time of minute representing.
Embodiment
With reference to Figure 1A, as SiO 2Comprise the semiconductor wafer shown in the local amplification profile Deng silicon dielectric material 10.Dielectric material 10 has the groove 12 that forms in it.
The surface-coated of dielectric material 10 has thin barrier layer 14, preferably uses PVD technology, yet also can use CVD technology.The barrier layer is generally thin refractory metal or metal nitride.Representational barrier material comprises tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride and titanium silicon nitride and other ternary nitride.
Shown in Figure 1A, barrier layer 14 forms pantostrat or the film that does not have discontinuous part or blemish.For this barrier layer, this is desirable surface coverage.Barrier layer thickness on the interior smooth lower surface of zone (field) and groove usually from 100 to 500 , depend on the depth-width ratio and the opening size of groove, the barrier layer thickness on the trenched side-wall is 100 or still less.For the very little opening with big degree of depth, the deposited film on the sidewall is too thin, produces discontinuous part and blemish.
Next with reference to figure 2 and 2A, be formed on barrier layer 16 on the dielectric material 10 and be presented at and have the surface coverage defective in the groove 12.As shown in Figure 2, barrier layer 16 does not have covering groove sidewall and flat bottom surface glossily.Seam 18 is stayed the barrier layer not to be had in the bottom corner of overwrite media material.Discontinuous part 20 is along the fracture part in the covering of sidewall.The intrinsic adhering blemish of copper seed layer that on the barrier layer, forms subsequently in the mosaic technology that crystal boundary 22 is represented to have suppressed known.
Most of faults in the barrier layer relate to the copper diffusion of crystal boundary, are because the crystal boundary diffusion is far away from the diffusion by body." filling " crystal boundary has the barrier layer of grain boundary defects with raising barrier properties is now proposed.For example, usually in oxygen atmosphere annealing TiN barrier layer with at crystal boundary place " filling " oxygen.The other method that reduces the diffusion of crystal boundary place is that other material is added in the initial barrier metal to form alloy.The material that adds accumulates in crystal boundary (also being called isolation) usually.Regulate alloy composite to satisfy different requirements.For example, the copper alloy as Cu-Sn, Cu-Zn, Cu-Mg or Cu-Al can be used as the diffusion barrier that is used for copper.The metal that adds in the alloy accumulates in the crystal boundary surface or the scope of freedom usually, and has prevented that copper atom from moving.Existing known Cu-Sn and Cu-Zn are by anti-block diffusion the having slowed down aerial corrosion of Cu.Recently, having studied and used Cu-Al as the diffusion barrier that is used for copper, is because Al often isolates at crystal boundary place and surface.
One of the most difficult problem is to make between the inculating crystal layer of initial barrier layer and deposit on it to obtain good adhesiveness during the deposit inculating crystal layer on the barrier layer.The copper of plating adheres to barrier layer surface relatively poorly.The seed crystal enhancement layer why Here it is introduces in the U.S. patent 6,197,181 directly is not deposited on the barrier layer, but is deposited to the reason on the copper seed layer of PVD deposit.The CVD copper seed layer that directly is deposited on the barrier layer also has relatively poor adhesiveness, often uses the PVD copper seed layer to improve the adhesiveness of CVD copper seed layer.
Use CVD technology, PVD technology or electrochemical process deposition preventing enhancement layer 24 conformally on barrier layer 16, preferred electrochemical process or CVD technology.Most preferably as the electrochemical deposition technology of electroless plating and electroplating technology.Stop that enhancement layer is thick to 100 from 10 , and covered in the barrier layer 16 defective that exists, for example stitch 18, discontinuous part 20 and crystal boundary 22.Stop that enhancement layer has good step and covers.
Stop that enhancement layer 24 is intended to strengthen the performance of diffusion impervious layer and the inculating crystal layer of conduct copper-plating technique subsequently.Thus, the deposition preventing enhancement layer can need independent copper seed layer.
Stop that enhancement layer is by adhering to the barrier layer and also allowing copper-plated subsequently conducting metal to form.Preferably, stop that enhancement layer is formed by a kind of binary or the ternary metal alloy material that are selected among following: cobalt-phosphorus (Co-P) or cobalt-tungsten-phosphorus (Co-W-P); , perhaps can be the mixture of these alloys perhaps by copper alloy as Cu-Al, Cu-Mg, Cu-Sn and/or Cu-Zn.
Preferably, deposit is as stopping that the alloy material of enhancement layer is Co-W-P.The electrochemical deposition technology that is used for Co-W-P at length is presented in the U.S. patent 5,695,810, here is incorporated herein by reference.The common deposition temperature that is used for this alloy is from room temperature to 90 ℃.Yet at 90 ℃, the electrolytic aqueous solution by evaporation loss can be too much, preferred thus as 75 ℃ lower temperature.For given deposit chemical substance, can control the thickness of the Co-W-P of deposit by control deposition time and temperature.In electrochemical deposition technology, the Co-W-P alloy material is deposited on the TiN barrier layer, as shown in Figure 6 to the speed of 200 with about 100 of per minute under 75 ℃.
Preferred electrochemical deposition technology deposition preventing enhancement layer.The hardware compatibility that has used in the copper-plating technique of this technology and standard and the copper-connection manufacturing.Therefore by new process chamber is installed, be used to stop that the new electrochemical deposition technology of enhancement layer can easily combine with existing plating equipment in existing systems.Suitable bonding apparatus constitutes the Figure 12 that is presented in the U.S. patent 6,017,437.In conjunction with device structure reduced equipment cost, and allow simple wafer technique flow sequence.After the deposition preventing enhancement layer, wafer can directly be sent to the copper facing assembly to finish plating technic, does not leave plating equipment simultaneously.
Stop that enhancement layer 24 is coated in after the barrier layer 16, etched figure is filled with electro-coppering shown in Figure 4.After this, preferably by chemico-mechanical polishing (" CMP ") step, excessive copper is removed on polishing area (field) surface.Damascene conductor graphical display complete after the CMP is in Fig. 5.
In alternative, two individual courses can be deposited on the barrier layer.As shown in Figure 6, the amplification profile of medium wafer material 10 has formation groove 12 within it.Barrier layer 16 is deposited on the smooth bottom and the sidewall surfaces of groove, and has crystal boundary, seam and the discontinuous part of pointing out among the last embodiment in it.Stop that enhancement layer 24 is coated on the barrier layer 16 once more.After this, inculating crystal layer 28 is formed on and stops on the enhancement layer 24.Inculating crystal layer 28 can form alloy, for example is used to form to stop enhancement layer 24 or can be the copper metal.Though can pass through CVD, PVD or electrochemical deposition technology deposit inculating crystal layer, preferred electrochemical deposition technology.In addition, more economical be to use compatible depositing technics, and preferred in identical equipment deposition preventing enhancement layer and inculating crystal layer.
Example
Example 1
The single enhancement layer that stops is deposited on the TiN barrier layer.The TiN barrier layer sputters on the silica dioxide medium material.Clean and wash the TiN barrier layer surface then.Deposit thin electroless plating Co-W-P layer on the TiN barrier layer then.The electrolyte that is used for deposit is made up of following:
CoClx6H 2O 30g/l
(NH4) 2WO 4 10g/l
Na 3C 6H 5O 7xH 2O 80g/l
NaH 2PO 2xH 2O 20g/l
Be adjusted to pH=9.5 with KOH
Deposition temperature is 75 ℃, about 1 minute of deposition time.The film of deposit (about 100 ) has good scattering nature, and successfully is used as the inculating crystal layer of copper-plating technique subsequently.
Example 2
The tantalum barrier layer of sputter is coated to the silica dioxide medium substrate.Because existing known directly Co-W-P being deposited to has a spot of adhesiveness on the tantalum, so the cobalt of sputter thin layer (about 100 ) is to tantalum surface.Then, by electroless plating at about 1 minute Co-W-P layer of 75 ℃ of deposits to the Co surface of sputter.The film (about 200 ) of combination obtains satisfied adhesiveness.The copper Direct Electroplating is to the Co-W-P layer then.In this example, the Co layer is for stopping enhancement layer, and Co-W-P is for being used for copper-plated inculating crystal layer.
This example shows according to a second embodiment of the present invention: (1) can use two different layers---stop enhancement layer and inculating crystal layer; And (2) use different deposition technology deposition preventing enhancement layer and inculating crystal layer.
Show the present invention by DETAILED DESCRIPTION OF THE PREFERRED and example.Can carry out multiple change to form and details in technical staff's the ability in the art.Therefore, the present invention must be weighed by claims, rather than the description of example or preferred embodiment.

Claims (61)

  1. One kind with washing to the technology of microelectronic workpiece, microelectronic workpiece comprises the surface that is provided with one or more micro groove structures in it, this technology may further comprise the steps:
    (d) on the surface of microelectronic workpiece, be included on the wall of micro groove structure and form the barrier layer;
    (e) form enhancement layer on the barrier layer, wherein said enhancement layer is made up of metal alloy; And
    (f) plate metal on the enhancement layer to fill the micro groove structure.
  2. 2. according to the technology of claim 1, wherein use electrochemical deposition technology to form enhancement layer.
  3. 3. according to the technology of claim 2, wherein electrochemical deposition technology is selected from electroless plating and electroplating technology
  4. 4. according to the technology of claim 1, wherein use CVD technology to form enhancement layer.
  5. 5. according to the technology of claim 1, wherein use PVD technology to form enhancement layer.
  6. 6. according to the technology of claim 1, wherein the thickness of enhancement layer is 100 or still less.
  7. 7. according to the technology of claim 1, wherein the thickness of enhancement layer is formed and has the thickness range of 10 to 100 .
  8. 8. according to the technology of claim 1, wherein there are seam, discontinuous part or grain boundary defects in the barrier layer that so forms, and enhancement layer covering barrier layer conformally wherein.
  9. 9. according to the technology of claim 1, wherein enhancement layer is formed by copper alloy.
  10. 10. according to the technology of claim 9, wherein copper alloy is selected from the mixture of Cu-Al, Cu-Mg, Cu-Zn, Cu-Sn and these alloys thereof.
  11. 11. according to the technology of claim 1, wherein enhancement layer is formed by the bianry alloy composition.
  12. 12. according to the technology of claim 11, wherein alloy is Co-P.
  13. 13. according to the technology of claim 1, wherein enhancement layer is formed by the ternary alloy three-partalloy composition.
  14. 14. according to the technology of claim 13, wherein alloy is Co-P-W.
  15. 15. according to the technology of claim 1, the metal that wherein is electroplated onto on the enhancement layer is a copper.
  16. 16. the technology according to claim 1 also comprises:
    (e) remove part metals from the surface of microelectronic workpiece.
  17. 17., wherein remove by chemico-mechanical polishing according to the technology of claim 16.
  18. 18. according to the technology of claim 1, wherein microelectronic workpiece is silicon or gallium arsenide semiconductor wafer.
  19. 19. metal layer that the technology that adopts claim 1 forms in microelectronic workpiece.
  20. 20. one kind with washing to the technology of microelectronic workpiece, microelectronic workpiece comprises the surface that is provided with one or more micro groove structures in it, this technology comprises:
    (a) on the surface of microelectronic workpiece, be included on the wall of micro groove structure and form the barrier layer;
    (b) enhancement layer of formation metal alloy on the barrier layer;
    (c) on enhancement layer, form inculating crystal layer; And
    (d) on enhancement layer plated metal to fill the micro groove structure.
  21. 21., wherein use electrochemical deposition technology to form enhancement layer according to the technology of claim 20.
  22. 22. according to the technology of claim 21, wherein electrochemical deposition technology is selected from electroless plating and electroplating technology.
  23. 23., wherein use CVD technology to form enhancement layer according to the technology of claim 20.
  24. 24., wherein use PVD technology to form enhancement layer according to the technology of claim 20.
  25. 25. according to the technology of claim 20, wherein the thickness of enhancement layer is 100 or still less.
  26. 26. according to the technology of claim 20, wherein the thickness of enhancement layer is the thickness ranges of 10 to 100 .
  27. 27. according to the technology of claim 20, wherein there are seam, discontinuous part or grain boundary defects in the barrier layer that so forms, and enhancement layer covering barrier layer conformally wherein.
  28. 28. according to the technology of claim 20, wherein enhancement layer is formed by copper alloy.
  29. 29. according to the technology of claim 28, wherein copper alloy is selected from the mixture of Cu-Al, Cu-Mg, Cu-Zn, Cu-Sn and these alloys thereof.
  30. 30. according to the technology of claim 20, wherein enhancement layer is formed by the bianry alloy composition.
  31. 31. according to the technology of claim 30, wherein alloy is Co-P.
  32. 32. according to the technology of claim 20, wherein enhancement layer is formed by the ternary alloy three-partalloy composition.
  33. 33. according to the technology of claim 32, wherein alloy is Co-P-W.
  34. 34. according to the technology of claim 20, the metal that wherein is electroplated onto on the enhancement layer is a copper.
  35. 35. the technology according to claim 20 also comprises:
    (e) remove part metals from the surface of microelectronic workpiece.
  36. 36., wherein remove by chemico-mechanical polishing according to the technology of claim 35.
  37. 37. according to the technology of claim 20, wherein microelectronic workpiece is silicon or gallium arsenide semiconductor wafer
  38. 38. metal layer that the technology that adopts claim 20 forms in microelectronic workpiece.
  39. 39. in the production line that comprises a plurality of equipment of making microelectronic circuit or parts, use one or more equipment of a plurality of equipment in mosaic technology, interconnect metallization to be applied to the surface of microelectronic workpiece, be used to form microelectronic circuit or parts, one or more equipment comprise:
    Use first depositing technics that the barrier layer is applied to the device on microelectronic workpiece surface, wherein the barrier layer is not suitable for the body electrochemical deposition of interconnect metallization usually;
    Use second depositing technics that enhancement layer is applied to device on the barrier layer, wherein enhancement layer is formed by alloy composite, and this alloy composite is applicable to that usually electrochemistry applies the predetermined thickness metal subsequently, represents the body portion of interconnect metallization; And
    On enhancement layer, electrochemically apply the device of metal.
  40. 40. according to the production line of claim 39, the device that wherein applies enhancement layer is the equipment that is used for electrochemical deposition.
  41. 41. according to the production line of claim 40, the device that wherein applies enhancement layer is selected from the electrochemical deposition technology of electroless plating and electroplating technology.
  42. 42. according to the production line of claim 39, the device that wherein applies enhancement layer is the device that is used for CVD technology.
  43. 43. according to the production line of claim 39, the device that wherein applies enhancement layer is the device that is used for PVD technology.
  44. 44. according to the production line of claim 39, the device that wherein applies enhancement layer can conformally be coated to enhancement layer on the barrier layer, the thickness of coating is 100 or still less.
  45. 45. according to the production line of claim 39, wherein enhancement layer is formed by a kind of metal alloy that is selected from Cu-Al, Cu-Mg, Cu-Zn, Cu-Sn, Co-P and Co-W-P and their mixture thereof.
  46. 46. according to the production line of claim 39, wherein on enhancement layer the device of electrochemistry metallizing can coated copper as metal.
  47. 47. the production line according to claim 39 also comprises:
    Remove the device of part metals from the surface of microelectronic workpiece.
  48. 48. according to the production line of claim 47, the device of wherein removing the part copper metal comprises chemical-mechanical polisher.
  49. 49. according to the production line of claim 39, wherein microelectronic workpiece is silicon or gallium arsenide semiconductor wafer.
  50. 50. one kind is applied to the lip-deep device of the microelectronic workpiece that is used to form microelectronic circuit or parts with interconnect metallization, comprises in mosaic technology:
    Use first depositing technics that the barrier layer is coated to the device on microelectronic workpiece surface, wherein the barrier layer is not suitable for the body electrochemical deposition of interconnect metallization usually;
    Use second depositing technics that enhancement layer is coated to device on the barrier layer, wherein enhancement layer is formed by alloy composite, and this alloy composite is applicable to that usually electrochemistry applies the predetermined thickness metal subsequently, represents the body portion of interconnect metallization; And
    The device of metallizing electrochemically on enhancement layer.
  51. 51. according to the device of claim 50, the device that wherein applies enhancement layer is the equipment that is used for electrochemical deposition.
  52. 52. according to the device of claim 51, the device that wherein applies enhancement layer is selected from the electrochemical deposition technology of electroless plating and electroplating technology.
  53. 53. according to the device of claim 51, wherein electrochemical deposition equipment comprise a chamber, one or more electrode, one or more negative electrode and connect one or more electrodes and one or more negative electrode to the treatment fluid of microelectronic workpiece.
  54. 54. according to the device of claim 53, wherein treatment fluid is the electrolyte that is used for electro-coppering or metal alloy, metal alloy is selected from Cu-Al, Cu-Mg, Cu-Zn, Cu-Sn, Co-P and Co-W-P and their mixture thereof.
  55. 55. according to the device of claim 50, the device that wherein applies enhancement layer can conformally be coated to enhancement layer on the barrier layer, the thickness of coating is 100 or still less.
  56. 56. according to the device of claim 50, wherein enhancement layer is formed by a kind of metal alloy that is selected from Cu-Al, Cu-Mg, Cu-Zn, Cu-Sn, Co-P and Co-W-P.
  57. 57. according to the device of claim 50, wherein on enhancement layer the device of electrochemistry metallizing can coated copper as metal.
  58. 58. according to the device of claim 50, it is first indoor that the device that wherein applies the barrier layer is positioned at, it is indoor that the device that applies enhancement layer is positioned at equipment second.
  59. 59. according to the device of claim 50, the device that wherein applies enhancement layer is positioned at the first indoor of equipment, it is indoor that the device that applies metal on enhancement layer is positioned at equipment second.
  60. 60. according to the device of claim 50, the device that wherein applies enhancement layer is first indoor, the device that applies metal on enhancement layer is included in the first indoor same apparatus of equipment.
  61. 61. according to the device of claim 50, wherein microelectronic workpiece is silicon or gallium arsenide semiconductor wafer.
CNA028119231A 2001-06-14 2002-06-14 Barrier enhancement process for copper interconnects Pending CN1516895A (en)

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